i965/fs: Make the register allocation class_sizes[] choice static.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs.h
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #pragma once
29
30 #include "brw_shader.h"
31
32 extern "C" {
33
34 #include <sys/types.h>
35
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/uniforms.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/prog_optimize.h"
42 #include "program/register_allocate.h"
43 #include "program/sampler.h"
44 #include "program/hash_table.h"
45 #include "brw_context.h"
46 #include "brw_eu.h"
47 #include "brw_wm.h"
48 #include "brw_shader.h"
49 }
50 #include "glsl/glsl_types.h"
51 #include "glsl/ir.h"
52
53 class bblock_t;
54 namespace {
55 class acp_entry;
56 }
57
58 enum register_file {
59 BAD_FILE,
60 ARF,
61 GRF,
62 MRF,
63 IMM,
64 FIXED_HW_REG, /* a struct brw_reg */
65 UNIFORM, /* prog_data->params[reg] */
66 };
67
68 class fs_reg {
69 public:
70 /* Callers of this ralloc-based new need not call delete. It's
71 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
72 static void* operator new(size_t size, void *ctx)
73 {
74 void *node;
75
76 node = ralloc_size(ctx, size);
77 assert(node != NULL);
78
79 return node;
80 }
81
82 void init();
83
84 fs_reg();
85 fs_reg(float f);
86 fs_reg(int32_t i);
87 fs_reg(uint32_t u);
88 fs_reg(struct brw_reg fixed_hw_reg);
89 fs_reg(enum register_file file, int reg);
90 fs_reg(enum register_file file, int reg, uint32_t type);
91 fs_reg(class fs_visitor *v, const struct glsl_type *type);
92
93 bool equals(const fs_reg &r) const;
94
95 /** Register file: ARF, GRF, MRF, IMM. */
96 enum register_file file;
97 /**
98 * Register number. For ARF/MRF, it's the hardware register. For
99 * GRF, it's a virtual register number until register allocation
100 */
101 int reg;
102 /**
103 * For virtual registers, this is a hardware register offset from
104 * the start of the register block (for example, a constant index
105 * in an array access).
106 */
107 int reg_offset;
108 /** Register type. BRW_REGISTER_TYPE_* */
109 int type;
110 bool negate;
111 bool abs;
112 bool sechalf;
113 struct brw_reg fixed_hw_reg;
114 int smear; /* -1, or a channel of the reg to smear to all channels. */
115
116 /** Value for file == IMM */
117 union {
118 int32_t i;
119 uint32_t u;
120 float f;
121 } imm;
122 };
123
124 static const fs_reg reg_undef;
125 static const fs_reg reg_null_f(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_F);
126 static const fs_reg reg_null_d(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_D);
127
128 class fs_inst : public backend_instruction {
129 public:
130 /* Callers of this ralloc-based new need not call delete. It's
131 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
132 static void* operator new(size_t size, void *ctx)
133 {
134 void *node;
135
136 node = rzalloc_size(ctx, size);
137 assert(node != NULL);
138
139 return node;
140 }
141
142 void init();
143
144 fs_inst();
145 fs_inst(enum opcode opcode);
146 fs_inst(enum opcode opcode, fs_reg dst);
147 fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0);
148 fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
149 fs_inst(enum opcode opcode, fs_reg dst,
150 fs_reg src0, fs_reg src1,fs_reg src2);
151
152 bool equals(fs_inst *inst);
153 int regs_written();
154 bool overwrites_reg(const fs_reg &reg);
155 bool is_tex();
156 bool is_math();
157
158 fs_reg dst;
159 fs_reg src[3];
160 bool saturate;
161 int conditional_mod; /**< BRW_CONDITIONAL_* */
162
163 int mlen; /**< SEND message length */
164 int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
165 uint32_t texture_offset; /**< Texture offset bitfield */
166 int sampler;
167 int target; /**< MRT target. */
168 bool eot;
169 bool header_present;
170 bool shadow_compare;
171 bool force_uncompressed;
172 bool force_sechalf;
173 uint32_t offset; /* spill/unspill offset */
174
175 /** @{
176 * Annotation for the generated IR. One of the two can be set.
177 */
178 const void *ir;
179 const char *annotation;
180 /** @} */
181 };
182
183 class fs_visitor : public backend_visitor
184 {
185 public:
186
187 fs_visitor(struct brw_wm_compile *c, struct gl_shader_program *prog,
188 struct brw_shader *shader);
189 ~fs_visitor();
190
191 fs_reg *variable_storage(ir_variable *var);
192 int virtual_grf_alloc(int size);
193 void import_uniforms(fs_visitor *v);
194
195 void visit(ir_variable *ir);
196 void visit(ir_assignment *ir);
197 void visit(ir_dereference_variable *ir);
198 void visit(ir_dereference_record *ir);
199 void visit(ir_dereference_array *ir);
200 void visit(ir_expression *ir);
201 void visit(ir_texture *ir);
202 void visit(ir_if *ir);
203 void visit(ir_constant *ir);
204 void visit(ir_swizzle *ir);
205 void visit(ir_return *ir);
206 void visit(ir_loop *ir);
207 void visit(ir_loop_jump *ir);
208 void visit(ir_discard *ir);
209 void visit(ir_call *ir);
210 void visit(ir_function *ir);
211 void visit(ir_function_signature *ir);
212
213 void swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler);
214
215 fs_inst *emit(fs_inst inst);
216
217 fs_inst *emit(enum opcode opcode);
218 fs_inst *emit(enum opcode opcode, fs_reg dst);
219 fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0);
220 fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
221 fs_inst *emit(enum opcode opcode, fs_reg dst,
222 fs_reg src0, fs_reg src1, fs_reg src2);
223
224 int type_size(const struct glsl_type *type);
225 fs_inst *get_instruction_generating_reg(fs_inst *start,
226 fs_inst *end,
227 fs_reg reg);
228
229 bool run();
230 void setup_paramvalues_refs();
231 void assign_curb_setup();
232 void calculate_urb_setup();
233 void assign_urb_setup();
234 bool assign_regs();
235 void assign_regs_trivial();
236 int choose_spill_reg(struct ra_graph *g);
237 void spill_reg(int spill_reg);
238 void split_virtual_grfs();
239 void setup_pull_constants();
240 void calculate_live_intervals();
241 bool opt_algebraic();
242 bool opt_cse();
243 bool opt_cse_local(bblock_t *block, exec_list *aeb);
244 bool opt_copy_propagate();
245 bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
246 bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
247 bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block);
248 bool register_coalesce();
249 bool register_coalesce_2();
250 bool compute_to_mrf();
251 bool dead_code_eliminate();
252 bool remove_dead_constants();
253 bool remove_duplicate_mrf_writes();
254 bool virtual_grf_interferes(int a, int b);
255 void schedule_instructions();
256 void fail(const char *msg, ...);
257
258 void push_force_uncompressed();
259 void pop_force_uncompressed();
260 void push_force_sechalf();
261 void pop_force_sechalf();
262
263 void generate_code();
264 void generate_fb_write(fs_inst *inst);
265 void generate_pixel_xy(struct brw_reg dst, bool is_x);
266 void generate_linterp(fs_inst *inst, struct brw_reg dst,
267 struct brw_reg *src);
268 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
269 void generate_math1_gen7(fs_inst *inst,
270 struct brw_reg dst,
271 struct brw_reg src);
272 void generate_math2_gen7(fs_inst *inst,
273 struct brw_reg dst,
274 struct brw_reg src0,
275 struct brw_reg src1);
276 void generate_math1_gen6(fs_inst *inst,
277 struct brw_reg dst,
278 struct brw_reg src);
279 void generate_math2_gen6(fs_inst *inst,
280 struct brw_reg dst,
281 struct brw_reg src0,
282 struct brw_reg src1);
283 void generate_math_gen4(fs_inst *inst,
284 struct brw_reg dst,
285 struct brw_reg src);
286 void generate_discard(fs_inst *inst);
287 void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
288 void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
289 bool negate_value);
290 void generate_spill(fs_inst *inst, struct brw_reg src);
291 void generate_unspill(fs_inst *inst, struct brw_reg dst);
292 void generate_pull_constant_load(fs_inst *inst, struct brw_reg dst,
293 struct brw_reg index,
294 struct brw_reg offset);
295 void generate_mov_dispatch_to_flags();
296
297 void emit_dummy_fs();
298 fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
299 fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
300 glsl_interp_qualifier interpolation_mode,
301 bool is_centroid);
302 fs_reg *emit_frontfacing_interpolation(ir_variable *ir);
303 fs_reg *emit_general_interpolation(ir_variable *ir);
304 void emit_interpolation_setup_gen4();
305 void emit_interpolation_setup_gen6();
306 fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
307 bool is_rect, int sampler, int texunit);
308 fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
309 fs_reg shadow_comp, fs_reg lod, fs_reg lod2);
310 fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
311 fs_reg shadow_comp, fs_reg lod, fs_reg lod2);
312 fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
313 fs_reg shadow_comp, fs_reg lod, fs_reg lod2);
314 fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
315 fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
316 void emit_minmax(uint32_t conditionalmod, fs_reg dst,
317 fs_reg src0, fs_reg src1);
318 bool try_emit_saturate(ir_expression *ir);
319 bool try_emit_mad(ir_expression *ir, int mul_arg);
320 void emit_bool_to_cond_code(ir_rvalue *condition);
321 void emit_if_gen6(ir_if *ir);
322 void emit_unspill(fs_inst *inst, fs_reg reg, uint32_t spill_offset);
323
324 void emit_fragment_program_code();
325 void setup_fp_regs();
326 fs_reg get_fp_src_reg(const prog_src_register *src);
327 fs_reg get_fp_dst_reg(const prog_dst_register *dst);
328 void emit_fp_alu1(enum opcode opcode,
329 const struct prog_instruction *fpi,
330 fs_reg dst, fs_reg src);
331 void emit_fp_alu2(enum opcode opcode,
332 const struct prog_instruction *fpi,
333 fs_reg dst, fs_reg src0, fs_reg src1);
334 void emit_fp_scalar_write(const struct prog_instruction *fpi,
335 fs_reg dst, fs_reg src);
336 void emit_fp_scalar_math(enum opcode opcode,
337 const struct prog_instruction *fpi,
338 fs_reg dst, fs_reg src);
339
340 void emit_fp_minmax(const struct prog_instruction *fpi,
341 fs_reg dst, fs_reg src0, fs_reg src1);
342
343 void emit_fp_sop(uint32_t conditional_mod,
344 const struct prog_instruction *fpi,
345 fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
346
347 void emit_color_write(int target, int index, int first_color_mrf);
348 void emit_fb_writes();
349 bool try_rewrite_rhs_to_dst(ir_assignment *ir,
350 fs_reg dst,
351 fs_reg src,
352 fs_inst *pre_rhs_inst,
353 fs_inst *last_rhs_inst);
354 void emit_assignment_writes(fs_reg &l, fs_reg &r,
355 const glsl_type *type, bool predicated);
356 void resolve_ud_negate(fs_reg *reg);
357 void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
358
359 struct brw_reg interp_reg(int location, int channel);
360 int setup_uniform_values(int loc, const glsl_type *type);
361 void setup_builtin_uniform_values(ir_variable *ir);
362 int implied_mrf_writes(fs_inst *inst);
363
364 const struct gl_fragment_program *fp;
365 struct brw_wm_compile *c;
366
367 /* Delayed setup of c->prog_data.params[] due to realloc of
368 * ParamValues[] during compile.
369 */
370 int param_index[MAX_UNIFORMS * 4];
371 int param_offset[MAX_UNIFORMS * 4];
372
373 int *virtual_grf_sizes;
374 int virtual_grf_count;
375 int virtual_grf_array_size;
376 int *virtual_grf_def;
377 int *virtual_grf_use;
378 bool live_intervals_valid;
379
380 /* This is the map from UNIFORM hw_reg + reg_offset as generated by
381 * the visitor to the packed uniform number after
382 * remove_dead_constants() that represents the actual uploaded
383 * uniform index.
384 */
385 int *params_remap;
386
387 struct hash_table *variable_ht;
388 fs_reg frag_depth;
389 fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
390 unsigned output_components[BRW_MAX_DRAW_BUFFERS];
391 fs_reg dual_src_output;
392 int first_non_payload_grf;
393 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
394 int max_grf;
395 int urb_setup[FRAG_ATTRIB_MAX];
396
397 fs_reg *fp_temp_regs;
398 fs_reg *fp_input_regs;
399
400 /** @{ debug annotation info */
401 const char *current_annotation;
402 const void *base_ir;
403 /** @} */
404
405 bool failed;
406 char *fail_msg;
407
408 /* Result of last visit() method. */
409 fs_reg result;
410
411 fs_reg pixel_x;
412 fs_reg pixel_y;
413 fs_reg wpos_w;
414 fs_reg pixel_w;
415 fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
416 fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
417 fs_reg reg_null_cmp;
418
419 int grf_used;
420
421 int force_uncompressed_stack;
422 int force_sechalf_stack;
423
424 class bblock_t *bblock;
425 };
426
427 bool brw_do_channel_expressions(struct exec_list *instructions);
428 bool brw_do_vector_splitting(struct exec_list *instructions);
429 bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);