src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31
  32 extern "C" {
  33
  34 #include <sys/types.h>
  35
  36 #include "main/macros.h"
  37 #include "main/shaderobj.h"
  38 #include "main/uniforms.h"
  39 #include "program/prog_parameter.h"
  40 #include "program/prog_print.h"
  41 #include "program/prog_optimize.h"
  42 #include "util/register_allocate.h"
  43 #include "program/sampler.h"
  44 #include "program/hash_table.h"
  45 #include "brw_context.h"
  46 #include "brw_eu.h"
  47 #include "brw_wm.h"
  48 #include "brw_shader.h"
  49 #include "intel_asm_annotation.h"
  50 }
  51 #include "glsl/glsl_types.h"
  52 #include "glsl/ir.h"
  53
  54 #define MAX_SAMPLER_MESSAGE_SIZE 11
  55
  56 struct bblock_t;
  57 namespace {
  58    struct acp_entry;
  59 }
  60
  61 namespace brw {
  62    class fs_live_variables;
  63 }
  64
  65 class fs_inst;
  66 class fs_visitor;
  67
  68 class fs_reg : public backend_reg {
  69 public:
  70    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  71
  72    void init();
  73
  74    fs_reg();
  75    explicit fs_reg(float f);
  76    explicit fs_reg(int32_t i);
  77    explicit fs_reg(uint32_t u);
  78    fs_reg(struct brw_reg fixed_hw_reg);
  79    fs_reg(enum register_file file, int reg);
  80    fs_reg(enum register_file file, int reg, enum brw_reg_type type);
  81    fs_reg(enum register_file file, int reg, enum brw_reg_type type, uint8_t width);
  82    fs_reg(fs_visitor *v, const struct glsl_type *type);
  83
  84    bool equals(const fs_reg &r) const;
  85    bool is_valid_3src() const;
  86    bool is_contiguous() const;
  87
  88    fs_reg &apply_stride(unsigned stride);
  89    /** Smear a channel of the reg to all channels. */
  90    fs_reg &set_smear(unsigned subreg);
  91
  92    /**
  93     * Offset in bytes from the start of the register.  Values up to a
  94     * backend_reg::reg_offset unit are valid.
  95     */
  96    int subreg_offset;
  97
  98    fs_reg *reladdr;
  99
 100    /**
 101     * The register width.  This indicates how many hardware values are
 102     * represented by each virtual value.  Valid values are 1, 8, or 16.
 103     * For immediate values, this is 1.  Most of the rest of the time, it
 104     * will be equal to the dispatch width.
 105     */
 106    uint8_t width;
 107
 108    /**
 109     * Returns the effective register width when used as a source in the
 110     * given instruction.  Registers such as uniforms and immediates
 111     * effectively take on the width of the instruction in which they are
 112     * used.
 113     */
 114    uint8_t effective_width;
 115
 116    /** Register region horizontal stride */
 117    uint8_t stride;
 118 };
 119
 120 static inline fs_reg
 121 retype(fs_reg reg, enum brw_reg_type type)
 122 {
 123    reg.fixed_hw_reg.type = reg.type = type;
 124    return reg;
 125 }
 126
 127 static inline fs_reg
 128 byte_offset(fs_reg reg, unsigned delta)
 129 {
 130    switch (reg.file) {
 131    case BAD_FILE:
 132       break;
 133    case GRF:
 134       reg.reg_offset += delta / 32;
 135       break;
 136    case MRF:
 137       reg.reg += delta / 32;
 138       break;
 139    default:
 140       assert(delta == 0);
 141    }
 142    reg.subreg_offset += delta % 32;
 143    return reg;
 144 }
 145
 146 static inline fs_reg
 147 offset(fs_reg reg, unsigned delta)
 148 {
 149    assert(reg.stride > 0);
 150    switch (reg.file) {
 151    case BAD_FILE:
 152       break;
 153    case GRF:
 154    case MRF:
 155       return byte_offset(reg, delta * reg.width * reg.stride * type_sz(reg.type));
 156    case UNIFORM:
 157       reg.reg_offset += delta;
 158       break;
 159    default:
 160       assert(delta == 0);
 161    }
 162    return reg;
 163 }
 164
 165 /**
 166  * Get either of the 8-component halves of a 16-component register.
 167  *
 168  * Note: this also works if \c reg represents a SIMD16 pair of registers.
 169  */
 170 static inline fs_reg
 171 half(fs_reg reg, unsigned idx)
 172 {
 173    assert(idx < 2);
 174    assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
 175    assert(reg.width == 16);
 176    reg.width = 8;
 177    return byte_offset(reg, 8 * idx * reg.stride * type_sz(reg.type));
 178 }
 179
 180 static const fs_reg reg_undef;
 181
 182 class ip_record : public exec_node {
 183 public:
 184    DECLARE_RALLOC_CXX_OPERATORS(ip_record)
 185
 186    ip_record(int ip)
 187    {
 188       this->ip = ip;
 189    }
 190
 191    int ip;
 192 };
 193
 194 class fs_inst : public backend_instruction {
 195    fs_inst &operator=(const fs_inst &);
 196
 197    void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
 198              fs_reg *src, int sources);
 199
 200 public:
 201    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 202
 203    fs_inst();
 204    fs_inst(enum opcode opcode, uint8_t exec_size);
 205    fs_inst(enum opcode opcode, const fs_reg &dst);
 206    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 207            const fs_reg &src0);
 208    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 209    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 210            const fs_reg &src0, const fs_reg &src1);
 211    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 212            const fs_reg &src1);
 213    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 214            const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 215    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 216            const fs_reg &src1, const fs_reg &src2);
 217    fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources);
 218    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 219            fs_reg src[], int sources);
 220    fs_inst(const fs_inst &that);
 221
 222    void resize_sources(uint8_t num_sources);
 223
 224    bool equals(fs_inst *inst) const;
 225    bool overwrites_reg(const fs_reg &reg) const;
 226    bool is_send_from_grf() const;
 227    bool is_partial_write() const;
 228    int regs_read(fs_visitor *v, int arg) const;
 229    bool can_do_source_mods(struct brw_context *brw);
 230
 231    bool reads_flag() const;
 232    bool writes_flag() const;
 233
 234    fs_reg dst;
 235    fs_reg *src;
 236
 237    uint8_t sources; /**< Number of fs_reg sources. */
 238
 239    /**
 240     * Execution size of the instruction.  This is used by the generator to
 241     * generate the correct binary for the given fs_inst.  Current valid
 242     * values are 1, 8, 16.
 243     */
 244    uint8_t exec_size;
 245
 246    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 247     * mod and predication.
 248     */
 249    uint8_t flag_subreg;
 250
 251    uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
 252    bool eot:1;
 253    bool header_present:1;
 254    bool shadow_compare:1;
 255    bool force_uncompressed:1;
 256    bool force_sechalf:1;
 257    bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
 258 };
 259
 260 /**
 261  * The fragment shader front-end.
 262  *
 263  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
 264  */
 265 class fs_visitor : public backend_visitor
 266 {
 267 public:
 268    const fs_reg reg_null_f;
 269    const fs_reg reg_null_d;
 270    const fs_reg reg_null_ud;
 271
 272    fs_visitor(struct brw_context *brw,
 273               void *mem_ctx,
 274               const struct brw_wm_prog_key *key,
 275               struct brw_wm_prog_data *prog_data,
 276               struct gl_shader_program *shader_prog,
 277               struct gl_fragment_program *fp,
 278               unsigned dispatch_width);
 279    ~fs_visitor();
 280    void init();
 281
 282    fs_reg *variable_storage(ir_variable *var);
 283    int virtual_grf_alloc(int size);
 284    void import_uniforms(fs_visitor *v);
 285
 286    void visit(ir_variable *ir);
 287    void visit(ir_assignment *ir);
 288    void visit(ir_dereference_variable *ir);
 289    void visit(ir_dereference_record *ir);
 290    void visit(ir_dereference_array *ir);
 291    void visit(ir_expression *ir);
 292    void visit(ir_texture *ir);
 293    void visit(ir_if *ir);
 294    void visit(ir_constant *ir);
 295    void visit(ir_swizzle *ir);
 296    void visit(ir_return *ir);
 297    void visit(ir_loop *ir);
 298    void visit(ir_loop_jump *ir);
 299    void visit(ir_discard *ir);
 300    void visit(ir_call *ir);
 301    void visit(ir_function *ir);
 302    void visit(ir_function_signature *ir);
 303    void visit(ir_emit_vertex *);
 304    void visit(ir_end_primitive *);
 305
 306    uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
 307    void swizzle_result(ir_texture *ir, fs_reg orig_val, uint32_t sampler);
 308
 309    fs_inst *emit(fs_inst *inst);
 310    void emit(exec_list list);
 311
 312    fs_inst *emit(enum opcode opcode);
 313    fs_inst *emit(enum opcode opcode, const fs_reg &dst);
 314    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 315    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 316                  const fs_reg &src1);
 317    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 318                  const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 319    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 320                  fs_reg src[], int sources);
 321
 322    fs_inst *MOV(const fs_reg &dst, const fs_reg &src);
 323    fs_inst *NOT(const fs_reg &dst, const fs_reg &src);
 324    fs_inst *RNDD(const fs_reg &dst, const fs_reg &src);
 325    fs_inst *RNDE(const fs_reg &dst, const fs_reg &src);
 326    fs_inst *RNDZ(const fs_reg &dst, const fs_reg &src);
 327    fs_inst *FRC(const fs_reg &dst, const fs_reg &src);
 328    fs_inst *ADD(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 329    fs_inst *MUL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 330    fs_inst *MACH(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 331    fs_inst *MAC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 332    fs_inst *SHL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 333    fs_inst *SHR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 334    fs_inst *ASR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 335    fs_inst *AND(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 336    fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 337    fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 338    fs_inst *IF(enum brw_predicate predicate);
 339    fs_inst *IF(const fs_reg &src0, const fs_reg &src1,
 340                enum brw_conditional_mod condition);
 341    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 342                 enum brw_conditional_mod condition);
 343    fs_inst *LRP(const fs_reg &dst, const fs_reg &a, const fs_reg &y,
 344                 const fs_reg &x);
 345    fs_inst *DEP_RESOLVE_MOV(int grf);
 346    fs_inst *BFREV(const fs_reg &dst, const fs_reg &value);
 347    fs_inst *BFE(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset,
 348                 const fs_reg &value);
 349    fs_inst *BFI1(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset);
 350    fs_inst *BFI2(const fs_reg &dst, const fs_reg &bfi1_dst,
 351                  const fs_reg &insert, const fs_reg &base);
 352    fs_inst *FBH(const fs_reg &dst, const fs_reg &value);
 353    fs_inst *FBL(const fs_reg &dst, const fs_reg &value);
 354    fs_inst *CBIT(const fs_reg &dst, const fs_reg &value);
 355    fs_inst *MAD(const fs_reg &dst, const fs_reg &c, const fs_reg &b,
 356                 const fs_reg &a);
 357    fs_inst *ADDC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 358    fs_inst *SUBB(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 359    fs_inst *SEL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 360
 361    int type_size(const struct glsl_type *type);
 362    fs_inst *get_instruction_generating_reg(fs_inst *start,
 363                                            fs_inst *end,
 364                                            const fs_reg &reg);
 365
 366    fs_inst *LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources);
 367
 368    exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
 369                                         const fs_reg &surf_index,
 370                                         const fs_reg &varying_offset,
 371                                         uint32_t const_offset);
 372
 373    bool run();
 374    void assign_binding_table_offsets();
 375    void setup_payload_gen4();
 376    void setup_payload_gen6();
 377    void assign_curb_setup();
 378    void calculate_urb_setup();
 379    void assign_urb_setup();
 380    bool assign_regs(bool allow_spilling);
 381    void assign_regs_trivial();
 382    void get_used_mrfs(bool *mrf_used);
 383    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 384                                    int first_payload_node);
 385    void setup_mrf_hack_interference(struct ra_graph *g,
 386                                     int first_mrf_hack_node);
 387    int choose_spill_reg(struct ra_graph *g);
 388    void spill_reg(int spill_reg);
 389    void split_virtual_grfs();
 390    bool compact_virtual_grfs();
 391    void move_uniform_array_access_to_pull_constants();
 392    void assign_constant_locations();
 393    void demote_pull_constants();
 394    void invalidate_live_intervals();
 395    void calculate_live_intervals();
 396    void calculate_register_pressure();
 397    bool opt_algebraic();
 398    bool opt_cse();
 399    bool opt_cse_local(bblock_t *block);
 400    bool opt_copy_propagate();
 401    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 402    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 403    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 404                                  exec_list *acp);
 405    void opt_drop_redundant_mov_to_flags();
 406    bool opt_register_renaming();
 407    bool register_coalesce();
 408    bool compute_to_mrf();
 409    bool dead_code_eliminate();
 410    bool remove_duplicate_mrf_writes();
 411    bool virtual_grf_interferes(int a, int b);
 412    void schedule_instructions(instruction_scheduler_mode mode);
 413    void insert_gen4_send_dependency_workarounds();
 414    void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
 415                                                     fs_inst *inst);
 416    void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
 417                                                      fs_inst *inst);
 418    void vfail(const char *msg, va_list args);
 419    void fail(const char *msg, ...);
 420    void no16(const char *msg, ...);
 421    void lower_uniform_pull_constant_loads();
 422    bool lower_load_payload();
 423
 424    void push_force_uncompressed();
 425    void pop_force_uncompressed();
 426
 427    void emit_dummy_fs();
 428    void emit_repclear_shader();
 429    fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
 430    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 431                          glsl_interp_qualifier interpolation_mode,
 432                          bool is_centroid, bool is_sample);
 433    fs_reg *emit_frontfacing_interpolation();
 434    fs_reg *emit_samplepos_setup();
 435    fs_reg *emit_sampleid_setup(ir_variable *ir);
 436    fs_reg *emit_general_interpolation(ir_variable *ir);
 437    void emit_interpolation_setup_gen4();
 438    void emit_interpolation_setup_gen6();
 439    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
 440    fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
 441                            bool is_rect, uint32_t sampler, int texunit);
 442    fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 443                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 444                               uint32_t sampler);
 445    fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 446                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 447                               fs_reg sample_index, uint32_t sampler);
 448    fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 449                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 450                               fs_reg sample_index, fs_reg mcs, fs_reg sampler);
 451    fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, fs_reg sampler);
 452    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
 453    fs_reg fix_math_operand(fs_reg src);
 454    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 455    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 456    void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
 457                  const fs_reg &a);
 458    void emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
 459                     const fs_reg &src0, const fs_reg &src1);
 460    bool try_emit_saturate(ir_expression *ir);
 461    bool try_emit_mad(ir_expression *ir);
 462    void try_replace_with_sel();
 463    bool opt_peephole_sel();
 464    bool opt_peephole_predicated_break();
 465    bool opt_saturate_propagation();
 466    void emit_bool_to_cond_code(ir_rvalue *condition);
 467    void emit_if_gen6(ir_if *ir);
 468    void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
 469                      uint32_t spill_offset, int count);
 470    void emit_spill(bblock_t *block, fs_inst *inst, fs_reg reg,
 471                    uint32_t spill_offset, int count);
 472
 473    void emit_fragment_program_code();
 474    void setup_fp_regs();
 475    fs_reg get_fp_src_reg(const prog_src_register *src);
 476    fs_reg get_fp_dst_reg(const prog_dst_register *dst);
 477    void emit_fp_alu1(enum opcode opcode,
 478                      const struct prog_instruction *fpi,
 479                      fs_reg dst, fs_reg src);
 480    void emit_fp_alu2(enum opcode opcode,
 481                      const struct prog_instruction *fpi,
 482                      fs_reg dst, fs_reg src0, fs_reg src1);
 483    void emit_fp_scalar_write(const struct prog_instruction *fpi,
 484                              fs_reg dst, fs_reg src);
 485    void emit_fp_scalar_math(enum opcode opcode,
 486                             const struct prog_instruction *fpi,
 487                             fs_reg dst, fs_reg src);
 488
 489    void emit_fp_minmax(const struct prog_instruction *fpi,
 490                        fs_reg dst, fs_reg src0, fs_reg src1);
 491
 492    void emit_fp_sop(enum brw_conditional_mod conditional_mod,
 493                     const struct prog_instruction *fpi,
 494                     fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
 495
 496    void emit_color_write(fs_reg color, int index, int first_color_mrf);
 497    void emit_alpha_test();
 498    fs_inst *emit_single_fb_write(fs_reg color1, fs_reg color2,
 499                                  fs_reg src0_alpha, unsigned components);
 500    void emit_fb_writes();
 501
 502    void emit_shader_time_begin();
 503    void emit_shader_time_end();
 504    void emit_shader_time_write(enum shader_time_shader_type type,
 505                                fs_reg value);
 506
 507    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 508                             fs_reg dst, fs_reg offset, fs_reg src0,
 509                             fs_reg src1);
 510
 511    void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
 512                                   fs_reg offset);
 513
 514    void emit_interpolate_expression(ir_expression *ir);
 515
 516    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 517                                fs_reg dst,
 518                                fs_reg src,
 519                                fs_inst *pre_rhs_inst,
 520                                fs_inst *last_rhs_inst);
 521    void emit_assignment_writes(fs_reg &l, fs_reg &r,
 522                                const glsl_type *type, bool predicated);
 523    void resolve_ud_negate(fs_reg *reg);
 524    void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
 525
 526    fs_reg get_timestamp();
 527
 528    struct brw_reg interp_reg(int location, int channel);
 529    void setup_uniform_values(ir_variable *ir);
 530    void setup_builtin_uniform_values(ir_variable *ir);
 531    int implied_mrf_writes(fs_inst *inst);
 532
 533    virtual void dump_instructions();
 534    virtual void dump_instructions(const char *name);
 535    void dump_instruction(backend_instruction *inst);
 536    void dump_instruction(backend_instruction *inst, FILE *file);
 537
 538    void visit_atomic_counter_intrinsic(ir_call *ir);
 539
 540    const void *const key;
 541    struct brw_stage_prog_data *prog_data;
 542    unsigned int sanity_param_count;
 543
 544    int *param_size;
 545
 546    int *virtual_grf_sizes;
 547    int virtual_grf_count;
 548    int virtual_grf_array_size;
 549    int *virtual_grf_start;
 550    int *virtual_grf_end;
 551    brw::fs_live_variables *live_intervals;
 552
 553    int *regs_live_at_ip;
 554
 555    /** Number of uniform variable components visited. */
 556    unsigned uniforms;
 557
 558    /** Byte-offset for the next available spot in the scratch space buffer. */
 559    unsigned last_scratch;
 560
 561    /**
 562     * Array mapping UNIFORM register numbers to the pull parameter index,
 563     * or -1 if this uniform register isn't being uploaded as a pull constant.
 564     */
 565    int *pull_constant_loc;
 566
 567    /**
 568     * Array mapping UNIFORM register numbers to the push parameter index,
 569     * or -1 if this uniform register isn't being uploaded as a push constant.
 570     */
 571    int *push_constant_loc;
 572
 573    struct hash_table *variable_ht;
 574    fs_reg frag_depth;
 575    fs_reg sample_mask;
 576    fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
 577    unsigned output_components[BRW_MAX_DRAW_BUFFERS];
 578    fs_reg dual_src_output;
 579    bool do_dual_src;
 580    int first_non_payload_grf;
 581    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 582    int max_grf;
 583
 584    fs_reg *fp_temp_regs;
 585    fs_reg *fp_input_regs;
 586
 587    /** @{ debug annotation info */
 588    const char *current_annotation;
 589    const void *base_ir;
 590    /** @} */
 591
 592    bool failed;
 593    char *fail_msg;
 594    bool simd16_unsupported;
 595    char *no16_msg;
 596
 597    /* Result of last visit() method. */
 598    fs_reg result;
 599
 600    /** Register numbers for thread payload fields. */
 601    struct {
 602       uint8_t source_depth_reg;
 603       uint8_t source_w_reg;
 604       uint8_t aa_dest_stencil_reg;
 605       uint8_t dest_depth_reg;
 606       uint8_t sample_pos_reg;
 607       uint8_t sample_mask_in_reg;
 608       uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 609
 610       /** The number of thread payload registers the hardware will supply. */
 611       uint8_t num_regs;
 612    } payload;
 613
 614    bool source_depth_to_render_target;
 615    bool runtime_check_aads_emit;
 616
 617    fs_reg pixel_x;
 618    fs_reg pixel_y;
 619    fs_reg wpos_w;
 620    fs_reg pixel_w;
 621    fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 622    fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 623    fs_reg shader_start_time;
 624
 625    int grf_used;
 626    bool spilled_any_registers;
 627
 628    const unsigned dispatch_width; /**< 8 or 16 */
 629
 630    int force_uncompressed_stack;
 631 };
 632
 633 /**
 634  * The fragment shader code generator.
 635  *
 636  * Translates FS IR to actual i965 assembly code.
 637  */
 638 class fs_generator
 639 {
 640 public:
 641    fs_generator(struct brw_context *brw,
 642                 void *mem_ctx,
 643                 const struct brw_wm_prog_key *key,
 644                 struct brw_wm_prog_data *prog_data,
 645                 struct gl_shader_program *shader_prog,
 646                 struct gl_fragment_program *fp,
 647                 bool runtime_check_aads_emit,
 648                 bool debug_flag);
 649    ~fs_generator();
 650
 651    const unsigned *generate_assembly(const cfg_t *simd8_cfg,
 652                                      const cfg_t *simd16_cfg,
 653                                      unsigned *assembly_size);
 654
 655 private:
 656    void generate_code(const cfg_t *cfg);
 657    void fire_fb_write(fs_inst *inst,
 658                       GLuint base_reg,
 659                       struct brw_reg implied_header,
 660                       GLuint nr);
 661    void generate_fb_write(fs_inst *inst);
 662    void generate_blorp_fb_write(fs_inst *inst);
 663    void generate_rep_fb_write(fs_inst *inst);
 664    void generate_pixel_xy(struct brw_reg dst, bool is_x);
 665    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 666                          struct brw_reg *src);
 667    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 668                      struct brw_reg sampler_index);
 669    void generate_math_gen6(fs_inst *inst,
 670                            struct brw_reg dst,
 671                            struct brw_reg src0,
 672                            struct brw_reg src1);
 673    void generate_math_gen4(fs_inst *inst,
 674                            struct brw_reg dst,
 675                            struct brw_reg src);
 676    void generate_math_g45(fs_inst *inst,
 677                           struct brw_reg dst,
 678                           struct brw_reg src);
 679    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg quality);
 680    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 681                      struct brw_reg quality, bool negate_value);
 682    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 683    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 684    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 685    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 686                                             struct brw_reg index,
 687                                             struct brw_reg offset);
 688    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 689                                                  struct brw_reg dst,
 690                                                  struct brw_reg surf_index,
 691                                                  struct brw_reg offset);
 692    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 693                                             struct brw_reg index,
 694                                             struct brw_reg offset);
 695    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 696                                                  struct brw_reg dst,
 697                                                  struct brw_reg index,
 698                                                  struct brw_reg offset);
 699    void generate_mov_dispatch_to_flags(fs_inst *inst);
 700
 701    void generate_pixel_interpolator_query(fs_inst *inst,
 702                                           struct brw_reg dst,
 703                                           struct brw_reg src,
 704                                           struct brw_reg msg_data,
 705                                           unsigned msg_type);
 706
 707    void generate_set_omask(fs_inst *inst,
 708                            struct brw_reg dst,
 709                            struct brw_reg sample_mask);
 710
 711    void generate_set_sample_id(fs_inst *inst,
 712                                struct brw_reg dst,
 713                                struct brw_reg src0,
 714                                struct brw_reg src1);
 715
 716    void generate_set_simd4x2_offset(fs_inst *inst,
 717                                     struct brw_reg dst,
 718                                     struct brw_reg offset);
 719    void generate_discard_jump(fs_inst *inst);
 720
 721    void generate_pack_half_2x16_split(fs_inst *inst,
 722                                       struct brw_reg dst,
 723                                       struct brw_reg x,
 724                                       struct brw_reg y);
 725    void generate_unpack_half_2x16_split(fs_inst *inst,
 726                                         struct brw_reg dst,
 727                                         struct brw_reg src);
 728
 729    void generate_shader_time_add(fs_inst *inst,
 730                                  struct brw_reg payload,
 731                                  struct brw_reg offset,
 732                                  struct brw_reg value);
 733
 734    void generate_untyped_atomic(fs_inst *inst,
 735                                 struct brw_reg dst,
 736                                 struct brw_reg atomic_op,
 737                                 struct brw_reg surf_index);
 738
 739    void generate_untyped_surface_read(fs_inst *inst,
 740                                       struct brw_reg dst,
 741                                       struct brw_reg surf_index);
 742
 743    bool patch_discard_jumps_to_fb_writes();
 744
 745    struct brw_context *brw;
 746    struct gl_context *ctx;
 747
 748    struct brw_compile *p;
 749    gl_shader_stage stage;
 750    const void * const key;
 751    struct brw_stage_prog_data * const prog_data;
 752
 753    struct gl_shader_program * const shader_prog;
 754    const struct gl_program *prog;
 755
 756    unsigned dispatch_width; /**< 8 or 16 */
 757
 758    exec_list discard_halt_patches;
 759    bool runtime_check_aads_emit;
 760    const bool debug_flag;
 761    void *mem_ctx;
 762 };
 763
 764 bool brw_do_channel_expressions(struct exec_list *instructions);
 765 bool brw_do_vector_splitting(struct exec_list *instructions);
 766 bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);
 767
 768 struct brw_reg brw_reg_from_fs_reg(fs_reg *reg);