src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31
  32 extern "C" {
  33
  34 #include <sys/types.h>
  35
  36 #include "main/macros.h"
  37 #include "main/shaderobj.h"
  38 #include "main/uniforms.h"
  39 #include "program/prog_parameter.h"
  40 #include "program/prog_print.h"
  41 #include "program/prog_optimize.h"
  42 #include "util/register_allocate.h"
  43 #include "program/sampler.h"
  44 #include "program/hash_table.h"
  45 #include "brw_context.h"
  46 #include "brw_eu.h"
  47 #include "brw_wm.h"
  48 #include "brw_shader.h"
  49 #include "intel_asm_annotation.h"
  50 }
  51 #include "glsl/glsl_types.h"
  52 #include "glsl/ir.h"
  53
  54 #define MAX_SAMPLER_MESSAGE_SIZE 11
  55 #define MAX_VGRF_SIZE 16
  56
  57 struct bblock_t;
  58 namespace {
  59    struct acp_entry;
  60 }
  61
  62 namespace brw {
  63    class fs_live_variables;
  64 }
  65
  66 class fs_inst;
  67 class fs_visitor;
  68
  69 class fs_reg : public backend_reg {
  70 public:
  71    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  72
  73    void init();
  74
  75    fs_reg();
  76    explicit fs_reg(float f);
  77    explicit fs_reg(int32_t i);
  78    explicit fs_reg(uint32_t u);
  79    fs_reg(struct brw_reg fixed_hw_reg);
  80    fs_reg(enum register_file file, int reg);
  81    fs_reg(enum register_file file, int reg, enum brw_reg_type type);
  82    fs_reg(enum register_file file, int reg, enum brw_reg_type type, uint8_t width);
  83    fs_reg(fs_visitor *v, const struct glsl_type *type);
  84
  85    bool equals(const fs_reg &r) const;
  86    bool is_contiguous() const;
  87
  88    /** Smear a channel of the reg to all channels. */
  89    fs_reg &set_smear(unsigned subreg);
  90
  91    /**
  92     * Offset in bytes from the start of the register.  Values up to a
  93     * backend_reg::reg_offset unit are valid.
  94     */
  95    int subreg_offset;
  96
  97    fs_reg *reladdr;
  98
  99    /**
 100     * The register width.  This indicates how many hardware values are
 101     * represented by each virtual value.  Valid values are 1, 8, or 16.
 102     * For immediate values, this is 1.  Most of the rest of the time, it
 103     * will be equal to the dispatch width.
 104     */
 105    uint8_t width;
 106
 107    /**
 108     * Returns the effective register width when used as a source in the
 109     * given instruction.  Registers such as uniforms and immediates
 110     * effectively take on the width of the instruction in which they are
 111     * used.
 112     */
 113    uint8_t effective_width;
 114
 115    /** Register region horizontal stride */
 116    uint8_t stride;
 117 };
 118
 119 static inline fs_reg
 120 retype(fs_reg reg, enum brw_reg_type type)
 121 {
 122    reg.fixed_hw_reg.type = reg.type = type;
 123    return reg;
 124 }
 125
 126 static inline fs_reg
 127 byte_offset(fs_reg reg, unsigned delta)
 128 {
 129    switch (reg.file) {
 130    case BAD_FILE:
 131       break;
 132    case GRF:
 133       reg.reg_offset += delta / 32;
 134       break;
 135    case MRF:
 136       reg.reg += delta / 32;
 137       break;
 138    default:
 139       assert(delta == 0);
 140    }
 141    reg.subreg_offset += delta % 32;
 142    return reg;
 143 }
 144
 145 static inline fs_reg
 146 horiz_offset(fs_reg reg, unsigned delta)
 147 {
 148    switch (reg.file) {
 149    case BAD_FILE:
 150    case UNIFORM:
 151    case IMM:
 152       /* These only have a single component that is implicitly splatted.  A
 153        * horizontal offset should be a harmless no-op.
 154        */
 155       break;
 156    case GRF:
 157    case MRF:
 158       return byte_offset(reg, delta * reg.stride * type_sz(reg.type));
 159    default:
 160       assert(delta == 0);
 161    }
 162    return reg;
 163 }
 164
 165 static inline fs_reg
 166 offset(fs_reg reg, unsigned delta)
 167 {
 168    assert(reg.stride > 0);
 169    switch (reg.file) {
 170    case BAD_FILE:
 171       break;
 172    case GRF:
 173    case MRF:
 174       return byte_offset(reg, delta * reg.width * reg.stride * type_sz(reg.type));
 175    case UNIFORM:
 176       reg.reg_offset += delta;
 177       break;
 178    default:
 179       assert(delta == 0);
 180    }
 181    return reg;
 182 }
 183
 184 static inline fs_reg
 185 component(fs_reg reg, unsigned idx)
 186 {
 187    assert(reg.subreg_offset == 0);
 188    assert(idx < reg.width);
 189    reg.subreg_offset = idx * type_sz(reg.type);
 190    reg.width = 1;
 191    return reg;
 192 }
 193
 194 /**
 195  * Get either of the 8-component halves of a 16-component register.
 196  *
 197  * Note: this also works if \c reg represents a SIMD16 pair of registers.
 198  */
 199 static inline fs_reg
 200 half(fs_reg reg, unsigned idx)
 201 {
 202    assert(idx < 2);
 203    assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
 204    assert(reg.width == 16);
 205    reg.width = 8;
 206    return horiz_offset(reg, 8 * idx);
 207 }
 208
 209 static const fs_reg reg_undef;
 210
 211 class fs_inst : public backend_instruction {
 212    fs_inst &operator=(const fs_inst &);
 213
 214    void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
 215              fs_reg *src, int sources);
 216
 217 public:
 218    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 219
 220    fs_inst();
 221    fs_inst(enum opcode opcode, uint8_t exec_size);
 222    fs_inst(enum opcode opcode, const fs_reg &dst);
 223    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 224            const fs_reg &src0);
 225    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 226    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 227            const fs_reg &src0, const fs_reg &src1);
 228    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 229            const fs_reg &src1);
 230    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 231            const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 232    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 233            const fs_reg &src1, const fs_reg &src2);
 234    fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources);
 235    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 236            fs_reg src[], int sources);
 237    fs_inst(const fs_inst &that);
 238
 239    void resize_sources(uint8_t num_sources);
 240
 241    bool equals(fs_inst *inst) const;
 242    bool overwrites_reg(const fs_reg &reg) const;
 243    bool is_send_from_grf() const;
 244    bool is_partial_write() const;
 245    int regs_read(fs_visitor *v, int arg) const;
 246    bool can_do_source_mods(struct brw_context *brw);
 247
 248    bool reads_flag() const;
 249    bool writes_flag() const;
 250
 251    fs_reg dst;
 252    fs_reg *src;
 253
 254    uint8_t sources; /**< Number of fs_reg sources. */
 255
 256    /**
 257     * Execution size of the instruction.  This is used by the generator to
 258     * generate the correct binary for the given fs_inst.  Current valid
 259     * values are 1, 8, 16.
 260     */
 261    uint8_t exec_size;
 262
 263    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 264     * mod and predication.
 265     */
 266    uint8_t flag_subreg;
 267
 268    uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
 269    bool eot:1;
 270    bool force_uncompressed:1;
 271    bool force_sechalf:1;
 272    bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
 273 };
 274
 275 /**
 276  * The fragment shader front-end.
 277  *
 278  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
 279  */
 280 class fs_visitor : public backend_visitor
 281 {
 282 public:
 283    const fs_reg reg_null_f;
 284    const fs_reg reg_null_d;
 285    const fs_reg reg_null_ud;
 286
 287    fs_visitor(struct brw_context *brw,
 288               void *mem_ctx,
 289               const struct brw_wm_prog_key *key,
 290               struct brw_wm_prog_data *prog_data,
 291               struct gl_shader_program *shader_prog,
 292               struct gl_fragment_program *fp,
 293               unsigned dispatch_width);
 294    ~fs_visitor();
 295    void init();
 296
 297    fs_reg *variable_storage(ir_variable *var);
 298    int virtual_grf_alloc(int size);
 299    void import_uniforms(fs_visitor *v);
 300
 301    void visit(ir_variable *ir);
 302    void visit(ir_assignment *ir);
 303    void visit(ir_dereference_variable *ir);
 304    void visit(ir_dereference_record *ir);
 305    void visit(ir_dereference_array *ir);
 306    void visit(ir_expression *ir);
 307    void visit(ir_texture *ir);
 308    void visit(ir_if *ir);
 309    void visit(ir_constant *ir);
 310    void visit(ir_swizzle *ir);
 311    void visit(ir_return *ir);
 312    void visit(ir_loop *ir);
 313    void visit(ir_loop_jump *ir);
 314    void visit(ir_discard *ir);
 315    void visit(ir_call *ir);
 316    void visit(ir_function *ir);
 317    void visit(ir_function_signature *ir);
 318    void visit(ir_emit_vertex *);
 319    void visit(ir_end_primitive *);
 320
 321    uint32_t gather_channel(int orig_chan, uint32_t sampler);
 322    void swizzle_result(ir_texture_opcode op, int dest_components,
 323                        fs_reg orig_val, uint32_t sampler);
 324
 325    fs_inst *emit(fs_inst *inst);
 326    void emit(exec_list list);
 327
 328    fs_inst *emit(enum opcode opcode);
 329    fs_inst *emit(enum opcode opcode, const fs_reg &dst);
 330    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 331    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 332                  const fs_reg &src1);
 333    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 334                  const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 335    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 336                  fs_reg src[], int sources);
 337
 338    fs_inst *MOV(const fs_reg &dst, const fs_reg &src);
 339    fs_inst *NOT(const fs_reg &dst, const fs_reg &src);
 340    fs_inst *RNDD(const fs_reg &dst, const fs_reg &src);
 341    fs_inst *RNDE(const fs_reg &dst, const fs_reg &src);
 342    fs_inst *RNDZ(const fs_reg &dst, const fs_reg &src);
 343    fs_inst *FRC(const fs_reg &dst, const fs_reg &src);
 344    fs_inst *ADD(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 345    fs_inst *MUL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 346    fs_inst *MACH(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 347    fs_inst *MAC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 348    fs_inst *SHL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 349    fs_inst *SHR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 350    fs_inst *ASR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 351    fs_inst *AND(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 352    fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 353    fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 354    fs_inst *IF(enum brw_predicate predicate);
 355    fs_inst *IF(const fs_reg &src0, const fs_reg &src1,
 356                enum brw_conditional_mod condition);
 357    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 358                 enum brw_conditional_mod condition);
 359    fs_inst *LRP(const fs_reg &dst, const fs_reg &a, const fs_reg &y,
 360                 const fs_reg &x);
 361    fs_inst *DEP_RESOLVE_MOV(int grf);
 362    fs_inst *BFREV(const fs_reg &dst, const fs_reg &value);
 363    fs_inst *BFE(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset,
 364                 const fs_reg &value);
 365    fs_inst *BFI1(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset);
 366    fs_inst *BFI2(const fs_reg &dst, const fs_reg &bfi1_dst,
 367                  const fs_reg &insert, const fs_reg &base);
 368    fs_inst *FBH(const fs_reg &dst, const fs_reg &value);
 369    fs_inst *FBL(const fs_reg &dst, const fs_reg &value);
 370    fs_inst *CBIT(const fs_reg &dst, const fs_reg &value);
 371    fs_inst *MAD(const fs_reg &dst, const fs_reg &c, const fs_reg &b,
 372                 const fs_reg &a);
 373    fs_inst *ADDC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 374    fs_inst *SUBB(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 375    fs_inst *SEL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 376
 377    int type_size(const struct glsl_type *type);
 378    fs_inst *get_instruction_generating_reg(fs_inst *start,
 379                                            fs_inst *end,
 380                                            const fs_reg &reg);
 381
 382    fs_inst *LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources);
 383
 384    exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
 385                                         const fs_reg &surf_index,
 386                                         const fs_reg &varying_offset,
 387                                         uint32_t const_offset);
 388
 389    bool run();
 390    void optimize();
 391    void allocate_registers();
 392    void assign_binding_table_offsets();
 393    void setup_payload_gen4();
 394    void setup_payload_gen6();
 395    void assign_curb_setup();
 396    void calculate_urb_setup();
 397    void assign_urb_setup();
 398    bool assign_regs(bool allow_spilling);
 399    void assign_regs_trivial();
 400    void get_used_mrfs(bool *mrf_used);
 401    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 402                                    int first_payload_node);
 403    void setup_mrf_hack_interference(struct ra_graph *g,
 404                                     int first_mrf_hack_node);
 405    int choose_spill_reg(struct ra_graph *g);
 406    void spill_reg(int spill_reg);
 407    void split_virtual_grfs();
 408    bool compact_virtual_grfs();
 409    void move_uniform_array_access_to_pull_constants();
 410    void assign_constant_locations();
 411    void demote_pull_constants();
 412    void invalidate_live_intervals();
 413    void calculate_live_intervals();
 414    void calculate_register_pressure();
 415    bool opt_algebraic();
 416    bool opt_cse();
 417    bool opt_cse_local(bblock_t *block);
 418    bool opt_copy_propagate();
 419    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 420    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 421    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 422                                  exec_list *acp);
 423    void opt_drop_redundant_mov_to_flags();
 424    bool opt_register_renaming();
 425    bool register_coalesce();
 426    bool compute_to_mrf();
 427    bool dead_code_eliminate();
 428    bool remove_duplicate_mrf_writes();
 429    bool virtual_grf_interferes(int a, int b);
 430    void schedule_instructions(instruction_scheduler_mode mode);
 431    void insert_gen4_send_dependency_workarounds();
 432    void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
 433                                                     fs_inst *inst);
 434    void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
 435                                                      fs_inst *inst);
 436    void vfail(const char *msg, va_list args);
 437    void fail(const char *msg, ...);
 438    void no16(const char *msg, ...);
 439    void lower_uniform_pull_constant_loads();
 440    bool lower_load_payload();
 441
 442    void emit_dummy_fs();
 443    void emit_repclear_shader();
 444    fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
 445    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 446                          glsl_interp_qualifier interpolation_mode,
 447                          bool is_centroid, bool is_sample);
 448    fs_reg *emit_frontfacing_interpolation();
 449    fs_reg *emit_samplepos_setup();
 450    fs_reg *emit_sampleid_setup();
 451    fs_reg *emit_general_interpolation(ir_variable *ir);
 452    void emit_interpolation_setup_gen4();
 453    void emit_interpolation_setup_gen6();
 454    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
 455    fs_reg rescale_texcoord(fs_reg coordinate, const glsl_type *coord_type,
 456                            bool is_rect, uint32_t sampler, int texunit);
 457    fs_inst *emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
 458                               fs_reg coordinate, int coord_components,
 459                               fs_reg shadow_comp,
 460                               fs_reg lod, fs_reg lod2, int grad_components,
 461                               uint32_t sampler);
 462    fs_inst *emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
 463                               fs_reg coordinate, int coord_components,
 464                               fs_reg shadow_comp,
 465                               fs_reg lod, fs_reg lod2, int grad_components,
 466                               fs_reg sample_index, uint32_t sampler,
 467                               bool has_offset);
 468    fs_inst *emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
 469                               fs_reg coordinate, int coord_components,
 470                               fs_reg shadow_comp,
 471                               fs_reg lod, fs_reg lod2, int grad_components,
 472                               fs_reg sample_index, fs_reg mcs, fs_reg sampler,
 473                               fs_reg offset_value);
 474    void emit_texture(ir_texture_opcode op,
 475                      const glsl_type *dest_type,
 476                      fs_reg coordinate, const struct glsl_type *coord_type,
 477                      fs_reg shadow_c,
 478                      fs_reg lod, fs_reg dpdy, int grad_components,
 479                      fs_reg sample_index,
 480                      fs_reg offset, unsigned offset_components,
 481                      fs_reg mcs,
 482                      int gather_component,
 483                      bool is_cube_array,
 484                      bool is_rect,
 485                      uint32_t sampler,
 486                      fs_reg sampler_reg,
 487                      int texunit);
 488    fs_reg emit_mcs_fetch(fs_reg coordinate, int components, fs_reg sampler);
 489    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
 490    fs_reg fix_math_operand(fs_reg src);
 491    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 492    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 493    void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
 494                  const fs_reg &a);
 495    void emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
 496                     const fs_reg &src0, const fs_reg &src1);
 497    bool try_emit_saturate(ir_expression *ir);
 498    bool try_emit_mad(ir_expression *ir);
 499    void try_replace_with_sel();
 500    bool opt_peephole_sel();
 501    bool opt_peephole_predicated_break();
 502    bool opt_saturate_propagation();
 503    void emit_bool_to_cond_code(ir_rvalue *condition);
 504    void emit_if_gen6(ir_if *ir);
 505    void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
 506                      uint32_t spill_offset, int count);
 507    void emit_spill(bblock_t *block, fs_inst *inst, fs_reg reg,
 508                    uint32_t spill_offset, int count);
 509
 510    void emit_fragment_program_code();
 511    void setup_fp_regs();
 512    fs_reg get_fp_src_reg(const prog_src_register *src);
 513    fs_reg get_fp_dst_reg(const prog_dst_register *dst);
 514    void emit_fp_alu1(enum opcode opcode,
 515                      const struct prog_instruction *fpi,
 516                      fs_reg dst, fs_reg src);
 517    void emit_fp_alu2(enum opcode opcode,
 518                      const struct prog_instruction *fpi,
 519                      fs_reg dst, fs_reg src0, fs_reg src1);
 520    void emit_fp_scalar_write(const struct prog_instruction *fpi,
 521                              fs_reg dst, fs_reg src);
 522    void emit_fp_scalar_math(enum opcode opcode,
 523                             const struct prog_instruction *fpi,
 524                             fs_reg dst, fs_reg src);
 525
 526    void emit_fp_minmax(const struct prog_instruction *fpi,
 527                        fs_reg dst, fs_reg src0, fs_reg src1);
 528
 529    void emit_fp_sop(enum brw_conditional_mod conditional_mod,
 530                     const struct prog_instruction *fpi,
 531                     fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
 532
 533    int setup_color_payload(fs_reg *dst, fs_reg color, unsigned components);
 534    void emit_alpha_test();
 535    fs_inst *emit_single_fb_write(fs_reg color1, fs_reg color2,
 536                                  fs_reg src0_alpha, unsigned components);
 537    void emit_fb_writes();
 538
 539    void emit_shader_time_begin();
 540    void emit_shader_time_end();
 541    void emit_shader_time_write(enum shader_time_shader_type type,
 542                                fs_reg value);
 543
 544    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 545                             fs_reg dst, fs_reg offset, fs_reg src0,
 546                             fs_reg src1);
 547
 548    void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
 549                                   fs_reg offset);
 550
 551    void emit_interpolate_expression(ir_expression *ir);
 552
 553    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 554                                fs_reg dst,
 555                                fs_reg src,
 556                                fs_inst *pre_rhs_inst,
 557                                fs_inst *last_rhs_inst);
 558    void emit_assignment_writes(fs_reg &l, fs_reg &r,
 559                                const glsl_type *type, bool predicated);
 560    void resolve_ud_negate(fs_reg *reg);
 561    void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
 562
 563    fs_reg get_timestamp();
 564
 565    struct brw_reg interp_reg(int location, int channel);
 566    void setup_uniform_values(ir_variable *ir);
 567    void setup_builtin_uniform_values(ir_variable *ir);
 568    int implied_mrf_writes(fs_inst *inst);
 569
 570    virtual void dump_instructions();
 571    virtual void dump_instructions(const char *name);
 572    void dump_instruction(backend_instruction *inst);
 573    void dump_instruction(backend_instruction *inst, FILE *file);
 574
 575    void visit_atomic_counter_intrinsic(ir_call *ir);
 576
 577    const void *const key;
 578    struct brw_stage_prog_data *prog_data;
 579    unsigned int sanity_param_count;
 580
 581    int *param_size;
 582
 583    int *virtual_grf_sizes;
 584    int virtual_grf_count;
 585    int virtual_grf_array_size;
 586    int *virtual_grf_start;
 587    int *virtual_grf_end;
 588    brw::fs_live_variables *live_intervals;
 589
 590    int *regs_live_at_ip;
 591
 592    /** Number of uniform variable components visited. */
 593    unsigned uniforms;
 594
 595    /** Byte-offset for the next available spot in the scratch space buffer. */
 596    unsigned last_scratch;
 597
 598    /**
 599     * Array mapping UNIFORM register numbers to the pull parameter index,
 600     * or -1 if this uniform register isn't being uploaded as a pull constant.
 601     */
 602    int *pull_constant_loc;
 603
 604    /**
 605     * Array mapping UNIFORM register numbers to the push parameter index,
 606     * or -1 if this uniform register isn't being uploaded as a push constant.
 607     */
 608    int *push_constant_loc;
 609
 610    struct hash_table *variable_ht;
 611    fs_reg frag_depth;
 612    fs_reg sample_mask;
 613    fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
 614    unsigned output_components[BRW_MAX_DRAW_BUFFERS];
 615    fs_reg dual_src_output;
 616    bool do_dual_src;
 617    int first_non_payload_grf;
 618    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 619    int max_grf;
 620
 621    fs_reg *fp_temp_regs;
 622    fs_reg *fp_input_regs;
 623
 624    /** @{ debug annotation info */
 625    const char *current_annotation;
 626    const void *base_ir;
 627    /** @} */
 628
 629    bool failed;
 630    char *fail_msg;
 631    bool simd16_unsupported;
 632    char *no16_msg;
 633
 634    /* Result of last visit() method. */
 635    fs_reg result;
 636
 637    /** Register numbers for thread payload fields. */
 638    struct {
 639       uint8_t source_depth_reg;
 640       uint8_t source_w_reg;
 641       uint8_t aa_dest_stencil_reg;
 642       uint8_t dest_depth_reg;
 643       uint8_t sample_pos_reg;
 644       uint8_t sample_mask_in_reg;
 645       uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 646
 647       /** The number of thread payload registers the hardware will supply. */
 648       uint8_t num_regs;
 649    } payload;
 650
 651    bool source_depth_to_render_target;
 652    bool runtime_check_aads_emit;
 653
 654    fs_reg pixel_x;
 655    fs_reg pixel_y;
 656    fs_reg wpos_w;
 657    fs_reg pixel_w;
 658    fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 659    fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 660    fs_reg shader_start_time;
 661
 662    int grf_used;
 663    bool spilled_any_registers;
 664
 665    const unsigned dispatch_width; /**< 8 or 16 */
 666 };
 667
 668 /**
 669  * The fragment shader code generator.
 670  *
 671  * Translates FS IR to actual i965 assembly code.
 672  */
 673 class fs_generator
 674 {
 675 public:
 676    fs_generator(struct brw_context *brw,
 677                 void *mem_ctx,
 678                 const struct brw_wm_prog_key *key,
 679                 struct brw_wm_prog_data *prog_data,
 680                 struct gl_shader_program *shader_prog,
 681                 struct gl_fragment_program *fp,
 682                 bool runtime_check_aads_emit,
 683                 bool debug_flag);
 684    ~fs_generator();
 685
 686    int generate_code(const cfg_t *cfg, int dispatch_width);
 687    const unsigned *get_assembly(unsigned int *assembly_size);
 688
 689 private:
 690    void fire_fb_write(fs_inst *inst,
 691                       struct brw_reg payload,
 692                       struct brw_reg implied_header,
 693                       GLuint nr);
 694    void generate_fb_write(fs_inst *inst, struct brw_reg payload);
 695    void generate_blorp_fb_write(fs_inst *inst);
 696    void generate_pixel_xy(struct brw_reg dst, bool is_x);
 697    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 698                          struct brw_reg *src);
 699    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 700                      struct brw_reg sampler_index);
 701    void generate_math_gen6(fs_inst *inst,
 702                            struct brw_reg dst,
 703                            struct brw_reg src0,
 704                            struct brw_reg src1);
 705    void generate_math_gen4(fs_inst *inst,
 706                            struct brw_reg dst,
 707                            struct brw_reg src);
 708    void generate_math_g45(fs_inst *inst,
 709                           struct brw_reg dst,
 710                           struct brw_reg src);
 711    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg quality);
 712    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 713                      struct brw_reg quality, bool negate_value);
 714    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 715    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 716    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 717    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 718                                             struct brw_reg index,
 719                                             struct brw_reg offset);
 720    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 721                                                  struct brw_reg dst,
 722                                                  struct brw_reg surf_index,
 723                                                  struct brw_reg offset);
 724    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 725                                             struct brw_reg index,
 726                                             struct brw_reg offset);
 727    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 728                                                  struct brw_reg dst,
 729                                                  struct brw_reg index,
 730                                                  struct brw_reg offset);
 731    void generate_mov_dispatch_to_flags(fs_inst *inst);
 732
 733    void generate_pixel_interpolator_query(fs_inst *inst,
 734                                           struct brw_reg dst,
 735                                           struct brw_reg src,
 736                                           struct brw_reg msg_data,
 737                                           unsigned msg_type);
 738
 739    void generate_set_omask(fs_inst *inst,
 740                            struct brw_reg dst,
 741                            struct brw_reg sample_mask);
 742
 743    void generate_set_sample_id(fs_inst *inst,
 744                                struct brw_reg dst,
 745                                struct brw_reg src0,
 746                                struct brw_reg src1);
 747
 748    void generate_set_simd4x2_offset(fs_inst *inst,
 749                                     struct brw_reg dst,
 750                                     struct brw_reg offset);
 751    void generate_discard_jump(fs_inst *inst);
 752
 753    void generate_pack_half_2x16_split(fs_inst *inst,
 754                                       struct brw_reg dst,
 755                                       struct brw_reg x,
 756                                       struct brw_reg y);
 757    void generate_unpack_half_2x16_split(fs_inst *inst,
 758                                         struct brw_reg dst,
 759                                         struct brw_reg src);
 760
 761    void generate_shader_time_add(fs_inst *inst,
 762                                  struct brw_reg payload,
 763                                  struct brw_reg offset,
 764                                  struct brw_reg value);
 765
 766    void generate_untyped_atomic(fs_inst *inst,
 767                                 struct brw_reg dst,
 768                                 struct brw_reg payload,
 769                                 struct brw_reg atomic_op,
 770                                 struct brw_reg surf_index);
 771
 772    void generate_untyped_surface_read(fs_inst *inst,
 773                                       struct brw_reg dst,
 774                                       struct brw_reg payload,
 775                                       struct brw_reg surf_index);
 776
 777    bool patch_discard_jumps_to_fb_writes();
 778
 779    struct brw_context *brw;
 780    struct gl_context *ctx;
 781
 782    struct brw_compile *p;
 783    gl_shader_stage stage;
 784    const void * const key;
 785    struct brw_stage_prog_data * const prog_data;
 786
 787    struct gl_shader_program * const shader_prog;
 788    const struct gl_program *prog;
 789
 790    unsigned dispatch_width; /**< 8 or 16 */
 791
 792    exec_list discard_halt_patches;
 793    bool runtime_check_aads_emit;
 794    const bool debug_flag;
 795    void *mem_ctx;
 796 };
 797
 798 bool brw_do_channel_expressions(struct exec_list *instructions);
 799 bool brw_do_vector_splitting(struct exec_list *instructions);
 800 bool brw_fs_precompile(struct gl_context *ctx,
 801                        struct gl_shader_program *shader_prog,
 802                        struct gl_program *prog);
 803
 804 struct brw_reg brw_reg_from_fs_reg(fs_reg *reg);