2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include "brw_shader.h"
34 #include <sys/types.h>
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/uniforms.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/prog_optimize.h"
42 #include "program/register_allocate.h"
43 #include "program/sampler.h"
44 #include "program/hash_table.h"
45 #include "brw_context.h"
48 #include "brw_shader.h"
50 #include "gen8_generator.h"
51 #include "glsl/glsl_types.h"
54 #define MAX_SAMPLER_MESSAGE_SIZE 11
62 class fs_live_variables
;
67 DECLARE_RALLOC_CXX_OPERATORS(fs_reg
)
75 fs_reg(struct brw_reg fixed_hw_reg
);
76 fs_reg(enum register_file file
, int reg
);
77 fs_reg(enum register_file file
, int reg
, uint32_t type
);
78 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
80 bool equals(const fs_reg
&r
) const;
84 bool is_valid_3src() const;
85 bool is_contiguous() const;
86 bool is_accumulator() const;
88 fs_reg
&apply_stride(unsigned stride
);
89 /** Smear a channel of the reg to all channels. */
90 fs_reg
&set_smear(unsigned subreg
);
92 /** Register file: GRF, MRF, IMM. */
93 enum register_file file
;
94 /** Register type. BRW_REGISTER_TYPE_* */
97 * Register number. For MRF, it's the hardware register. For
98 * GRF, it's a virtual register number until register allocation
102 * Offset from the start of the contiguous register block.
104 * For pre-register-allocation GRFs, this is in units of a float per pixel
105 * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
106 * For uniforms, this is in units of 1 float.
110 * Offset in bytes from the start of the register. Values up to a
111 * backend_reg::reg_offset unit are valid.
115 /** Value for file == IMM */
122 struct brw_reg fixed_hw_reg
;
129 /** Register region horizontal stride */
134 retype(fs_reg reg
, unsigned type
)
136 reg
.fixed_hw_reg
.type
= reg
.type
= type
;
141 offset(fs_reg reg
, unsigned delta
)
143 assert(delta
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
144 reg
.reg_offset
+= delta
;
149 byte_offset(fs_reg reg
, unsigned delta
)
151 assert(delta
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
152 reg
.subreg_offset
+= delta
;
157 * Get either of the 8-component halves of a 16-component register.
159 * Note: this also works if \c reg represents a SIMD16 pair of registers.
162 half(const fs_reg
®
, unsigned idx
)
165 assert(idx
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
166 return byte_offset(reg
, 8 * idx
* reg
.stride
* type_sz(reg
.type
));
169 static const fs_reg reg_undef
;
170 static const fs_reg
reg_null_f(retype(brw_null_reg(), BRW_REGISTER_TYPE_F
));
171 static const fs_reg
reg_null_d(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
172 static const fs_reg
reg_null_ud(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
174 class ip_record
: public exec_node
{
176 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
186 class fs_inst
: public backend_instruction
{
188 DECLARE_RALLOC_CXX_OPERATORS(fs_inst
)
193 fs_inst(enum opcode opcode
);
194 fs_inst(enum opcode opcode
, fs_reg dst
);
195 fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
);
196 fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
197 fs_inst(enum opcode opcode
, fs_reg dst
,
198 fs_reg src0
, fs_reg src1
,fs_reg src2
);
200 bool equals(fs_inst
*inst
) const;
201 bool overwrites_reg(const fs_reg
®
) const;
202 bool is_send_from_grf() const;
203 bool is_partial_write() const;
204 int regs_read(fs_visitor
*v
, int arg
) const;
206 bool reads_flag() const;
207 bool writes_flag() const;
213 * Annotation for the generated IR. One of the two can be set.
216 const char *annotation
;
219 uint32_t texture_offset
; /**< Texture offset bitfield */
220 uint32_t offset
; /* spill/unspill offset */
222 uint8_t conditional_mod
; /**< BRW_CONDITIONAL_* */
224 /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
225 * mod and predication.
229 uint8_t mlen
; /**< SEND message length */
230 uint8_t regs_written
; /**< Number of vgrfs written by a SEND message, or 1 */
231 int8_t base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
233 uint8_t target
; /**< MRT target. */
236 bool header_present
:1;
237 bool shadow_compare
:1;
238 bool force_uncompressed
:1;
239 bool force_sechalf
:1;
240 bool force_writemask_all
:1;
244 * The fragment shader front-end.
246 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
248 class fs_visitor
: public backend_visitor
252 fs_visitor(struct brw_context
*brw
,
253 struct brw_wm_compile
*c
,
254 struct gl_shader_program
*shader_prog
,
255 struct gl_fragment_program
*fp
,
256 unsigned dispatch_width
);
259 fs_reg
*variable_storage(ir_variable
*var
);
260 int virtual_grf_alloc(int size
);
261 void import_uniforms(fs_visitor
*v
);
263 void visit(ir_variable
*ir
);
264 void visit(ir_assignment
*ir
);
265 void visit(ir_dereference_variable
*ir
);
266 void visit(ir_dereference_record
*ir
);
267 void visit(ir_dereference_array
*ir
);
268 void visit(ir_expression
*ir
);
269 void visit(ir_texture
*ir
);
270 void visit(ir_if
*ir
);
271 void visit(ir_constant
*ir
);
272 void visit(ir_swizzle
*ir
);
273 void visit(ir_return
*ir
);
274 void visit(ir_loop
*ir
);
275 void visit(ir_loop_jump
*ir
);
276 void visit(ir_discard
*ir
);
277 void visit(ir_call
*ir
);
278 void visit(ir_function
*ir
);
279 void visit(ir_function_signature
*ir
);
280 void visit(ir_emit_vertex
*);
281 void visit(ir_end_primitive
*);
283 uint32_t gather_channel(ir_texture
*ir
, int sampler
);
284 void swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
);
286 bool can_do_source_mods(fs_inst
*inst
);
288 fs_inst
*emit(fs_inst
*inst
);
289 void emit(exec_list list
);
291 fs_inst
*emit(enum opcode opcode
);
292 fs_inst
*emit(enum opcode opcode
, fs_reg dst
);
293 fs_inst
*emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
);
294 fs_inst
*emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
295 fs_inst
*emit(enum opcode opcode
, fs_reg dst
,
296 fs_reg src0
, fs_reg src1
, fs_reg src2
);
298 fs_inst
*MOV(fs_reg dst
, fs_reg src
);
299 fs_inst
*NOT(fs_reg dst
, fs_reg src
);
300 fs_inst
*RNDD(fs_reg dst
, fs_reg src
);
301 fs_inst
*RNDE(fs_reg dst
, fs_reg src
);
302 fs_inst
*RNDZ(fs_reg dst
, fs_reg src
);
303 fs_inst
*FRC(fs_reg dst
, fs_reg src
);
304 fs_inst
*ADD(fs_reg dst
, fs_reg src0
, fs_reg src1
);
305 fs_inst
*MUL(fs_reg dst
, fs_reg src0
, fs_reg src1
);
306 fs_inst
*MACH(fs_reg dst
, fs_reg src0
, fs_reg src1
);
307 fs_inst
*MAC(fs_reg dst
, fs_reg src0
, fs_reg src1
);
308 fs_inst
*SHL(fs_reg dst
, fs_reg src0
, fs_reg src1
);
309 fs_inst
*SHR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
310 fs_inst
*ASR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
311 fs_inst
*AND(fs_reg dst
, fs_reg src0
, fs_reg src1
);
312 fs_inst
*OR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
313 fs_inst
*XOR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
314 fs_inst
*IF(uint32_t predicate
);
315 fs_inst
*IF(fs_reg src0
, fs_reg src1
, uint32_t condition
);
316 fs_inst
*CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
,
318 fs_inst
*LRP(fs_reg dst
, fs_reg a
, fs_reg y
, fs_reg x
);
319 fs_inst
*DEP_RESOLVE_MOV(int grf
);
320 fs_inst
*BFREV(fs_reg dst
, fs_reg value
);
321 fs_inst
*BFE(fs_reg dst
, fs_reg bits
, fs_reg offset
, fs_reg value
);
322 fs_inst
*BFI1(fs_reg dst
, fs_reg bits
, fs_reg offset
);
323 fs_inst
*BFI2(fs_reg dst
, fs_reg bfi1_dst
, fs_reg insert
, fs_reg base
);
324 fs_inst
*FBH(fs_reg dst
, fs_reg value
);
325 fs_inst
*FBL(fs_reg dst
, fs_reg value
);
326 fs_inst
*CBIT(fs_reg dst
, fs_reg value
);
327 fs_inst
*MAD(fs_reg dst
, fs_reg c
, fs_reg b
, fs_reg a
);
328 fs_inst
*ADDC(fs_reg dst
, fs_reg src0
, fs_reg src1
);
329 fs_inst
*SUBB(fs_reg dst
, fs_reg src0
, fs_reg src1
);
330 fs_inst
*SEL(fs_reg dst
, fs_reg src0
, fs_reg src1
);
332 int type_size(const struct glsl_type
*type
);
333 fs_inst
*get_instruction_generating_reg(fs_inst
*start
,
337 exec_list
VARYING_PULL_CONSTANT_LOAD(const fs_reg
&dst
,
338 const fs_reg
&surf_index
,
339 const fs_reg
&varying_offset
,
340 uint32_t const_offset
);
343 void assign_binding_table_offsets();
344 void setup_payload_gen4();
345 void setup_payload_gen6();
346 void assign_curb_setup();
347 void calculate_urb_setup();
348 void assign_urb_setup();
349 bool assign_regs(bool allow_spilling
);
350 void assign_regs_trivial();
351 void get_used_mrfs(bool *mrf_used
);
352 void setup_payload_interference(struct ra_graph
*g
, int payload_reg_count
,
353 int first_payload_node
);
354 void setup_mrf_hack_interference(struct ra_graph
*g
,
355 int first_mrf_hack_node
);
356 int choose_spill_reg(struct ra_graph
*g
);
357 void spill_reg(int spill_reg
);
358 void split_virtual_grfs();
359 void compact_virtual_grfs();
360 void move_uniform_array_access_to_pull_constants();
361 void assign_constant_locations();
362 void demote_pull_constants();
363 void invalidate_live_intervals();
364 void calculate_live_intervals();
365 void calculate_register_pressure();
366 bool opt_algebraic();
368 bool opt_cse_local(bblock_t
*block
, exec_list
*aeb
);
369 bool opt_copy_propagate();
370 bool try_copy_propagate(fs_inst
*inst
, int arg
, acp_entry
*entry
);
371 bool try_constant_propagate(fs_inst
*inst
, acp_entry
*entry
);
372 bool opt_copy_propagate_local(void *mem_ctx
, bblock_t
*block
,
374 void opt_drop_redundant_mov_to_flags();
375 bool register_coalesce();
376 bool compute_to_mrf();
377 bool dead_code_eliminate();
378 bool remove_duplicate_mrf_writes();
379 bool virtual_grf_interferes(int a
, int b
);
380 void schedule_instructions(instruction_scheduler_mode mode
);
381 void insert_gen4_send_dependency_workarounds();
382 void insert_gen4_pre_send_dependency_workarounds(fs_inst
*inst
);
383 void insert_gen4_post_send_dependency_workarounds(fs_inst
*inst
);
384 void vfail(const char *msg
, va_list args
);
385 void fail(const char *msg
, ...);
386 void no16(const char *msg
, ...);
387 void lower_uniform_pull_constant_loads();
389 void push_force_uncompressed();
390 void pop_force_uncompressed();
392 void emit_dummy_fs();
393 fs_reg
*emit_fragcoord_interpolation(ir_variable
*ir
);
394 fs_inst
*emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
395 glsl_interp_qualifier interpolation_mode
,
396 bool is_centroid
, bool is_sample
);
397 fs_reg
*emit_frontfacing_interpolation(ir_variable
*ir
);
398 fs_reg
*emit_samplepos_setup(ir_variable
*ir
);
399 fs_reg
*emit_sampleid_setup(ir_variable
*ir
);
400 fs_reg
*emit_general_interpolation(ir_variable
*ir
);
401 void emit_interpolation_setup_gen4();
402 void emit_interpolation_setup_gen6();
403 void compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
);
404 fs_reg
rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
405 bool is_rect
, int sampler
, int texunit
);
406 fs_inst
*emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
407 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
);
408 fs_inst
*emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
409 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
,
410 fs_reg sample_index
);
411 fs_inst
*emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
412 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
,
413 fs_reg sample_index
, fs_reg mcs
, int sampler
);
414 fs_reg
emit_mcs_fetch(ir_texture
*ir
, fs_reg coordinate
, int sampler
);
415 void emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
);
416 fs_reg
fix_math_operand(fs_reg src
);
417 fs_inst
*emit_math(enum opcode op
, fs_reg dst
, fs_reg src0
);
418 fs_inst
*emit_math(enum opcode op
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
419 void emit_lrp(const fs_reg
&dst
, const fs_reg
&x
, const fs_reg
&y
,
421 void emit_minmax(uint32_t conditionalmod
, const fs_reg
&dst
,
422 const fs_reg
&src0
, const fs_reg
&src1
);
423 bool try_emit_saturate(ir_expression
*ir
);
424 bool try_emit_mad(ir_expression
*ir
);
425 void try_replace_with_sel();
426 bool opt_peephole_sel();
427 bool opt_peephole_predicated_break();
428 bool opt_saturate_propagation();
429 void emit_bool_to_cond_code(ir_rvalue
*condition
);
430 void emit_if_gen6(ir_if
*ir
);
431 void emit_unspill(fs_inst
*inst
, fs_reg reg
, uint32_t spill_offset
,
434 void emit_fragment_program_code();
435 void setup_fp_regs();
436 fs_reg
get_fp_src_reg(const prog_src_register
*src
);
437 fs_reg
get_fp_dst_reg(const prog_dst_register
*dst
);
438 void emit_fp_alu1(enum opcode opcode
,
439 const struct prog_instruction
*fpi
,
440 fs_reg dst
, fs_reg src
);
441 void emit_fp_alu2(enum opcode opcode
,
442 const struct prog_instruction
*fpi
,
443 fs_reg dst
, fs_reg src0
, fs_reg src1
);
444 void emit_fp_scalar_write(const struct prog_instruction
*fpi
,
445 fs_reg dst
, fs_reg src
);
446 void emit_fp_scalar_math(enum opcode opcode
,
447 const struct prog_instruction
*fpi
,
448 fs_reg dst
, fs_reg src
);
450 void emit_fp_minmax(const struct prog_instruction
*fpi
,
451 fs_reg dst
, fs_reg src0
, fs_reg src1
);
453 void emit_fp_sop(uint32_t conditional_mod
,
454 const struct prog_instruction
*fpi
,
455 fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg one
);
457 void emit_color_write(int target
, int index
, int first_color_mrf
);
458 void emit_alpha_test();
459 void emit_fb_writes();
461 void emit_shader_time_begin();
462 void emit_shader_time_end();
463 void emit_shader_time_write(enum shader_time_shader_type type
,
466 void emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
467 fs_reg dst
, fs_reg offset
, fs_reg src0
,
470 void emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
473 bool try_rewrite_rhs_to_dst(ir_assignment
*ir
,
476 fs_inst
*pre_rhs_inst
,
477 fs_inst
*last_rhs_inst
);
478 void emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
479 const glsl_type
*type
, bool predicated
);
480 void resolve_ud_negate(fs_reg
*reg
);
481 void resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
);
483 fs_reg
get_timestamp();
485 struct brw_reg
interp_reg(int location
, int channel
);
486 void setup_uniform_values(ir_variable
*ir
);
487 void setup_builtin_uniform_values(ir_variable
*ir
);
488 int implied_mrf_writes(fs_inst
*inst
);
490 virtual void dump_instructions();
491 void dump_instruction(backend_instruction
*inst
);
493 void visit_atomic_counter_intrinsic(ir_call
*ir
);
495 struct gl_fragment_program
*fp
;
496 struct brw_wm_compile
*c
;
497 const struct brw_wm_prog_key
*const key
;
498 struct brw_wm_prog_data
*prog_data
;
499 unsigned int sanity_param_count
;
503 int *virtual_grf_sizes
;
504 int virtual_grf_count
;
505 int virtual_grf_array_size
;
506 int *virtual_grf_start
;
507 int *virtual_grf_end
;
508 brw::fs_live_variables
*live_intervals
;
510 int *regs_live_at_ip
;
512 /** Number of uniform variable components visited. */
515 /** Byte-offset for the next available spot in the scratch space buffer. */
516 unsigned last_scratch
;
519 * Array mapping UNIFORM register numbers to the pull parameter index,
520 * or -1 if this uniform register isn't being uploaded as a pull constant.
522 int *pull_constant_loc
;
525 * Array mapping UNIFORM register numbers to the push parameter index,
526 * or -1 if this uniform register isn't being uploaded as a push constant.
528 int *push_constant_loc
;
530 struct hash_table
*variable_ht
;
533 fs_reg outputs
[BRW_MAX_DRAW_BUFFERS
];
534 unsigned output_components
[BRW_MAX_DRAW_BUFFERS
];
535 fs_reg dual_src_output
;
537 int first_non_payload_grf
;
538 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
541 fs_reg
*fp_temp_regs
;
542 fs_reg
*fp_input_regs
;
544 /** @{ debug annotation info */
545 const char *current_annotation
;
551 bool simd16_unsupported
;
554 /* Result of last visit() method. */
557 /** Register numbers for thread payload fields. */
559 uint8_t source_depth_reg
;
560 uint8_t source_w_reg
;
561 uint8_t aa_dest_stencil_reg
;
562 uint8_t dest_depth_reg
;
563 uint8_t sample_pos_reg
;
564 uint8_t sample_mask_in_reg
;
565 uint8_t barycentric_coord_reg
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
567 /** The number of thread payload registers the hardware will supply. */
571 bool source_depth_to_render_target
;
572 bool runtime_check_aads_emit
;
578 fs_reg delta_x
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
579 fs_reg delta_y
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
580 fs_reg shader_start_time
;
583 bool spilled_any_registers
;
585 const unsigned dispatch_width
; /**< 8 or 16 */
587 int force_uncompressed_stack
;
591 * The fragment shader code generator.
593 * Translates FS IR to actual i965 assembly code.
598 fs_generator(struct brw_context
*brw
,
599 struct brw_wm_compile
*c
,
600 struct gl_shader_program
*prog
,
601 struct gl_fragment_program
*fp
,
602 bool dual_source_output
);
605 const unsigned *generate_assembly(exec_list
*simd8_instructions
,
606 exec_list
*simd16_instructions
,
607 unsigned *assembly_size
,
608 FILE *dump_file
= NULL
);
611 void generate_code(exec_list
*instructions
, FILE *dump_file
);
612 void generate_fb_write(fs_inst
*inst
);
613 void generate_blorp_fb_write(fs_inst
*inst
);
614 void generate_pixel_xy(struct brw_reg dst
, bool is_x
);
615 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
616 struct brw_reg
*src
);
617 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
618 void generate_math1_gen7(fs_inst
*inst
,
621 void generate_math2_gen7(fs_inst
*inst
,
624 struct brw_reg src1
);
625 void generate_math1_gen6(fs_inst
*inst
,
628 void generate_math2_gen6(fs_inst
*inst
,
631 struct brw_reg src1
);
632 void generate_math_gen4(fs_inst
*inst
,
635 void generate_math_g45(fs_inst
*inst
,
638 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
639 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
641 void generate_scratch_write(fs_inst
*inst
, struct brw_reg src
);
642 void generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
);
643 void generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
);
644 void generate_uniform_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
,
645 struct brw_reg index
,
646 struct brw_reg offset
);
647 void generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
649 struct brw_reg surf_index
,
650 struct brw_reg offset
);
651 void generate_varying_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
,
652 struct brw_reg index
,
653 struct brw_reg offset
);
654 void generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
656 struct brw_reg index
,
657 struct brw_reg offset
);
658 void generate_mov_dispatch_to_flags(fs_inst
*inst
);
660 void generate_set_omask(fs_inst
*inst
,
662 struct brw_reg sample_mask
);
664 void generate_set_sample_id(fs_inst
*inst
,
667 struct brw_reg src1
);
669 void generate_set_simd4x2_offset(fs_inst
*inst
,
671 struct brw_reg offset
);
672 void generate_discard_jump(fs_inst
*inst
);
674 void generate_pack_half_2x16_split(fs_inst
*inst
,
678 void generate_unpack_half_2x16_split(fs_inst
*inst
,
682 void generate_shader_time_add(fs_inst
*inst
,
683 struct brw_reg payload
,
684 struct brw_reg offset
,
685 struct brw_reg value
);
687 void generate_untyped_atomic(fs_inst
*inst
,
689 struct brw_reg atomic_op
,
690 struct brw_reg surf_index
);
692 void generate_untyped_surface_read(fs_inst
*inst
,
694 struct brw_reg surf_index
);
696 void patch_discard_jumps_to_fb_writes();
698 struct brw_context
*brw
;
699 struct gl_context
*ctx
;
701 struct brw_compile
*p
;
702 struct brw_wm_compile
*c
;
703 struct brw_wm_prog_data
*prog_data
;
705 struct gl_shader_program
*prog
;
706 const struct gl_fragment_program
*fp
;
708 unsigned dispatch_width
; /**< 8 or 16 */
710 exec_list discard_halt_patches
;
711 bool dual_source_output
;
716 * The fragment shader code generator.
718 * Translates FS IR to actual i965 assembly code.
720 class gen8_fs_generator
: public gen8_generator
723 gen8_fs_generator(struct brw_context
*brw
,
724 struct brw_wm_compile
*c
,
725 struct gl_shader_program
*prog
,
726 struct gl_fragment_program
*fp
,
727 bool dual_source_output
);
728 ~gen8_fs_generator();
730 const unsigned *generate_assembly(exec_list
*simd8_instructions
,
731 exec_list
*simd16_instructions
,
732 unsigned *assembly_size
);
735 void generate_code(exec_list
*instructions
);
736 void generate_fb_write(fs_inst
*inst
);
737 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
738 struct brw_reg
*src
);
739 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
740 void generate_math1(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
741 void generate_math2(fs_inst
*inst
, struct brw_reg dst
,
742 struct brw_reg src0
, struct brw_reg src1
);
743 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
744 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
746 void generate_scratch_write(fs_inst
*inst
, struct brw_reg src
);
747 void generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
);
748 void generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
);
749 void generate_uniform_pull_constant_load(fs_inst
*inst
,
751 struct brw_reg index
,
752 struct brw_reg offset
);
753 void generate_varying_pull_constant_load(fs_inst
*inst
,
755 struct brw_reg index
,
756 struct brw_reg offset
);
757 void generate_mov_dispatch_to_flags(fs_inst
*ir
);
758 void generate_set_omask(fs_inst
*ir
,
760 struct brw_reg sample_mask
);
761 void generate_set_sample_id(fs_inst
*ir
,
764 struct brw_reg src1
);
765 void generate_set_simd4x2_offset(fs_inst
*ir
,
767 struct brw_reg offset
);
768 void generate_pack_half_2x16_split(fs_inst
*inst
,
772 void generate_unpack_half_2x16_split(fs_inst
*inst
,
775 void generate_untyped_atomic(fs_inst
*inst
,
777 struct brw_reg atomic_op
,
778 struct brw_reg surf_index
);
780 void generate_untyped_surface_read(fs_inst
*inst
,
782 struct brw_reg surf_index
);
783 void generate_discard_jump(fs_inst
*ir
);
785 void patch_discard_jumps_to_fb_writes();
787 struct brw_wm_compile
*c
;
788 struct brw_wm_prog_data
*prog_data
;
789 const struct gl_fragment_program
*fp
;
791 unsigned dispatch_width
; /** 8 or 16 */
793 bool dual_source_output
;
795 exec_list discard_halt_patches
;
798 bool brw_do_channel_expressions(struct exec_list
*instructions
);
799 bool brw_do_vector_splitting(struct exec_list
*instructions
);
800 bool brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
);
802 struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
);