src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31
  32 extern "C" {
  33
  34 #include <sys/types.h>
  35
  36 #include "main/macros.h"
  37 #include "main/shaderobj.h"
  38 #include "main/uniforms.h"
  39 #include "program/prog_parameter.h"
  40 #include "program/prog_print.h"
  41 #include "program/prog_optimize.h"
  42 #include "program/register_allocate.h"
  43 #include "program/sampler.h"
  44 #include "program/hash_table.h"
  45 #include "brw_context.h"
  46 #include "brw_eu.h"
  47 #include "brw_wm.h"
  48 #include "brw_shader.h"
  49 }
  50 #include "gen8_generator.h"
  51 #include "glsl/glsl_types.h"
  52 #include "glsl/ir.h"
  53
  54 #define MAX_SAMPLER_MESSAGE_SIZE 11
  55
  56 class bblock_t;
  57 namespace {
  58    struct acp_entry;
  59 }
  60
  61 namespace brw {
  62    class fs_live_variables;
  63 }
  64
  65 class fs_reg {
  66 public:
  67    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  68
  69    void init();
  70
  71    fs_reg();
  72    fs_reg(float f);
  73    fs_reg(int32_t i);
  74    fs_reg(uint32_t u);
  75    fs_reg(struct brw_reg fixed_hw_reg);
  76    fs_reg(enum register_file file, int reg);
  77    fs_reg(enum register_file file, int reg, uint32_t type);
  78    fs_reg(class fs_visitor *v, const struct glsl_type *type);
  79
  80    bool equals(const fs_reg &r) const;
  81    bool is_zero() const;
  82    bool is_one() const;
  83    bool is_null() const;
  84    bool is_valid_3src() const;
  85    bool is_contiguous() const;
  86    bool is_accumulator() const;
  87
  88    fs_reg &apply_stride(unsigned stride);
  89    /** Smear a channel of the reg to all channels. */
  90    fs_reg &set_smear(unsigned subreg);
  91
  92    /** Register file: GRF, MRF, IMM. */
  93    enum register_file file;
  94    /** Register type.  BRW_REGISTER_TYPE_* */
  95    uint8_t type;
  96    /**
  97     * Register number.  For MRF, it's the hardware register.  For
  98     * GRF, it's a virtual register number until register allocation
  99     */
 100    uint16_t reg;
 101    /**
 102     * Offset from the start of the contiguous register block.
 103     *
 104     * For pre-register-allocation GRFs, this is in units of a float per pixel
 105     * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
 106     * For uniforms, this is in units of 1 float.
 107     */
 108    int reg_offset;
 109    /**
 110     * Offset in bytes from the start of the register.  Values up to a
 111     * backend_reg::reg_offset unit are valid.
 112     */
 113    int subreg_offset;
 114
 115    /** Value for file == IMM */
 116    union {
 117       int32_t i;
 118       uint32_t u;
 119       float f;
 120    } imm;
 121
 122    struct brw_reg fixed_hw_reg;
 123
 124    fs_reg *reladdr;
 125
 126    bool negate;
 127    bool abs;
 128
 129    /** Register region horizontal stride */
 130    uint8_t stride;
 131 };
 132
 133 static inline fs_reg
 134 retype(fs_reg reg, unsigned type)
 135 {
 136    reg.fixed_hw_reg.type = reg.type = type;
 137    return reg;
 138 }
 139
 140 static inline fs_reg
 141 offset(fs_reg reg, unsigned delta)
 142 {
 143    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 144    reg.reg_offset += delta;
 145    return reg;
 146 }
 147
 148 static inline fs_reg
 149 byte_offset(fs_reg reg, unsigned delta)
 150 {
 151    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 152    reg.subreg_offset += delta;
 153    return reg;
 154 }
 155
 156 /**
 157  * Get either of the 8-component halves of a 16-component register.
 158  *
 159  * Note: this also works if \c reg represents a SIMD16 pair of registers.
 160  */
 161 static inline fs_reg
 162 half(const fs_reg &reg, unsigned idx)
 163 {
 164    assert(idx < 2);
 165    assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
 166    return byte_offset(reg, 8 * idx * reg.stride * type_sz(reg.type));
 167 }
 168
 169 static const fs_reg reg_undef;
 170 static const fs_reg reg_null_f(retype(brw_null_reg(), BRW_REGISTER_TYPE_F));
 171 static const fs_reg reg_null_d(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 172 static const fs_reg reg_null_ud(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 173
 174 class ip_record : public exec_node {
 175 public:
 176    DECLARE_RALLOC_CXX_OPERATORS(ip_record)
 177
 178    ip_record(int ip)
 179    {
 180       this->ip = ip;
 181    }
 182
 183    int ip;
 184 };
 185
 186 class fs_inst : public backend_instruction {
 187 public:
 188    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 189
 190    void init();
 191
 192    fs_inst();
 193    fs_inst(enum opcode opcode);
 194    fs_inst(enum opcode opcode, fs_reg dst);
 195    fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0);
 196    fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
 197    fs_inst(enum opcode opcode, fs_reg dst,
 198            fs_reg src0, fs_reg src1,fs_reg src2);
 199
 200    bool equals(fs_inst *inst) const;
 201    bool overwrites_reg(const fs_reg &reg) const;
 202    bool is_send_from_grf() const;
 203    bool is_partial_write() const;
 204    int regs_read(fs_visitor *v, int arg) const;
 205
 206    bool reads_flag() const;
 207    bool writes_flag() const;
 208
 209    fs_reg dst;
 210    fs_reg src[3];
 211
 212    /** @{
 213     * Annotation for the generated IR.  One of the two can be set.
 214     */
 215    const void *ir;
 216    const char *annotation;
 217    /** @} */
 218
 219    uint32_t texture_offset; /**< Texture offset bitfield */
 220    uint32_t offset; /* spill/unspill offset */
 221
 222    uint8_t conditional_mod; /**< BRW_CONDITIONAL_* */
 223
 224    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 225     * mod and predication.
 226     */
 227    uint8_t flag_subreg;
 228
 229    uint8_t mlen; /**< SEND message length */
 230    uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
 231    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 232    uint8_t sampler;
 233    uint8_t target; /**< MRT target. */
 234    bool saturate:1;
 235    bool eot:1;
 236    bool header_present:1;
 237    bool shadow_compare:1;
 238    bool force_uncompressed:1;
 239    bool force_sechalf:1;
 240    bool force_writemask_all:1;
 241 };
 242
 243 /**
 244  * The fragment shader front-end.
 245  *
 246  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
 247  */
 248 class fs_visitor : public backend_visitor
 249 {
 250 public:
 251
 252    fs_visitor(struct brw_context *brw,
 253               struct brw_wm_compile *c,
 254               struct gl_shader_program *shader_prog,
 255               struct gl_fragment_program *fp,
 256               unsigned dispatch_width);
 257    ~fs_visitor();
 258
 259    fs_reg *variable_storage(ir_variable *var);
 260    int virtual_grf_alloc(int size);
 261    void import_uniforms(fs_visitor *v);
 262
 263    void visit(ir_variable *ir);
 264    void visit(ir_assignment *ir);
 265    void visit(ir_dereference_variable *ir);
 266    void visit(ir_dereference_record *ir);
 267    void visit(ir_dereference_array *ir);
 268    void visit(ir_expression *ir);
 269    void visit(ir_texture *ir);
 270    void visit(ir_if *ir);
 271    void visit(ir_constant *ir);
 272    void visit(ir_swizzle *ir);
 273    void visit(ir_return *ir);
 274    void visit(ir_loop *ir);
 275    void visit(ir_loop_jump *ir);
 276    void visit(ir_discard *ir);
 277    void visit(ir_call *ir);
 278    void visit(ir_function *ir);
 279    void visit(ir_function_signature *ir);
 280    void visit(ir_emit_vertex *);
 281    void visit(ir_end_primitive *);
 282
 283    uint32_t gather_channel(ir_texture *ir, int sampler);
 284    void swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler);
 285
 286    bool can_do_source_mods(fs_inst *inst);
 287
 288    fs_inst *emit(fs_inst *inst);
 289    void emit(exec_list list);
 290
 291    fs_inst *emit(enum opcode opcode);
 292    fs_inst *emit(enum opcode opcode, fs_reg dst);
 293    fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0);
 294    fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
 295    fs_inst *emit(enum opcode opcode, fs_reg dst,
 296                  fs_reg src0, fs_reg src1, fs_reg src2);
 297
 298    fs_inst *MOV(fs_reg dst, fs_reg src);
 299    fs_inst *NOT(fs_reg dst, fs_reg src);
 300    fs_inst *RNDD(fs_reg dst, fs_reg src);
 301    fs_inst *RNDE(fs_reg dst, fs_reg src);
 302    fs_inst *RNDZ(fs_reg dst, fs_reg src);
 303    fs_inst *FRC(fs_reg dst, fs_reg src);
 304    fs_inst *ADD(fs_reg dst, fs_reg src0, fs_reg src1);
 305    fs_inst *MUL(fs_reg dst, fs_reg src0, fs_reg src1);
 306    fs_inst *MACH(fs_reg dst, fs_reg src0, fs_reg src1);
 307    fs_inst *MAC(fs_reg dst, fs_reg src0, fs_reg src1);
 308    fs_inst *SHL(fs_reg dst, fs_reg src0, fs_reg src1);
 309    fs_inst *SHR(fs_reg dst, fs_reg src0, fs_reg src1);
 310    fs_inst *ASR(fs_reg dst, fs_reg src0, fs_reg src1);
 311    fs_inst *AND(fs_reg dst, fs_reg src0, fs_reg src1);
 312    fs_inst *OR(fs_reg dst, fs_reg src0, fs_reg src1);
 313    fs_inst *XOR(fs_reg dst, fs_reg src0, fs_reg src1);
 314    fs_inst *IF(uint32_t predicate);
 315    fs_inst *IF(fs_reg src0, fs_reg src1, uint32_t condition);
 316    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 317                 uint32_t condition);
 318    fs_inst *LRP(fs_reg dst, fs_reg a, fs_reg y, fs_reg x);
 319    fs_inst *DEP_RESOLVE_MOV(int grf);
 320    fs_inst *BFREV(fs_reg dst, fs_reg value);
 321    fs_inst *BFE(fs_reg dst, fs_reg bits, fs_reg offset, fs_reg value);
 322    fs_inst *BFI1(fs_reg dst, fs_reg bits, fs_reg offset);
 323    fs_inst *BFI2(fs_reg dst, fs_reg bfi1_dst, fs_reg insert, fs_reg base);
 324    fs_inst *FBH(fs_reg dst, fs_reg value);
 325    fs_inst *FBL(fs_reg dst, fs_reg value);
 326    fs_inst *CBIT(fs_reg dst, fs_reg value);
 327    fs_inst *MAD(fs_reg dst, fs_reg c, fs_reg b, fs_reg a);
 328    fs_inst *ADDC(fs_reg dst, fs_reg src0, fs_reg src1);
 329    fs_inst *SUBB(fs_reg dst, fs_reg src0, fs_reg src1);
 330    fs_inst *SEL(fs_reg dst, fs_reg src0, fs_reg src1);
 331
 332    int type_size(const struct glsl_type *type);
 333    fs_inst *get_instruction_generating_reg(fs_inst *start,
 334                                            fs_inst *end,
 335                                            const fs_reg &reg);
 336
 337    exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
 338                                         const fs_reg &surf_index,
 339                                         const fs_reg &varying_offset,
 340                                         uint32_t const_offset);
 341
 342    bool run();
 343    void assign_binding_table_offsets();
 344    void setup_payload_gen4();
 345    void setup_payload_gen6();
 346    void assign_curb_setup();
 347    void calculate_urb_setup();
 348    void assign_urb_setup();
 349    bool assign_regs(bool allow_spilling);
 350    void assign_regs_trivial();
 351    void get_used_mrfs(bool *mrf_used);
 352    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 353                                    int first_payload_node);
 354    void setup_mrf_hack_interference(struct ra_graph *g,
 355                                     int first_mrf_hack_node);
 356    int choose_spill_reg(struct ra_graph *g);
 357    void spill_reg(int spill_reg);
 358    void split_virtual_grfs();
 359    void compact_virtual_grfs();
 360    void move_uniform_array_access_to_pull_constants();
 361    void assign_constant_locations();
 362    void demote_pull_constants();
 363    void invalidate_live_intervals();
 364    void calculate_live_intervals();
 365    void calculate_register_pressure();
 366    bool opt_algebraic();
 367    bool opt_cse();
 368    bool opt_cse_local(bblock_t *block, exec_list *aeb);
 369    bool opt_copy_propagate();
 370    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 371    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 372    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 373                                  exec_list *acp);
 374    void opt_drop_redundant_mov_to_flags();
 375    bool register_coalesce();
 376    bool compute_to_mrf();
 377    bool dead_code_eliminate();
 378    bool remove_duplicate_mrf_writes();
 379    bool virtual_grf_interferes(int a, int b);
 380    void schedule_instructions(instruction_scheduler_mode mode);
 381    void insert_gen4_send_dependency_workarounds();
 382    void insert_gen4_pre_send_dependency_workarounds(fs_inst *inst);
 383    void insert_gen4_post_send_dependency_workarounds(fs_inst *inst);
 384    void vfail(const char *msg, va_list args);
 385    void fail(const char *msg, ...);
 386    void no16(const char *msg, ...);
 387    void lower_uniform_pull_constant_loads();
 388
 389    void push_force_uncompressed();
 390    void pop_force_uncompressed();
 391
 392    void emit_dummy_fs();
 393    fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
 394    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 395                          glsl_interp_qualifier interpolation_mode,
 396                          bool is_centroid, bool is_sample);
 397    fs_reg *emit_frontfacing_interpolation(ir_variable *ir);
 398    fs_reg *emit_samplepos_setup(ir_variable *ir);
 399    fs_reg *emit_sampleid_setup(ir_variable *ir);
 400    fs_reg *emit_samplemaskin_setup(ir_variable *ir);
 401    fs_reg *emit_general_interpolation(ir_variable *ir);
 402    void emit_interpolation_setup_gen4();
 403    void emit_interpolation_setup_gen6();
 404    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
 405    fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
 406                            bool is_rect, int sampler, int texunit);
 407    fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 408                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2);
 409    fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 410                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 411                               fs_reg sample_index);
 412    fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 413                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 414                               fs_reg sample_index, fs_reg mcs, int sampler);
 415    fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, int sampler);
 416    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
 417    fs_reg fix_math_operand(fs_reg src);
 418    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 419    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 420    void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
 421                  const fs_reg &a);
 422    void emit_minmax(uint32_t conditionalmod, const fs_reg &dst,
 423                     const fs_reg &src0, const fs_reg &src1);
 424    bool try_emit_saturate(ir_expression *ir);
 425    bool try_emit_mad(ir_expression *ir);
 426    void try_replace_with_sel();
 427    bool opt_peephole_sel();
 428    bool opt_peephole_predicated_break();
 429    bool opt_saturate_propagation();
 430    void emit_bool_to_cond_code(ir_rvalue *condition);
 431    void emit_if_gen6(ir_if *ir);
 432    void emit_unspill(fs_inst *inst, fs_reg reg, uint32_t spill_offset,
 433                      int count);
 434
 435    void emit_fragment_program_code();
 436    void setup_fp_regs();
 437    fs_reg get_fp_src_reg(const prog_src_register *src);
 438    fs_reg get_fp_dst_reg(const prog_dst_register *dst);
 439    void emit_fp_alu1(enum opcode opcode,
 440                      const struct prog_instruction *fpi,
 441                      fs_reg dst, fs_reg src);
 442    void emit_fp_alu2(enum opcode opcode,
 443                      const struct prog_instruction *fpi,
 444                      fs_reg dst, fs_reg src0, fs_reg src1);
 445    void emit_fp_scalar_write(const struct prog_instruction *fpi,
 446                              fs_reg dst, fs_reg src);
 447    void emit_fp_scalar_math(enum opcode opcode,
 448                             const struct prog_instruction *fpi,
 449                             fs_reg dst, fs_reg src);
 450
 451    void emit_fp_minmax(const struct prog_instruction *fpi,
 452                        fs_reg dst, fs_reg src0, fs_reg src1);
 453
 454    void emit_fp_sop(uint32_t conditional_mod,
 455                     const struct prog_instruction *fpi,
 456                     fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
 457
 458    void emit_color_write(int target, int index, int first_color_mrf);
 459    void emit_alpha_test();
 460    void emit_fb_writes();
 461
 462    void emit_shader_time_begin();
 463    void emit_shader_time_end();
 464    void emit_shader_time_write(enum shader_time_shader_type type,
 465                                fs_reg value);
 466
 467    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 468                             fs_reg dst, fs_reg offset, fs_reg src0,
 469                             fs_reg src1);
 470
 471    void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
 472                                   fs_reg offset);
 473
 474    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 475                                fs_reg dst,
 476                                fs_reg src,
 477                                fs_inst *pre_rhs_inst,
 478                                fs_inst *last_rhs_inst);
 479    void emit_assignment_writes(fs_reg &l, fs_reg &r,
 480                                const glsl_type *type, bool predicated);
 481    void resolve_ud_negate(fs_reg *reg);
 482    void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
 483
 484    fs_reg get_timestamp();
 485
 486    struct brw_reg interp_reg(int location, int channel);
 487    void setup_uniform_values(ir_variable *ir);
 488    void setup_builtin_uniform_values(ir_variable *ir);
 489    int implied_mrf_writes(fs_inst *inst);
 490
 491    virtual void dump_instructions();
 492    void dump_instruction(backend_instruction *inst);
 493
 494    void visit_atomic_counter_intrinsic(ir_call *ir);
 495
 496    struct gl_fragment_program *fp;
 497    struct brw_wm_compile *c;
 498    unsigned int sanity_param_count;
 499
 500    int *param_size;
 501
 502    int *virtual_grf_sizes;
 503    int virtual_grf_count;
 504    int virtual_grf_array_size;
 505    int *virtual_grf_start;
 506    int *virtual_grf_end;
 507    brw::fs_live_variables *live_intervals;
 508
 509    int *regs_live_at_ip;
 510
 511    /** Number of uniform variable components visited. */
 512    unsigned uniforms;
 513
 514    /**
 515     * Array mapping UNIFORM register numbers to the pull parameter index,
 516     * or -1 if this uniform register isn't being uploaded as a pull constant.
 517     */
 518    int *pull_constant_loc;
 519
 520    /**
 521     * Array mapping UNIFORM register numbers to the push parameter index,
 522     * or -1 if this uniform register isn't being uploaded as a push constant.
 523     */
 524    int *push_constant_loc;
 525
 526    struct hash_table *variable_ht;
 527    fs_reg frag_depth;
 528    fs_reg sample_mask;
 529    fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
 530    unsigned output_components[BRW_MAX_DRAW_BUFFERS];
 531    fs_reg dual_src_output;
 532    bool do_dual_src;
 533    int first_non_payload_grf;
 534    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 535    int max_grf;
 536
 537    fs_reg *fp_temp_regs;
 538    fs_reg *fp_input_regs;
 539
 540    /** @{ debug annotation info */
 541    const char *current_annotation;
 542    const void *base_ir;
 543    /** @} */
 544
 545    bool failed;
 546    char *fail_msg;
 547    bool simd16_unsupported;
 548    char *no16_msg;
 549
 550    /* Result of last visit() method. */
 551    fs_reg result;
 552
 553    fs_reg pixel_x;
 554    fs_reg pixel_y;
 555    fs_reg wpos_w;
 556    fs_reg pixel_w;
 557    fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 558    fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 559    fs_reg shader_start_time;
 560
 561    int grf_used;
 562    bool spilled_any_registers;
 563
 564    const unsigned dispatch_width; /**< 8 or 16 */
 565
 566    int force_uncompressed_stack;
 567 };
 568
 569 /**
 570  * The fragment shader code generator.
 571  *
 572  * Translates FS IR to actual i965 assembly code.
 573  */
 574 class fs_generator
 575 {
 576 public:
 577    fs_generator(struct brw_context *brw,
 578                 struct brw_wm_compile *c,
 579                 struct gl_shader_program *prog,
 580                 struct gl_fragment_program *fp,
 581                 bool dual_source_output);
 582    ~fs_generator();
 583
 584    const unsigned *generate_assembly(exec_list *simd8_instructions,
 585                                      exec_list *simd16_instructions,
 586                                      unsigned *assembly_size,
 587                                      FILE *dump_file = NULL);
 588
 589 private:
 590    void generate_code(exec_list *instructions, FILE *dump_file);
 591    void generate_fb_write(fs_inst *inst);
 592    void generate_blorp_fb_write(fs_inst *inst);
 593    void generate_pixel_xy(struct brw_reg dst, bool is_x);
 594    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 595                          struct brw_reg *src);
 596    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 597    void generate_math1_gen7(fs_inst *inst,
 598                             struct brw_reg dst,
 599                             struct brw_reg src);
 600    void generate_math2_gen7(fs_inst *inst,
 601                             struct brw_reg dst,
 602                             struct brw_reg src0,
 603                             struct brw_reg src1);
 604    void generate_math1_gen6(fs_inst *inst,
 605                             struct brw_reg dst,
 606                             struct brw_reg src);
 607    void generate_math2_gen6(fs_inst *inst,
 608                             struct brw_reg dst,
 609                             struct brw_reg src0,
 610                             struct brw_reg src1);
 611    void generate_math_gen4(fs_inst *inst,
 612                            struct brw_reg dst,
 613                            struct brw_reg src);
 614    void generate_math_g45(fs_inst *inst,
 615                           struct brw_reg dst,
 616                           struct brw_reg src);
 617    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 618    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 619                      bool negate_value);
 620    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 621    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 622    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 623    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 624                                             struct brw_reg index,
 625                                             struct brw_reg offset);
 626    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 627                                                  struct brw_reg dst,
 628                                                  struct brw_reg surf_index,
 629                                                  struct brw_reg offset);
 630    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 631                                             struct brw_reg index,
 632                                             struct brw_reg offset);
 633    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 634                                                  struct brw_reg dst,
 635                                                  struct brw_reg index,
 636                                                  struct brw_reg offset);
 637    void generate_mov_dispatch_to_flags(fs_inst *inst);
 638
 639    void generate_set_omask(fs_inst *inst,
 640                            struct brw_reg dst,
 641                            struct brw_reg sample_mask);
 642
 643    void generate_set_sample_id(fs_inst *inst,
 644                                struct brw_reg dst,
 645                                struct brw_reg src0,
 646                                struct brw_reg src1);
 647
 648    void generate_set_simd4x2_offset(fs_inst *inst,
 649                                     struct brw_reg dst,
 650                                     struct brw_reg offset);
 651    void generate_discard_jump(fs_inst *inst);
 652
 653    void generate_pack_half_2x16_split(fs_inst *inst,
 654                                       struct brw_reg dst,
 655                                       struct brw_reg x,
 656                                       struct brw_reg y);
 657    void generate_unpack_half_2x16_split(fs_inst *inst,
 658                                         struct brw_reg dst,
 659                                         struct brw_reg src);
 660
 661    void generate_shader_time_add(fs_inst *inst,
 662                                  struct brw_reg payload,
 663                                  struct brw_reg offset,
 664                                  struct brw_reg value);
 665
 666    void generate_untyped_atomic(fs_inst *inst,
 667                                 struct brw_reg dst,
 668                                 struct brw_reg atomic_op,
 669                                 struct brw_reg surf_index);
 670
 671    void generate_untyped_surface_read(fs_inst *inst,
 672                                       struct brw_reg dst,
 673                                       struct brw_reg surf_index);
 674
 675    void patch_discard_jumps_to_fb_writes();
 676
 677    struct brw_context *brw;
 678    struct gl_context *ctx;
 679
 680    struct brw_compile *p;
 681    struct brw_wm_compile *c;
 682
 683    struct gl_shader_program *prog;
 684    const struct gl_fragment_program *fp;
 685
 686    unsigned dispatch_width; /**< 8 or 16 */
 687
 688    exec_list discard_halt_patches;
 689    bool dual_source_output;
 690    void *mem_ctx;
 691 };
 692
 693 /**
 694  * The fragment shader code generator.
 695  *
 696  * Translates FS IR to actual i965 assembly code.
 697  */
 698 class gen8_fs_generator : public gen8_generator
 699 {
 700 public:
 701    gen8_fs_generator(struct brw_context *brw,
 702                      struct brw_wm_compile *c,
 703                      struct gl_shader_program *prog,
 704                      struct gl_fragment_program *fp,
 705                      bool dual_source_output);
 706    ~gen8_fs_generator();
 707
 708    const unsigned *generate_assembly(exec_list *simd8_instructions,
 709                                      exec_list *simd16_instructions,
 710                                      unsigned *assembly_size);
 711
 712 private:
 713    void generate_code(exec_list *instructions);
 714    void generate_fb_write(fs_inst *inst);
 715    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 716                          struct brw_reg *src);
 717    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 718    void generate_math1(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 719    void generate_math2(fs_inst *inst, struct brw_reg dst,
 720                        struct brw_reg src0, struct brw_reg src1);
 721    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 722    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 723                      bool negate_value);
 724    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 725    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 726    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 727    void generate_uniform_pull_constant_load(fs_inst *inst,
 728                                             struct brw_reg dst,
 729                                             struct brw_reg index,
 730                                             struct brw_reg offset);
 731    void generate_varying_pull_constant_load(fs_inst *inst,
 732                                             struct brw_reg dst,
 733                                             struct brw_reg index,
 734                                             struct brw_reg offset);
 735    void generate_mov_dispatch_to_flags(fs_inst *ir);
 736    void generate_set_omask(fs_inst *ir,
 737                            struct brw_reg dst,
 738                            struct brw_reg sample_mask);
 739    void generate_set_sample_id(fs_inst *ir,
 740                                struct brw_reg dst,
 741                                struct brw_reg src0,
 742                                struct brw_reg src1);
 743    void generate_set_simd4x2_offset(fs_inst *ir,
 744                                     struct brw_reg dst,
 745                                     struct brw_reg offset);
 746    void generate_pack_half_2x16_split(fs_inst *inst,
 747                                       struct brw_reg dst,
 748                                       struct brw_reg x,
 749                                       struct brw_reg y);
 750    void generate_unpack_half_2x16_split(fs_inst *inst,
 751                                         struct brw_reg dst,
 752                                         struct brw_reg src);
 753    void generate_discard_jump(fs_inst *ir);
 754
 755    void patch_discard_jumps_to_fb_writes();
 756
 757    struct brw_wm_compile *c;
 758    const struct gl_fragment_program *fp;
 759
 760    unsigned dispatch_width; /** 8 or 16 */
 761
 762    bool dual_source_output;
 763
 764    exec_list discard_halt_patches;
 765 };
 766
 767 bool brw_do_channel_expressions(struct exec_list *instructions);
 768 bool brw_do_vector_splitting(struct exec_list *instructions);
 769 bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);
 770
 771 struct brw_reg brw_reg_from_fs_reg(fs_reg *reg);