src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31
  32 extern "C" {
  33
  34 #include <sys/types.h>
  35
  36 #include "main/macros.h"
  37 #include "main/shaderobj.h"
  38 #include "main/uniforms.h"
  39 #include "program/prog_parameter.h"
  40 #include "program/prog_print.h"
  41 #include "program/prog_optimize.h"
  42 #include "program/register_allocate.h"
  43 #include "program/sampler.h"
  44 #include "program/hash_table.h"
  45 #include "brw_context.h"
  46 #include "brw_eu.h"
  47 #include "brw_wm.h"
  48 #include "brw_shader.h"
  49 }
  50 #include "gen8_generator.h"
  51 #include "glsl/glsl_types.h"
  52 #include "glsl/ir.h"
  53
  54 #define MAX_SAMPLER_MESSAGE_SIZE 11
  55
  56 class bblock_t;
  57 namespace {
  58    struct acp_entry;
  59 }
  60
  61 namespace brw {
  62    class fs_live_variables;
  63 }
  64
  65 class fs_reg {
  66 public:
  67    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  68
  69    void init();
  70
  71    fs_reg();
  72    fs_reg(float f);
  73    fs_reg(int32_t i);
  74    fs_reg(uint32_t u);
  75    fs_reg(struct brw_reg fixed_hw_reg);
  76    fs_reg(enum register_file file, int reg);
  77    fs_reg(enum register_file file, int reg, uint32_t type);
  78    fs_reg(class fs_visitor *v, const struct glsl_type *type);
  79
  80    bool equals(const fs_reg &r) const;
  81    bool is_zero() const;
  82    bool is_one() const;
  83    bool is_null() const;
  84    bool is_valid_3src() const;
  85    bool is_contiguous() const;
  86
  87    fs_reg &apply_stride(unsigned stride);
  88
  89    /** Register file: GRF, MRF, IMM. */
  90    enum register_file file;
  91    /**
  92     * Register number.  For MRF, it's the hardware register.  For
  93     * GRF, it's a virtual register number until register allocation
  94     */
  95    int reg;
  96    /**
  97     * Offset from the start of the contiguous register block.
  98     *
  99     * For pre-register-allocation GRFs, this is in units of a float per pixel
 100     * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
 101     * For uniforms, this is in units of 1 float.
 102     */
 103    int reg_offset;
 104    /** Register type.  BRW_REGISTER_TYPE_* */
 105    int type;
 106    bool negate;
 107    bool abs;
 108    struct brw_reg fixed_hw_reg;
 109
 110    /** Smear a channel of the reg to all channels. */
 111    fs_reg &set_smear(unsigned subreg);
 112
 113    /** Value for file == IMM */
 114    union {
 115       int32_t i;
 116       uint32_t u;
 117       float f;
 118    } imm;
 119
 120    /**
 121     * Offset in bytes from the start of the register.  Values up to a
 122     * backend_reg::reg_offset unit are valid.
 123     */
 124    int subreg_offset;
 125
 126    /** Register region horizontal stride */
 127    int stride;
 128
 129    fs_reg *reladdr;
 130 };
 131
 132 static inline fs_reg
 133 retype(fs_reg reg, unsigned type)
 134 {
 135    reg.fixed_hw_reg.type = reg.type = type;
 136    return reg;
 137 }
 138
 139 static inline fs_reg
 140 offset(fs_reg reg, unsigned delta)
 141 {
 142    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 143    reg.reg_offset += delta;
 144    return reg;
 145 }
 146
 147 static inline fs_reg
 148 byte_offset(fs_reg reg, unsigned delta)
 149 {
 150    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 151    reg.subreg_offset += delta;
 152    return reg;
 153 }
 154
 155 /**
 156  * Get either of the 8-component halves of a 16-component register.
 157  *
 158  * Note: this also works if \c reg represents a SIMD16 pair of registers.
 159  */
 160 static inline fs_reg
 161 half(const fs_reg &reg, unsigned idx)
 162 {
 163    assert(idx < 2);
 164    assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
 165    return byte_offset(reg, 8 * idx * reg.stride * type_sz(reg.type));
 166 }
 167
 168 static const fs_reg reg_undef;
 169 static const fs_reg reg_null_f(retype(brw_null_reg(), BRW_REGISTER_TYPE_F));
 170 static const fs_reg reg_null_d(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 171 static const fs_reg reg_null_ud(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 172
 173 class ip_record : public exec_node {
 174 public:
 175    DECLARE_RALLOC_CXX_OPERATORS(ip_record)
 176
 177    ip_record(int ip)
 178    {
 179       this->ip = ip;
 180    }
 181
 182    int ip;
 183 };
 184
 185 class fs_inst : public backend_instruction {
 186 public:
 187    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 188
 189    void init();
 190
 191    fs_inst();
 192    fs_inst(enum opcode opcode);
 193    fs_inst(enum opcode opcode, fs_reg dst);
 194    fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0);
 195    fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
 196    fs_inst(enum opcode opcode, fs_reg dst,
 197            fs_reg src0, fs_reg src1,fs_reg src2);
 198
 199    bool equals(fs_inst *inst);
 200    bool overwrites_reg(const fs_reg &reg);
 201    bool is_send_from_grf();
 202    bool is_partial_write();
 203    int regs_read(fs_visitor *v, int arg);
 204
 205    bool reads_flag();
 206    bool writes_flag();
 207
 208    fs_reg dst;
 209    fs_reg src[3];
 210    bool saturate;
 211    int conditional_mod; /**< BRW_CONDITIONAL_* */
 212
 213    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 214     * mod and predication.
 215     */
 216    uint8_t flag_subreg;
 217
 218    int mlen; /**< SEND message length */
 219    int regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
 220    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 221    uint32_t texture_offset; /**< Texture offset bitfield */
 222    int sampler;
 223    int target; /**< MRT target. */
 224    bool eot;
 225    bool header_present;
 226    bool shadow_compare;
 227    bool force_uncompressed;
 228    bool force_sechalf;
 229    bool force_writemask_all;
 230    uint32_t offset; /* spill/unspill offset */
 231
 232    /** @{
 233     * Annotation for the generated IR.  One of the two can be set.
 234     */
 235    const void *ir;
 236    const char *annotation;
 237    /** @} */
 238 };
 239
 240 /**
 241  * The fragment shader front-end.
 242  *
 243  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
 244  */
 245 class fs_visitor : public backend_visitor
 246 {
 247 public:
 248
 249    fs_visitor(struct brw_context *brw,
 250               struct brw_wm_compile *c,
 251               struct gl_shader_program *shader_prog,
 252               struct gl_fragment_program *fp,
 253               unsigned dispatch_width);
 254    ~fs_visitor();
 255
 256    fs_reg *variable_storage(ir_variable *var);
 257    int virtual_grf_alloc(int size);
 258    void import_uniforms(fs_visitor *v);
 259
 260    void visit(ir_variable *ir);
 261    void visit(ir_assignment *ir);
 262    void visit(ir_dereference_variable *ir);
 263    void visit(ir_dereference_record *ir);
 264    void visit(ir_dereference_array *ir);
 265    void visit(ir_expression *ir);
 266    void visit(ir_texture *ir);
 267    void visit(ir_if *ir);
 268    void visit(ir_constant *ir);
 269    void visit(ir_swizzle *ir);
 270    void visit(ir_return *ir);
 271    void visit(ir_loop *ir);
 272    void visit(ir_loop_jump *ir);
 273    void visit(ir_discard *ir);
 274    void visit(ir_call *ir);
 275    void visit(ir_function *ir);
 276    void visit(ir_function_signature *ir);
 277    void visit(ir_emit_vertex *);
 278    void visit(ir_end_primitive *);
 279
 280    uint32_t gather_channel(ir_texture *ir, int sampler);
 281    void swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler);
 282
 283    bool can_do_source_mods(fs_inst *inst);
 284
 285    fs_inst *emit(fs_inst inst);
 286    fs_inst *emit(fs_inst *inst);
 287    void emit(exec_list list);
 288
 289    fs_inst *emit(enum opcode opcode);
 290    fs_inst *emit(enum opcode opcode, fs_reg dst);
 291    fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0);
 292    fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
 293    fs_inst *emit(enum opcode opcode, fs_reg dst,
 294                  fs_reg src0, fs_reg src1, fs_reg src2);
 295
 296    fs_inst *MOV(fs_reg dst, fs_reg src);
 297    fs_inst *NOT(fs_reg dst, fs_reg src);
 298    fs_inst *RNDD(fs_reg dst, fs_reg src);
 299    fs_inst *RNDE(fs_reg dst, fs_reg src);
 300    fs_inst *RNDZ(fs_reg dst, fs_reg src);
 301    fs_inst *FRC(fs_reg dst, fs_reg src);
 302    fs_inst *ADD(fs_reg dst, fs_reg src0, fs_reg src1);
 303    fs_inst *MUL(fs_reg dst, fs_reg src0, fs_reg src1);
 304    fs_inst *MACH(fs_reg dst, fs_reg src0, fs_reg src1);
 305    fs_inst *MAC(fs_reg dst, fs_reg src0, fs_reg src1);
 306    fs_inst *SHL(fs_reg dst, fs_reg src0, fs_reg src1);
 307    fs_inst *SHR(fs_reg dst, fs_reg src0, fs_reg src1);
 308    fs_inst *ASR(fs_reg dst, fs_reg src0, fs_reg src1);
 309    fs_inst *AND(fs_reg dst, fs_reg src0, fs_reg src1);
 310    fs_inst *OR(fs_reg dst, fs_reg src0, fs_reg src1);
 311    fs_inst *XOR(fs_reg dst, fs_reg src0, fs_reg src1);
 312    fs_inst *IF(uint32_t predicate);
 313    fs_inst *IF(fs_reg src0, fs_reg src1, uint32_t condition);
 314    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 315                 uint32_t condition);
 316    fs_inst *LRP(fs_reg dst, fs_reg a, fs_reg y, fs_reg x);
 317    fs_inst *DEP_RESOLVE_MOV(int grf);
 318    fs_inst *BFREV(fs_reg dst, fs_reg value);
 319    fs_inst *BFE(fs_reg dst, fs_reg bits, fs_reg offset, fs_reg value);
 320    fs_inst *BFI1(fs_reg dst, fs_reg bits, fs_reg offset);
 321    fs_inst *BFI2(fs_reg dst, fs_reg bfi1_dst, fs_reg insert, fs_reg base);
 322    fs_inst *FBH(fs_reg dst, fs_reg value);
 323    fs_inst *FBL(fs_reg dst, fs_reg value);
 324    fs_inst *CBIT(fs_reg dst, fs_reg value);
 325    fs_inst *MAD(fs_reg dst, fs_reg c, fs_reg b, fs_reg a);
 326    fs_inst *ADDC(fs_reg dst, fs_reg src0, fs_reg src1);
 327    fs_inst *SUBB(fs_reg dst, fs_reg src0, fs_reg src1);
 328    fs_inst *SEL(fs_reg dst, fs_reg src0, fs_reg src1);
 329
 330    int type_size(const struct glsl_type *type);
 331    fs_inst *get_instruction_generating_reg(fs_inst *start,
 332                                            fs_inst *end,
 333                                            fs_reg reg);
 334
 335    exec_list VARYING_PULL_CONSTANT_LOAD(fs_reg dst, fs_reg surf_index,
 336                                         fs_reg varying_offset,
 337                                         uint32_t const_offset);
 338
 339    bool run();
 340    void assign_binding_table_offsets();
 341    void setup_payload_gen4();
 342    void setup_payload_gen6();
 343    void assign_curb_setup();
 344    void calculate_urb_setup();
 345    void assign_urb_setup();
 346    bool assign_regs(bool allow_spilling);
 347    void assign_regs_trivial();
 348    void get_used_mrfs(bool *mrf_used);
 349    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 350                                    int first_payload_node);
 351    void setup_mrf_hack_interference(struct ra_graph *g,
 352                                     int first_mrf_hack_node);
 353    int choose_spill_reg(struct ra_graph *g);
 354    void spill_reg(int spill_reg);
 355    void split_virtual_grfs();
 356    void compact_virtual_grfs();
 357    void move_uniform_array_access_to_pull_constants();
 358    void setup_pull_constants();
 359    void invalidate_live_intervals();
 360    void calculate_live_intervals();
 361    void calculate_register_pressure();
 362    bool opt_algebraic();
 363    bool opt_cse();
 364    bool opt_cse_local(bblock_t *block, exec_list *aeb);
 365    bool opt_copy_propagate();
 366    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 367    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 368    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 369                                  exec_list *acp);
 370    bool register_coalesce();
 371    bool compute_to_mrf();
 372    bool dead_code_eliminate();
 373    bool dead_code_eliminate_local();
 374    bool remove_dead_constants();
 375    bool remove_duplicate_mrf_writes();
 376    bool virtual_grf_interferes(int a, int b);
 377    void schedule_instructions(instruction_scheduler_mode mode);
 378    void insert_gen4_send_dependency_workarounds();
 379    void insert_gen4_pre_send_dependency_workarounds(fs_inst *inst);
 380    void insert_gen4_post_send_dependency_workarounds(fs_inst *inst);
 381    void fail(const char *msg, ...);
 382    void lower_uniform_pull_constant_loads();
 383
 384    void push_force_uncompressed();
 385    void pop_force_uncompressed();
 386
 387    void emit_dummy_fs();
 388    fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
 389    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 390                          glsl_interp_qualifier interpolation_mode,
 391                          bool is_centroid, bool is_sample);
 392    fs_reg *emit_frontfacing_interpolation(ir_variable *ir);
 393    fs_reg *emit_samplepos_setup(ir_variable *ir);
 394    fs_reg *emit_sampleid_setup(ir_variable *ir);
 395    fs_reg *emit_samplemaskin_setup(ir_variable *ir);
 396    fs_reg *emit_general_interpolation(ir_variable *ir);
 397    void emit_interpolation_setup_gen4();
 398    void emit_interpolation_setup_gen6();
 399    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
 400    fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
 401                            bool is_rect, int sampler, int texunit);
 402    fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 403                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2);
 404    fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 405                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 406                               fs_reg sample_index);
 407    fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 408                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 409                               fs_reg sample_index, fs_reg mcs, int sampler);
 410    fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, int sampler);
 411    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
 412    fs_reg fix_math_operand(fs_reg src);
 413    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 414    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 415    void emit_lrp(fs_reg dst, fs_reg x, fs_reg y, fs_reg a);
 416    void emit_minmax(uint32_t conditionalmod, fs_reg dst,
 417                     fs_reg src0, fs_reg src1);
 418    bool try_emit_saturate(ir_expression *ir);
 419    bool try_emit_mad(ir_expression *ir, int mul_arg);
 420    void try_replace_with_sel();
 421    bool opt_peephole_sel();
 422    bool opt_peephole_predicated_break();
 423    bool opt_saturate_propagation();
 424    void emit_bool_to_cond_code(ir_rvalue *condition);
 425    void emit_if_gen6(ir_if *ir);
 426    void emit_unspill(fs_inst *inst, fs_reg reg, uint32_t spill_offset,
 427                      int count);
 428
 429    void emit_fragment_program_code();
 430    void setup_fp_regs();
 431    fs_reg get_fp_src_reg(const prog_src_register *src);
 432    fs_reg get_fp_dst_reg(const prog_dst_register *dst);
 433    void emit_fp_alu1(enum opcode opcode,
 434                      const struct prog_instruction *fpi,
 435                      fs_reg dst, fs_reg src);
 436    void emit_fp_alu2(enum opcode opcode,
 437                      const struct prog_instruction *fpi,
 438                      fs_reg dst, fs_reg src0, fs_reg src1);
 439    void emit_fp_scalar_write(const struct prog_instruction *fpi,
 440                              fs_reg dst, fs_reg src);
 441    void emit_fp_scalar_math(enum opcode opcode,
 442                             const struct prog_instruction *fpi,
 443                             fs_reg dst, fs_reg src);
 444
 445    void emit_fp_minmax(const struct prog_instruction *fpi,
 446                        fs_reg dst, fs_reg src0, fs_reg src1);
 447
 448    void emit_fp_sop(uint32_t conditional_mod,
 449                     const struct prog_instruction *fpi,
 450                     fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
 451
 452    void emit_color_write(int target, int index, int first_color_mrf);
 453    void emit_alpha_test();
 454    void emit_fb_writes();
 455
 456    void emit_shader_time_begin();
 457    void emit_shader_time_end();
 458    void emit_shader_time_write(enum shader_time_shader_type type,
 459                                fs_reg value);
 460
 461    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 462                             fs_reg dst, fs_reg offset, fs_reg src0,
 463                             fs_reg src1);
 464
 465    void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
 466                                   fs_reg offset);
 467
 468    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 469                                fs_reg dst,
 470                                fs_reg src,
 471                                fs_inst *pre_rhs_inst,
 472                                fs_inst *last_rhs_inst);
 473    void emit_assignment_writes(fs_reg &l, fs_reg &r,
 474                                const glsl_type *type, bool predicated);
 475    void resolve_ud_negate(fs_reg *reg);
 476    void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
 477
 478    fs_reg get_timestamp();
 479
 480    struct brw_reg interp_reg(int location, int channel);
 481    void setup_uniform_values(ir_variable *ir);
 482    void setup_builtin_uniform_values(ir_variable *ir);
 483    int implied_mrf_writes(fs_inst *inst);
 484
 485    virtual void dump_instructions();
 486    void dump_instruction(backend_instruction *inst);
 487
 488    void visit_atomic_counter_intrinsic(ir_call *ir);
 489
 490    struct gl_fragment_program *fp;
 491    struct brw_wm_compile *c;
 492    unsigned int sanity_param_count;
 493
 494    int param_size[MAX_UNIFORMS * 4];
 495
 496    int *virtual_grf_sizes;
 497    int virtual_grf_count;
 498    int virtual_grf_array_size;
 499    int *virtual_grf_start;
 500    int *virtual_grf_end;
 501    brw::fs_live_variables *live_intervals;
 502
 503    int *regs_live_at_ip;
 504
 505    /* This is the map from UNIFORM hw_reg + reg_offset as generated by
 506     * the visitor to the packed uniform number after
 507     * remove_dead_constants() that represents the actual uploaded
 508     * uniform index.
 509     */
 510    int *params_remap;
 511    int nr_params_remap;
 512
 513    struct hash_table *variable_ht;
 514    fs_reg frag_depth;
 515    fs_reg sample_mask;
 516    fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
 517    unsigned output_components[BRW_MAX_DRAW_BUFFERS];
 518    fs_reg dual_src_output;
 519    int first_non_payload_grf;
 520    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 521    int max_grf;
 522
 523    fs_reg *fp_temp_regs;
 524    fs_reg *fp_input_regs;
 525
 526    /** @{ debug annotation info */
 527    const char *current_annotation;
 528    const void *base_ir;
 529    /** @} */
 530
 531    bool failed;
 532    char *fail_msg;
 533
 534    /* Result of last visit() method. */
 535    fs_reg result;
 536
 537    fs_reg pixel_x;
 538    fs_reg pixel_y;
 539    fs_reg wpos_w;
 540    fs_reg pixel_w;
 541    fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 542    fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 543    fs_reg shader_start_time;
 544
 545    int grf_used;
 546    bool spilled_any_registers;
 547
 548    const unsigned dispatch_width; /**< 8 or 16 */
 549
 550    int force_uncompressed_stack;
 551 };
 552
 553 /**
 554  * The fragment shader code generator.
 555  *
 556  * Translates FS IR to actual i965 assembly code.
 557  */
 558 class fs_generator
 559 {
 560 public:
 561    fs_generator(struct brw_context *brw,
 562                 struct brw_wm_compile *c,
 563                 struct gl_shader_program *prog,
 564                 struct gl_fragment_program *fp,
 565                 bool dual_source_output);
 566    ~fs_generator();
 567
 568    const unsigned *generate_assembly(exec_list *simd8_instructions,
 569                                      exec_list *simd16_instructions,
 570                                      unsigned *assembly_size,
 571                                      FILE *dump_file = NULL);
 572
 573 private:
 574    void generate_code(exec_list *instructions, FILE *dump_file);
 575    void generate_fb_write(fs_inst *inst);
 576    void generate_blorp_fb_write(fs_inst *inst);
 577    void generate_pixel_xy(struct brw_reg dst, bool is_x);
 578    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 579                          struct brw_reg *src);
 580    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 581    void generate_math1_gen7(fs_inst *inst,
 582                             struct brw_reg dst,
 583                             struct brw_reg src);
 584    void generate_math2_gen7(fs_inst *inst,
 585                             struct brw_reg dst,
 586                             struct brw_reg src0,
 587                             struct brw_reg src1);
 588    void generate_math1_gen6(fs_inst *inst,
 589                             struct brw_reg dst,
 590                             struct brw_reg src);
 591    void generate_math2_gen6(fs_inst *inst,
 592                             struct brw_reg dst,
 593                             struct brw_reg src0,
 594                             struct brw_reg src1);
 595    void generate_math_gen4(fs_inst *inst,
 596                            struct brw_reg dst,
 597                            struct brw_reg src);
 598    void generate_math_g45(fs_inst *inst,
 599                           struct brw_reg dst,
 600                           struct brw_reg src);
 601    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 602    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 603                      bool negate_value);
 604    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 605    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 606    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 607    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 608                                             struct brw_reg index,
 609                                             struct brw_reg offset);
 610    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 611                                                  struct brw_reg dst,
 612                                                  struct brw_reg surf_index,
 613                                                  struct brw_reg offset);
 614    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 615                                             struct brw_reg index,
 616                                             struct brw_reg offset);
 617    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 618                                                  struct brw_reg dst,
 619                                                  struct brw_reg index,
 620                                                  struct brw_reg offset);
 621    void generate_mov_dispatch_to_flags(fs_inst *inst);
 622
 623    void generate_set_omask(fs_inst *inst,
 624                            struct brw_reg dst,
 625                            struct brw_reg sample_mask);
 626
 627    void generate_set_sample_id(fs_inst *inst,
 628                                struct brw_reg dst,
 629                                struct brw_reg src0,
 630                                struct brw_reg src1);
 631
 632    void generate_set_simd4x2_offset(fs_inst *inst,
 633                                     struct brw_reg dst,
 634                                     struct brw_reg offset);
 635    void generate_discard_jump(fs_inst *inst);
 636
 637    void generate_pack_half_2x16_split(fs_inst *inst,
 638                                       struct brw_reg dst,
 639                                       struct brw_reg x,
 640                                       struct brw_reg y);
 641    void generate_unpack_half_2x16_split(fs_inst *inst,
 642                                         struct brw_reg dst,
 643                                         struct brw_reg src);
 644
 645    void generate_shader_time_add(fs_inst *inst,
 646                                  struct brw_reg payload,
 647                                  struct brw_reg offset,
 648                                  struct brw_reg value);
 649
 650    void generate_untyped_atomic(fs_inst *inst,
 651                                 struct brw_reg dst,
 652                                 struct brw_reg atomic_op,
 653                                 struct brw_reg surf_index);
 654
 655    void generate_untyped_surface_read(fs_inst *inst,
 656                                       struct brw_reg dst,
 657                                       struct brw_reg surf_index);
 658
 659    void patch_discard_jumps_to_fb_writes();
 660
 661    struct brw_context *brw;
 662    struct gl_context *ctx;
 663
 664    struct brw_compile *p;
 665    struct brw_wm_compile *c;
 666
 667    struct gl_shader_program *prog;
 668    const struct gl_fragment_program *fp;
 669
 670    unsigned dispatch_width; /**< 8 or 16 */
 671
 672    exec_list discard_halt_patches;
 673    bool dual_source_output;
 674    void *mem_ctx;
 675 };
 676
 677 /**
 678  * The fragment shader code generator.
 679  *
 680  * Translates FS IR to actual i965 assembly code.
 681  */
 682 class gen8_fs_generator : public gen8_generator
 683 {
 684 public:
 685    gen8_fs_generator(struct brw_context *brw,
 686                      struct brw_wm_compile *c,
 687                      struct gl_shader_program *prog,
 688                      struct gl_fragment_program *fp,
 689                      bool dual_source_output);
 690    ~gen8_fs_generator();
 691
 692    const unsigned *generate_assembly(exec_list *simd8_instructions,
 693                                      exec_list *simd16_instructions,
 694                                      unsigned *assembly_size);
 695
 696 private:
 697    void generate_code(exec_list *instructions);
 698    void generate_fb_write(fs_inst *inst);
 699    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 700                          struct brw_reg *src);
 701    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 702    void generate_math1(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 703    void generate_math2(fs_inst *inst, struct brw_reg dst,
 704                        struct brw_reg src0, struct brw_reg src1);
 705    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 706    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 707                      bool negate_value);
 708    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 709    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 710    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 711    void generate_uniform_pull_constant_load(fs_inst *inst,
 712                                             struct brw_reg dst,
 713                                             struct brw_reg index,
 714                                             struct brw_reg offset);
 715    void generate_varying_pull_constant_load(fs_inst *inst,
 716                                             struct brw_reg dst,
 717                                             struct brw_reg index,
 718                                             struct brw_reg offset);
 719    void generate_mov_dispatch_to_flags(fs_inst *ir);
 720    void generate_set_simd4x2_offset(fs_inst *ir,
 721                                     struct brw_reg dst,
 722                                     struct brw_reg offset);
 723    void generate_discard_jump(fs_inst *ir);
 724
 725    void patch_discard_jumps_to_fb_writes();
 726
 727    void mark_surface_used(unsigned surf_index);
 728
 729    struct brw_wm_compile *c;
 730    const struct gl_fragment_program *fp;
 731
 732    unsigned dispatch_width; /** 8 or 16 */
 733
 734    bool dual_source_output;
 735
 736    exec_list discard_halt_patches;
 737 };
 738
 739 bool brw_do_channel_expressions(struct exec_list *instructions);
 740 bool brw_do_vector_splitting(struct exec_list *instructions);
 741 bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);
 742
 743 struct brw_reg brw_reg_from_fs_reg(fs_reg *reg);