2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include "brw_shader.h"
34 #include <sys/types.h>
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/uniforms.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/prog_optimize.h"
42 #include "util/register_allocate.h"
43 #include "program/sampler.h"
44 #include "program/hash_table.h"
45 #include "brw_context.h"
48 #include "brw_shader.h"
49 #include "intel_asm_annotation.h"
51 #include "glsl/glsl_types.h"
54 #define MAX_SAMPLER_MESSAGE_SIZE 11
62 class fs_live_variables
;
65 class fs_reg
: public backend_reg
{
67 DECLARE_RALLOC_CXX_OPERATORS(fs_reg
)
75 fs_reg(struct brw_reg fixed_hw_reg
);
76 fs_reg(enum register_file file
, int reg
);
77 fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
);
78 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
80 bool equals(const fs_reg
&r
) const;
81 bool is_valid_3src() const;
82 bool is_contiguous() const;
84 fs_reg
&apply_stride(unsigned stride
);
85 /** Smear a channel of the reg to all channels. */
86 fs_reg
&set_smear(unsigned subreg
);
89 * Offset in bytes from the start of the register. Values up to a
90 * backend_reg::reg_offset unit are valid.
96 /** Register region horizontal stride */
101 retype(fs_reg reg
, enum brw_reg_type type
)
103 reg
.fixed_hw_reg
.type
= reg
.type
= type
;
108 offset(fs_reg reg
, unsigned delta
)
110 assert(delta
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
111 reg
.reg_offset
+= delta
;
116 byte_offset(fs_reg reg
, unsigned delta
)
118 assert(delta
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
119 reg
.subreg_offset
+= delta
;
124 * Get either of the 8-component halves of a 16-component register.
126 * Note: this also works if \c reg represents a SIMD16 pair of registers.
129 half(const fs_reg
®
, unsigned idx
)
132 assert(idx
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
133 return byte_offset(reg
, 8 * idx
* reg
.stride
* type_sz(reg
.type
));
136 static const fs_reg reg_undef
;
137 static const fs_reg
reg_null_f(retype(brw_null_reg(), BRW_REGISTER_TYPE_F
));
138 static const fs_reg
reg_null_d(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
139 static const fs_reg
reg_null_ud(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
141 class ip_record
: public exec_node
{
143 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
153 class fs_inst
: public backend_instruction
{
154 fs_inst
&operator=(const fs_inst
&);
157 DECLARE_RALLOC_CXX_OPERATORS(fs_inst
)
159 void init(enum opcode opcode
, const fs_reg
&dst
, fs_reg
*src
, int sources
);
161 fs_inst(enum opcode opcode
= BRW_OPCODE_NOP
, const fs_reg
&dst
= reg_undef
);
162 fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
);
163 fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
165 fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
166 const fs_reg
&src1
, const fs_reg
&src2
);
167 fs_inst(enum opcode opcode
, const fs_reg
&dst
, fs_reg src
[], int sources
);
168 fs_inst(const fs_inst
&that
);
170 void resize_sources(uint8_t num_sources
);
172 bool equals(fs_inst
*inst
) const;
173 bool overwrites_reg(const fs_reg
®
) const;
174 bool is_send_from_grf() const;
175 bool is_partial_write() const;
176 int regs_read(fs_visitor
*v
, int arg
) const;
177 bool can_do_source_mods(struct brw_context
*brw
);
179 bool reads_flag() const;
180 bool writes_flag() const;
185 uint8_t sources
; /**< Number of fs_reg sources. */
187 /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
188 * mod and predication.
192 uint8_t regs_written
; /**< Number of vgrfs written by a SEND message, or 1 */
194 bool header_present
:1;
195 bool shadow_compare
:1;
196 bool force_uncompressed
:1;
197 bool force_sechalf
:1;
198 bool pi_noperspective
:1; /**< Pixel interpolator noperspective flag */
202 * The fragment shader front-end.
204 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
206 class fs_visitor
: public backend_visitor
210 fs_visitor(struct brw_context
*brw
,
212 const struct brw_wm_prog_key
*key
,
213 struct brw_wm_prog_data
*prog_data
,
214 struct gl_shader_program
*shader_prog
,
215 struct gl_fragment_program
*fp
,
216 unsigned dispatch_width
);
220 fs_reg
*variable_storage(ir_variable
*var
);
221 int virtual_grf_alloc(int size
);
222 void import_uniforms(fs_visitor
*v
);
224 void visit(ir_variable
*ir
);
225 void visit(ir_assignment
*ir
);
226 void visit(ir_dereference_variable
*ir
);
227 void visit(ir_dereference_record
*ir
);
228 void visit(ir_dereference_array
*ir
);
229 void visit(ir_expression
*ir
);
230 void visit(ir_texture
*ir
);
231 void visit(ir_if
*ir
);
232 void visit(ir_constant
*ir
);
233 void visit(ir_swizzle
*ir
);
234 void visit(ir_return
*ir
);
235 void visit(ir_loop
*ir
);
236 void visit(ir_loop_jump
*ir
);
237 void visit(ir_discard
*ir
);
238 void visit(ir_call
*ir
);
239 void visit(ir_function
*ir
);
240 void visit(ir_function_signature
*ir
);
241 void visit(ir_emit_vertex
*);
242 void visit(ir_end_primitive
*);
244 uint32_t gather_channel(ir_texture
*ir
, uint32_t sampler
);
245 void swizzle_result(ir_texture
*ir
, fs_reg orig_val
, uint32_t sampler
);
247 fs_inst
*emit(fs_inst
*inst
);
248 void emit(exec_list list
);
250 fs_inst
*emit(enum opcode opcode
);
251 fs_inst
*emit(enum opcode opcode
, const fs_reg
&dst
);
252 fs_inst
*emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
);
253 fs_inst
*emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
255 fs_inst
*emit(enum opcode opcode
, const fs_reg
&dst
,
256 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
);
257 fs_inst
*emit(enum opcode opcode
, const fs_reg
&dst
,
258 fs_reg src
[], int sources
);
260 fs_inst
*MOV(const fs_reg
&dst
, const fs_reg
&src
);
261 fs_inst
*NOT(const fs_reg
&dst
, const fs_reg
&src
);
262 fs_inst
*RNDD(const fs_reg
&dst
, const fs_reg
&src
);
263 fs_inst
*RNDE(const fs_reg
&dst
, const fs_reg
&src
);
264 fs_inst
*RNDZ(const fs_reg
&dst
, const fs_reg
&src
);
265 fs_inst
*FRC(const fs_reg
&dst
, const fs_reg
&src
);
266 fs_inst
*ADD(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
267 fs_inst
*MUL(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
268 fs_inst
*MACH(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
269 fs_inst
*MAC(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
270 fs_inst
*SHL(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
271 fs_inst
*SHR(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
272 fs_inst
*ASR(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
273 fs_inst
*AND(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
274 fs_inst
*OR(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
275 fs_inst
*XOR(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
276 fs_inst
*IF(enum brw_predicate predicate
);
277 fs_inst
*IF(const fs_reg
&src0
, const fs_reg
&src1
,
278 enum brw_conditional_mod condition
);
279 fs_inst
*CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
,
280 enum brw_conditional_mod condition
);
281 fs_inst
*LRP(const fs_reg
&dst
, const fs_reg
&a
, const fs_reg
&y
,
283 fs_inst
*DEP_RESOLVE_MOV(int grf
);
284 fs_inst
*BFREV(const fs_reg
&dst
, const fs_reg
&value
);
285 fs_inst
*BFE(const fs_reg
&dst
, const fs_reg
&bits
, const fs_reg
&offset
,
286 const fs_reg
&value
);
287 fs_inst
*BFI1(const fs_reg
&dst
, const fs_reg
&bits
, const fs_reg
&offset
);
288 fs_inst
*BFI2(const fs_reg
&dst
, const fs_reg
&bfi1_dst
,
289 const fs_reg
&insert
, const fs_reg
&base
);
290 fs_inst
*FBH(const fs_reg
&dst
, const fs_reg
&value
);
291 fs_inst
*FBL(const fs_reg
&dst
, const fs_reg
&value
);
292 fs_inst
*CBIT(const fs_reg
&dst
, const fs_reg
&value
);
293 fs_inst
*MAD(const fs_reg
&dst
, const fs_reg
&c
, const fs_reg
&b
,
295 fs_inst
*ADDC(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
296 fs_inst
*SUBB(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
297 fs_inst
*SEL(const fs_reg
&dst
, const fs_reg
&src0
, const fs_reg
&src1
);
299 int type_size(const struct glsl_type
*type
);
300 fs_inst
*get_instruction_generating_reg(fs_inst
*start
,
304 fs_inst
*LOAD_PAYLOAD(const fs_reg
&dst
, fs_reg
*src
, int sources
);
306 exec_list
VARYING_PULL_CONSTANT_LOAD(const fs_reg
&dst
,
307 const fs_reg
&surf_index
,
308 const fs_reg
&varying_offset
,
309 uint32_t const_offset
);
312 void assign_binding_table_offsets();
313 void setup_payload_gen4();
314 void setup_payload_gen6();
315 void assign_curb_setup();
316 void calculate_urb_setup();
317 void assign_urb_setup();
318 bool assign_regs(bool allow_spilling
);
319 void assign_regs_trivial();
320 void get_used_mrfs(bool *mrf_used
);
321 void setup_payload_interference(struct ra_graph
*g
, int payload_reg_count
,
322 int first_payload_node
);
323 void setup_mrf_hack_interference(struct ra_graph
*g
,
324 int first_mrf_hack_node
);
325 int choose_spill_reg(struct ra_graph
*g
);
326 void spill_reg(int spill_reg
);
327 void split_virtual_grfs();
328 void compact_virtual_grfs();
329 void move_uniform_array_access_to_pull_constants();
330 void assign_constant_locations();
331 void demote_pull_constants();
332 void invalidate_live_intervals();
333 void calculate_live_intervals();
334 void calculate_register_pressure();
335 bool opt_algebraic();
337 bool opt_cse_local(bblock_t
*block
);
338 bool opt_copy_propagate();
339 bool try_copy_propagate(fs_inst
*inst
, int arg
, acp_entry
*entry
);
340 bool opt_copy_propagate_local(void *mem_ctx
, bblock_t
*block
,
342 void opt_drop_redundant_mov_to_flags();
343 bool opt_register_renaming();
344 bool register_coalesce();
345 bool compute_to_mrf();
346 bool dead_code_eliminate();
347 bool remove_duplicate_mrf_writes();
348 bool virtual_grf_interferes(int a
, int b
);
349 void schedule_instructions(instruction_scheduler_mode mode
);
350 void insert_gen4_send_dependency_workarounds();
351 void insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
353 void insert_gen4_post_send_dependency_workarounds(bblock_t
*block
,
355 void vfail(const char *msg
, va_list args
);
356 void fail(const char *msg
, ...);
357 void no16(const char *msg
, ...);
358 void lower_uniform_pull_constant_loads();
359 bool lower_load_payload();
361 void push_force_uncompressed();
362 void pop_force_uncompressed();
364 void emit_dummy_fs();
365 void emit_repclear_shader();
366 fs_reg
*emit_fragcoord_interpolation(ir_variable
*ir
);
367 fs_inst
*emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
368 glsl_interp_qualifier interpolation_mode
,
369 bool is_centroid
, bool is_sample
);
370 fs_reg
*emit_frontfacing_interpolation();
371 fs_reg
*emit_samplepos_setup();
372 fs_reg
*emit_sampleid_setup(ir_variable
*ir
);
373 fs_reg
*emit_general_interpolation(ir_variable
*ir
);
374 void emit_interpolation_setup_gen4();
375 void emit_interpolation_setup_gen6();
376 void compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
);
377 fs_reg
rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
378 bool is_rect
, uint32_t sampler
, int texunit
);
379 fs_inst
*emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
380 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
,
382 fs_inst
*emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
383 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
,
384 fs_reg sample_index
, uint32_t sampler
);
385 fs_inst
*emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
386 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
,
387 fs_reg sample_index
, fs_reg mcs
, fs_reg sampler
);
388 fs_reg
emit_mcs_fetch(ir_texture
*ir
, fs_reg coordinate
, fs_reg sampler
);
389 void emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
);
390 fs_reg
fix_math_operand(fs_reg src
);
391 fs_inst
*emit_math(enum opcode op
, fs_reg dst
, fs_reg src0
);
392 fs_inst
*emit_math(enum opcode op
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
393 void emit_lrp(const fs_reg
&dst
, const fs_reg
&x
, const fs_reg
&y
,
395 void emit_minmax(enum brw_conditional_mod conditionalmod
, const fs_reg
&dst
,
396 const fs_reg
&src0
, const fs_reg
&src1
);
397 bool try_emit_saturate(ir_expression
*ir
);
398 bool try_emit_mad(ir_expression
*ir
);
399 void try_replace_with_sel();
400 bool opt_peephole_sel();
401 bool opt_peephole_predicated_break();
402 bool opt_saturate_propagation();
403 void emit_bool_to_cond_code(ir_rvalue
*condition
);
404 void emit_if_gen6(ir_if
*ir
);
405 void emit_unspill(bblock_t
*block
, fs_inst
*inst
, fs_reg reg
,
406 uint32_t spill_offset
, int count
);
408 void emit_fragment_program_code();
409 void setup_fp_regs();
410 fs_reg
get_fp_src_reg(const prog_src_register
*src
);
411 fs_reg
get_fp_dst_reg(const prog_dst_register
*dst
);
412 void emit_fp_alu1(enum opcode opcode
,
413 const struct prog_instruction
*fpi
,
414 fs_reg dst
, fs_reg src
);
415 void emit_fp_alu2(enum opcode opcode
,
416 const struct prog_instruction
*fpi
,
417 fs_reg dst
, fs_reg src0
, fs_reg src1
);
418 void emit_fp_scalar_write(const struct prog_instruction
*fpi
,
419 fs_reg dst
, fs_reg src
);
420 void emit_fp_scalar_math(enum opcode opcode
,
421 const struct prog_instruction
*fpi
,
422 fs_reg dst
, fs_reg src
);
424 void emit_fp_minmax(const struct prog_instruction
*fpi
,
425 fs_reg dst
, fs_reg src0
, fs_reg src1
);
427 void emit_fp_sop(enum brw_conditional_mod conditional_mod
,
428 const struct prog_instruction
*fpi
,
429 fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg one
);
431 void emit_color_write(int target
, int index
, int first_color_mrf
);
432 void emit_alpha_test();
433 void emit_fb_writes();
435 void emit_shader_time_begin();
436 void emit_shader_time_end();
437 void emit_shader_time_write(enum shader_time_shader_type type
,
440 void emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
441 fs_reg dst
, fs_reg offset
, fs_reg src0
,
444 void emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
447 void emit_interpolate_expression(ir_expression
*ir
);
449 bool try_rewrite_rhs_to_dst(ir_assignment
*ir
,
452 fs_inst
*pre_rhs_inst
,
453 fs_inst
*last_rhs_inst
);
454 void emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
455 const glsl_type
*type
, bool predicated
);
456 void resolve_ud_negate(fs_reg
*reg
);
457 void resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
);
459 fs_reg
get_timestamp();
461 struct brw_reg
interp_reg(int location
, int channel
);
462 void setup_uniform_values(ir_variable
*ir
);
463 void setup_builtin_uniform_values(ir_variable
*ir
);
464 int implied_mrf_writes(fs_inst
*inst
);
466 virtual void dump_instructions();
467 virtual void dump_instructions(const char *name
);
468 void dump_instruction(backend_instruction
*inst
);
469 void dump_instruction(backend_instruction
*inst
, FILE *file
);
471 void visit_atomic_counter_intrinsic(ir_call
*ir
);
473 const void *const key
;
474 struct brw_stage_prog_data
*prog_data
;
475 unsigned int sanity_param_count
;
479 int *virtual_grf_sizes
;
480 int virtual_grf_count
;
481 int virtual_grf_array_size
;
482 int *virtual_grf_start
;
483 int *virtual_grf_end
;
484 brw::fs_live_variables
*live_intervals
;
486 int *regs_live_at_ip
;
488 /** Number of uniform variable components visited. */
491 /** Byte-offset for the next available spot in the scratch space buffer. */
492 unsigned last_scratch
;
495 * Array mapping UNIFORM register numbers to the pull parameter index,
496 * or -1 if this uniform register isn't being uploaded as a pull constant.
498 int *pull_constant_loc
;
501 * Array mapping UNIFORM register numbers to the push parameter index,
502 * or -1 if this uniform register isn't being uploaded as a push constant.
504 int *push_constant_loc
;
506 struct hash_table
*variable_ht
;
509 fs_reg outputs
[BRW_MAX_DRAW_BUFFERS
];
510 unsigned output_components
[BRW_MAX_DRAW_BUFFERS
];
511 fs_reg dual_src_output
;
513 int first_non_payload_grf
;
514 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
517 fs_reg
*fp_temp_regs
;
518 fs_reg
*fp_input_regs
;
520 /** @{ debug annotation info */
521 const char *current_annotation
;
527 bool simd16_unsupported
;
530 /* Result of last visit() method. */
533 /** Register numbers for thread payload fields. */
535 uint8_t source_depth_reg
;
536 uint8_t source_w_reg
;
537 uint8_t aa_dest_stencil_reg
;
538 uint8_t dest_depth_reg
;
539 uint8_t sample_pos_reg
;
540 uint8_t sample_mask_in_reg
;
541 uint8_t barycentric_coord_reg
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
543 /** The number of thread payload registers the hardware will supply. */
547 bool source_depth_to_render_target
;
548 bool runtime_check_aads_emit
;
554 fs_reg delta_x
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
555 fs_reg delta_y
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
556 fs_reg shader_start_time
;
559 bool spilled_any_registers
;
561 const unsigned dispatch_width
; /**< 8 or 16 */
563 int force_uncompressed_stack
;
567 * The fragment shader code generator.
569 * Translates FS IR to actual i965 assembly code.
574 fs_generator(struct brw_context
*brw
,
576 const struct brw_wm_prog_key
*key
,
577 struct brw_wm_prog_data
*prog_data
,
578 struct gl_shader_program
*shader_prog
,
579 struct gl_fragment_program
*fp
,
580 bool runtime_check_aads_emit
,
584 const unsigned *generate_assembly(const cfg_t
*simd8_cfg
,
585 const cfg_t
*simd16_cfg
,
586 unsigned *assembly_size
);
589 void generate_code(const cfg_t
*cfg
);
590 void fire_fb_write(fs_inst
*inst
,
592 struct brw_reg implied_header
,
594 void generate_fb_write(fs_inst
*inst
);
595 void generate_blorp_fb_write(fs_inst
*inst
);
596 void generate_rep_fb_write(fs_inst
*inst
);
597 void generate_pixel_xy(struct brw_reg dst
, bool is_x
);
598 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
599 struct brw_reg
*src
);
600 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
601 struct brw_reg sampler_index
);
602 void generate_math_gen6(fs_inst
*inst
,
605 struct brw_reg src1
);
606 void generate_math_gen4(fs_inst
*inst
,
609 void generate_math_g45(fs_inst
*inst
,
612 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
, struct brw_reg quality
);
613 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
614 struct brw_reg quality
, bool negate_value
);
615 void generate_scratch_write(fs_inst
*inst
, struct brw_reg src
);
616 void generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
);
617 void generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
);
618 void generate_uniform_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
,
619 struct brw_reg index
,
620 struct brw_reg offset
);
621 void generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
623 struct brw_reg surf_index
,
624 struct brw_reg offset
);
625 void generate_varying_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
,
626 struct brw_reg index
,
627 struct brw_reg offset
);
628 void generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
630 struct brw_reg index
,
631 struct brw_reg offset
);
632 void generate_mov_dispatch_to_flags(fs_inst
*inst
);
634 void generate_pixel_interpolator_query(fs_inst
*inst
,
637 struct brw_reg msg_data
,
640 void generate_set_omask(fs_inst
*inst
,
642 struct brw_reg sample_mask
);
644 void generate_set_sample_id(fs_inst
*inst
,
647 struct brw_reg src1
);
649 void generate_set_simd4x2_offset(fs_inst
*inst
,
651 struct brw_reg offset
);
652 void generate_discard_jump(fs_inst
*inst
);
654 void generate_pack_half_2x16_split(fs_inst
*inst
,
658 void generate_unpack_half_2x16_split(fs_inst
*inst
,
662 void generate_shader_time_add(fs_inst
*inst
,
663 struct brw_reg payload
,
664 struct brw_reg offset
,
665 struct brw_reg value
);
667 void generate_untyped_atomic(fs_inst
*inst
,
669 struct brw_reg atomic_op
,
670 struct brw_reg surf_index
);
672 void generate_untyped_surface_read(fs_inst
*inst
,
674 struct brw_reg surf_index
);
676 bool patch_discard_jumps_to_fb_writes();
678 struct brw_context
*brw
;
679 struct gl_context
*ctx
;
681 struct brw_compile
*p
;
682 gl_shader_stage stage
;
683 const void * const key
;
684 struct brw_stage_prog_data
* const prog_data
;
686 struct gl_shader_program
* const shader_prog
;
687 const struct gl_program
*prog
;
689 unsigned dispatch_width
; /**< 8 or 16 */
691 exec_list discard_halt_patches
;
692 bool runtime_check_aads_emit
;
693 const bool debug_flag
;
697 bool brw_do_channel_expressions(struct exec_list
*instructions
);
698 bool brw_do_vector_splitting(struct exec_list
*instructions
);
699 bool brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
);
701 struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
);