src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31 #include "brw_ir_fs.h"
  32 #include "brw_fs_builder.h"
  33 #include "compiler/glsl/ir.h"
  34 #include "compiler/nir/nir.h"
  35
  36 struct bblock_t;
  37 namespace {
  38    struct acp_entry;
  39 }
  40
  41 namespace brw {
  42    class fs_live_variables;
  43 }
  44
  45 struct brw_gs_compile;
  46
  47 static inline fs_reg
  48 offset(fs_reg reg, const brw::fs_builder& bld, unsigned delta)
  49 {
  50    switch (reg.file) {
  51    case BAD_FILE:
  52       break;
  53    case ARF:
  54    case FIXED_GRF:
  55    case MRF:
  56    case VGRF:
  57    case ATTR:
  58       return byte_offset(reg,
  59                          delta * reg.component_size(bld.dispatch_width()));
  60    case UNIFORM:
  61       reg.reg_offset += delta;
  62       break;
  63    case IMM:
  64       assert(delta == 0);
  65    }
  66    return reg;
  67 }
  68
  69 /**
  70  * The fragment shader front-end.
  71  *
  72  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
  73  */
  74 class fs_visitor : public backend_shader
  75 {
  76 public:
  77    fs_visitor(const struct brw_compiler *compiler, void *log_data,
  78               void *mem_ctx,
  79               const void *key,
  80               struct brw_stage_prog_data *prog_data,
  81               struct gl_program *prog,
  82               const nir_shader *shader,
  83               unsigned dispatch_width,
  84               int shader_time_index,
  85               const struct brw_vue_map *input_vue_map = NULL);
  86    fs_visitor(const struct brw_compiler *compiler, void *log_data,
  87               void *mem_ctx,
  88               struct brw_gs_compile *gs_compile,
  89               struct brw_gs_prog_data *prog_data,
  90               const nir_shader *shader,
  91               int shader_time_index);
  92    void init();
  93    ~fs_visitor();
  94
  95    fs_reg vgrf(const glsl_type *const type);
  96    void import_uniforms(fs_visitor *v);
  97    void setup_uniform_clipplane_values(gl_clip_plane *clip_planes);
  98    void compute_clip_distance(gl_clip_plane *clip_planes);
  99
 100    fs_inst *get_instruction_generating_reg(fs_inst *start,
 101                                            fs_inst *end,
 102                                            const fs_reg &reg);
 103
 104    void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld,
 105                                    const fs_reg &dst,
 106                                    const fs_reg &surf_index,
 107                                    const fs_reg &varying_offset,
 108                                    uint32_t const_offset);
 109    void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf);
 110
 111    bool run_fs(bool do_rep_send);
 112    bool run_vs(gl_clip_plane *clip_planes);
 113    bool run_tcs_single_patch();
 114    bool run_tes();
 115    bool run_gs();
 116    bool run_cs();
 117    void optimize();
 118    void allocate_registers();
 119    void setup_fs_payload_gen4();
 120    void setup_fs_payload_gen6();
 121    void setup_vs_payload();
 122    void setup_gs_payload();
 123    void setup_cs_payload();
 124    void fixup_3src_null_dest();
 125    void assign_curb_setup();
 126    void calculate_urb_setup();
 127    void assign_urb_setup();
 128    void convert_attr_sources_to_hw_regs(fs_inst *inst);
 129    void assign_vs_urb_setup();
 130    void assign_tcs_single_patch_urb_setup();
 131    void assign_tes_urb_setup();
 132    void assign_gs_urb_setup();
 133    bool assign_regs(bool allow_spilling);
 134    void assign_regs_trivial();
 135    void calculate_payload_ranges(int payload_node_count,
 136                                  int *payload_last_use_ip);
 137    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 138                                    int first_payload_node);
 139    int choose_spill_reg(struct ra_graph *g);
 140    void spill_reg(int spill_reg);
 141    void split_virtual_grfs();
 142    bool compact_virtual_grfs();
 143    void assign_constant_locations();
 144    void lower_constant_loads();
 145    void invalidate_live_intervals();
 146    void calculate_live_intervals();
 147    void calculate_register_pressure();
 148    void validate();
 149    bool opt_algebraic();
 150    bool opt_redundant_discard_jumps();
 151    bool opt_cse();
 152    bool opt_cse_local(bblock_t *block);
 153    bool opt_copy_propagate();
 154    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 155    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 156    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 157                                  exec_list *acp);
 158    bool opt_drop_redundant_mov_to_flags();
 159    bool opt_register_renaming();
 160    bool register_coalesce();
 161    bool compute_to_mrf();
 162    bool eliminate_find_live_channel();
 163    bool dead_code_eliminate();
 164    bool remove_duplicate_mrf_writes();
 165
 166    bool opt_sampler_eot();
 167    bool virtual_grf_interferes(int a, int b);
 168    void schedule_instructions(instruction_scheduler_mode mode);
 169    void insert_gen4_send_dependency_workarounds();
 170    void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
 171                                                     fs_inst *inst);
 172    void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
 173                                                      fs_inst *inst);
 174    void vfail(const char *msg, va_list args);
 175    void fail(const char *msg, ...);
 176    void no16(const char *msg);
 177    void lower_uniform_pull_constant_loads();
 178    bool lower_load_payload();
 179    bool lower_logical_sends();
 180    bool lower_integer_multiplication();
 181    bool lower_minmax();
 182    bool lower_simd_width();
 183    bool opt_combine_constants();
 184
 185    void emit_dummy_fs();
 186    void emit_repclear_shader();
 187    fs_reg *emit_fragcoord_interpolation(bool pixel_center_integer,
 188                                         bool origin_upper_left);
 189    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 190                          glsl_interp_qualifier interpolation_mode,
 191                          bool is_centroid, bool is_sample);
 192    fs_reg *emit_frontfacing_interpolation();
 193    fs_reg *emit_samplepos_setup();
 194    fs_reg *emit_sampleid_setup();
 195    fs_reg *emit_samplemaskin_setup();
 196    void emit_general_interpolation(fs_reg *attr, const char *name,
 197                                    const glsl_type *type,
 198                                    glsl_interp_qualifier interpolation_mode,
 199                                    int *location, bool mod_centroid,
 200                                    bool mod_sample);
 201    fs_reg *emit_vs_system_value(int location);
 202    void emit_interpolation_setup_gen4();
 203    void emit_interpolation_setup_gen6();
 204    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
 205    void emit_texture(ir_texture_opcode op,
 206                      const glsl_type *dest_type,
 207                      fs_reg coordinate, int components,
 208                      fs_reg shadow_c,
 209                      fs_reg lod, fs_reg dpdy, int grad_components,
 210                      fs_reg sample_index,
 211                      fs_reg offset,
 212                      fs_reg mcs,
 213                      int gather_component,
 214                      bool is_cube_array,
 215                      uint32_t surface,
 216                      fs_reg surface_reg,
 217                      uint32_t sampler,
 218                      fs_reg sampler_reg,
 219                      unsigned return_channels);
 220    fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
 221                          const fs_reg &sampler);
 222    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
 223    fs_reg resolve_source_modifiers(const fs_reg &src);
 224    void emit_discard_jump();
 225    bool opt_peephole_sel();
 226    bool opt_peephole_predicated_break();
 227    bool opt_saturate_propagation();
 228    bool opt_cmod_propagation();
 229    bool opt_zero_samples();
 230    void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
 231                      uint32_t spill_offset, int count);
 232    void emit_spill(bblock_t *block, fs_inst *inst, fs_reg reg,
 233                    uint32_t spill_offset, int count);
 234
 235    void emit_nir_code();
 236    void nir_setup_inputs();
 237    void nir_setup_single_output_varying(fs_reg *reg, const glsl_type *type,
 238                                         unsigned *location);
 239    void nir_setup_outputs();
 240    void nir_setup_uniforms();
 241    void nir_emit_system_values();
 242    void nir_emit_impl(nir_function_impl *impl);
 243    void nir_emit_cf_list(exec_list *list);
 244    void nir_emit_if(nir_if *if_stmt);
 245    void nir_emit_loop(nir_loop *loop);
 246    void nir_emit_block(nir_block *block);
 247    void nir_emit_instr(nir_instr *instr);
 248    void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr);
 249    void nir_emit_load_const(const brw::fs_builder &bld,
 250                             nir_load_const_instr *instr);
 251    void nir_emit_undef(const brw::fs_builder &bld,
 252                        nir_ssa_undef_instr *instr);
 253    void nir_emit_vs_intrinsic(const brw::fs_builder &bld,
 254                               nir_intrinsic_instr *instr);
 255    void nir_emit_tcs_intrinsic(const brw::fs_builder &bld,
 256                                nir_intrinsic_instr *instr);
 257    void nir_emit_gs_intrinsic(const brw::fs_builder &bld,
 258                               nir_intrinsic_instr *instr);
 259    void nir_emit_fs_intrinsic(const brw::fs_builder &bld,
 260                               nir_intrinsic_instr *instr);
 261    void nir_emit_cs_intrinsic(const brw::fs_builder &bld,
 262                               nir_intrinsic_instr *instr);
 263    void nir_emit_intrinsic(const brw::fs_builder &bld,
 264                            nir_intrinsic_instr *instr);
 265    void nir_emit_tes_intrinsic(const brw::fs_builder &bld,
 266                                nir_intrinsic_instr *instr);
 267    void nir_emit_ssbo_atomic(const brw::fs_builder &bld,
 268                              int op, nir_intrinsic_instr *instr);
 269    void nir_emit_shared_atomic(const brw::fs_builder &bld,
 270                                int op, nir_intrinsic_instr *instr);
 271    void nir_emit_texture(const brw::fs_builder &bld,
 272                          nir_tex_instr *instr);
 273    void nir_emit_jump(const brw::fs_builder &bld,
 274                       nir_jump_instr *instr);
 275    fs_reg get_nir_src(nir_src src);
 276    fs_reg get_nir_dest(nir_dest dest);
 277    fs_reg get_nir_image_deref(const nir_deref_var *deref);
 278    fs_reg get_indirect_offset(nir_intrinsic_instr *instr);
 279    void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst,
 280                      unsigned wr_mask);
 281
 282    bool optimize_extract_to_float(nir_alu_instr *instr,
 283                                   const fs_reg &result);
 284    bool optimize_frontfacing_ternary(nir_alu_instr *instr,
 285                                      const fs_reg &result);
 286
 287    void emit_alpha_test();
 288    fs_inst *emit_single_fb_write(const brw::fs_builder &bld,
 289                                  fs_reg color1, fs_reg color2,
 290                                  fs_reg src0_alpha, unsigned components);
 291    void emit_fb_writes();
 292    void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg());
 293    void set_gs_stream_control_data_bits(const fs_reg &vertex_count,
 294                                         unsigned stream_id);
 295    void emit_gs_control_data_bits(const fs_reg &vertex_count);
 296    void emit_gs_end_primitive(const nir_src &vertex_count_nir_src);
 297    void emit_gs_vertex(const nir_src &vertex_count_nir_src,
 298                        unsigned stream_id);
 299    void emit_gs_thread_end();
 300    void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src,
 301                            unsigned base_offset, const nir_src &offset_src,
 302                            unsigned num_components);
 303    void emit_cs_terminate();
 304    fs_reg *emit_cs_local_invocation_id_setup();
 305    fs_reg *emit_cs_work_group_id_setup();
 306
 307    void emit_barrier();
 308
 309    void emit_shader_time_begin();
 310    void emit_shader_time_end();
 311    void SHADER_TIME_ADD(const brw::fs_builder &bld,
 312                         int shader_time_subindex,
 313                         fs_reg value);
 314
 315    fs_reg get_timestamp(const brw::fs_builder &bld);
 316
 317    struct brw_reg interp_reg(int location, int channel);
 318
 319    int implied_mrf_writes(fs_inst *inst);
 320
 321    virtual void dump_instructions();
 322    virtual void dump_instructions(const char *name);
 323    void dump_instruction(backend_instruction *inst);
 324    void dump_instruction(backend_instruction *inst, FILE *file);
 325
 326    const void *const key;
 327    const struct brw_sampler_prog_key_data *key_tex;
 328
 329    struct brw_gs_compile *gs_compile;
 330
 331    struct brw_stage_prog_data *prog_data;
 332    struct gl_program *prog;
 333
 334    const struct brw_vue_map *input_vue_map;
 335
 336    int *virtual_grf_start;
 337    int *virtual_grf_end;
 338    brw::fs_live_variables *live_intervals;
 339
 340    int *regs_live_at_ip;
 341
 342    /** Number of uniform variable components visited. */
 343    unsigned uniforms;
 344
 345    /** Byte-offset for the next available spot in the scratch space buffer. */
 346    unsigned last_scratch;
 347
 348    /**
 349     * Array mapping UNIFORM register numbers to the pull parameter index,
 350     * or -1 if this uniform register isn't being uploaded as a pull constant.
 351     */
 352    int *pull_constant_loc;
 353
 354    /**
 355     * Array mapping UNIFORM register numbers to the push parameter index,
 356     * or -1 if this uniform register isn't being uploaded as a push constant.
 357     */
 358    int *push_constant_loc;
 359
 360    fs_reg frag_depth;
 361    fs_reg frag_stencil;
 362    fs_reg sample_mask;
 363    fs_reg outputs[VARYING_SLOT_MAX];
 364    unsigned output_components[VARYING_SLOT_MAX];
 365    fs_reg dual_src_output;
 366    bool do_dual_src;
 367    int first_non_payload_grf;
 368    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 369    unsigned max_grf;
 370
 371    fs_reg *nir_locals;
 372    fs_reg *nir_ssa_values;
 373    fs_reg nir_inputs;
 374    fs_reg nir_outputs;
 375    fs_reg *nir_system_values;
 376
 377    bool failed;
 378    char *fail_msg;
 379    bool simd16_unsupported;
 380    char *no16_msg;
 381
 382    /* Result of last visit() method. Still used by emit_texture() */
 383    fs_reg result;
 384
 385    /** Register numbers for thread payload fields. */
 386    struct thread_payload {
 387       uint8_t source_depth_reg;
 388       uint8_t source_w_reg;
 389       uint8_t aa_dest_stencil_reg;
 390       uint8_t dest_depth_reg;
 391       uint8_t sample_pos_reg;
 392       uint8_t sample_mask_in_reg;
 393       uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 394       uint8_t local_invocation_id_reg;
 395
 396       /** The number of thread payload registers the hardware will supply. */
 397       uint8_t num_regs;
 398    } payload;
 399
 400    bool source_depth_to_render_target;
 401    bool runtime_check_aads_emit;
 402
 403    fs_reg pixel_x;
 404    fs_reg pixel_y;
 405    fs_reg wpos_w;
 406    fs_reg pixel_w;
 407    fs_reg delta_xy[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 408    fs_reg shader_start_time;
 409    fs_reg userplane[MAX_CLIP_PLANES];
 410    fs_reg final_gs_vertex_count;
 411    fs_reg control_data_bits;
 412    fs_reg invocation_id;
 413
 414    unsigned grf_used;
 415    bool spilled_any_registers;
 416
 417    const unsigned dispatch_width; /**< 8 or 16 */
 418    unsigned min_dispatch_width;
 419
 420    int shader_time_index;
 421
 422    unsigned promoted_constants;
 423    brw::fs_builder bld;
 424 };
 425
 426 /**
 427  * The fragment shader code generator.
 428  *
 429  * Translates FS IR to actual i965 assembly code.
 430  */
 431 class fs_generator
 432 {
 433 public:
 434    fs_generator(const struct brw_compiler *compiler, void *log_data,
 435                 void *mem_ctx,
 436                 const void *key,
 437                 struct brw_stage_prog_data *prog_data,
 438                 unsigned promoted_constants,
 439                 bool runtime_check_aads_emit,
 440                 gl_shader_stage stage);
 441    ~fs_generator();
 442
 443    void enable_debug(const char *shader_name);
 444    int generate_code(const cfg_t *cfg, int dispatch_width);
 445    const unsigned *get_assembly(unsigned int *assembly_size);
 446
 447 private:
 448    void fire_fb_write(fs_inst *inst,
 449                       struct brw_reg payload,
 450                       struct brw_reg implied_header,
 451                       GLuint nr);
 452    void generate_fb_write(fs_inst *inst, struct brw_reg payload);
 453    void generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload);
 454    void generate_urb_write(fs_inst *inst, struct brw_reg payload);
 455    void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
 456    void generate_stencil_ref_packing(fs_inst *inst, struct brw_reg dst,
 457                                      struct brw_reg src);
 458    void generate_barrier(fs_inst *inst, struct brw_reg src);
 459    void generate_blorp_fb_write(fs_inst *inst, struct brw_reg payload);
 460    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 461                          struct brw_reg *src);
 462    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 463                      struct brw_reg surface_index,
 464                      struct brw_reg sampler_index);
 465    void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst,
 466                                  struct brw_reg src,
 467                                  struct brw_reg surf_index);
 468    void generate_math_gen6(fs_inst *inst,
 469                            struct brw_reg dst,
 470                            struct brw_reg src0,
 471                            struct brw_reg src1);
 472    void generate_math_gen4(fs_inst *inst,
 473                            struct brw_reg dst,
 474                            struct brw_reg src);
 475    void generate_math_g45(fs_inst *inst,
 476                           struct brw_reg dst,
 477                           struct brw_reg src);
 478    void generate_ddx(enum opcode op, struct brw_reg dst, struct brw_reg src);
 479    void generate_ddy(enum opcode op, struct brw_reg dst, struct brw_reg src,
 480                      bool negate_value);
 481    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 482    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 483    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 484    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 485                                             struct brw_reg index,
 486                                             struct brw_reg offset);
 487    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 488                                                  struct brw_reg dst,
 489                                                  struct brw_reg surf_index,
 490                                                  struct brw_reg offset);
 491    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 492                                             struct brw_reg index,
 493                                             struct brw_reg offset);
 494    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 495                                                  struct brw_reg dst,
 496                                                  struct brw_reg index,
 497                                                  struct brw_reg offset);
 498    void generate_mov_dispatch_to_flags(fs_inst *inst);
 499
 500    void generate_pixel_interpolator_query(fs_inst *inst,
 501                                           struct brw_reg dst,
 502                                           struct brw_reg src,
 503                                           struct brw_reg msg_data,
 504                                           unsigned msg_type);
 505
 506    void generate_set_sample_id(fs_inst *inst,
 507                                struct brw_reg dst,
 508                                struct brw_reg src0,
 509                                struct brw_reg src1);
 510
 511    void generate_set_simd4x2_offset(fs_inst *inst,
 512                                     struct brw_reg dst,
 513                                     struct brw_reg offset);
 514    void generate_discard_jump(fs_inst *inst);
 515
 516    void generate_pack_half_2x16_split(fs_inst *inst,
 517                                       struct brw_reg dst,
 518                                       struct brw_reg x,
 519                                       struct brw_reg y);
 520    void generate_unpack_half_2x16_split(fs_inst *inst,
 521                                         struct brw_reg dst,
 522                                         struct brw_reg src);
 523
 524    void generate_shader_time_add(fs_inst *inst,
 525                                  struct brw_reg payload,
 526                                  struct brw_reg offset,
 527                                  struct brw_reg value);
 528
 529    void generate_mov_indirect(fs_inst *inst,
 530                               struct brw_reg dst,
 531                               struct brw_reg reg,
 532                               struct brw_reg indirect_byte_offset);
 533
 534    bool patch_discard_jumps_to_fb_writes();
 535
 536    const struct brw_compiler *compiler;
 537    void *log_data; /* Passed to compiler->*_log functions */
 538
 539    const struct brw_device_info *devinfo;
 540
 541    struct brw_codegen *p;
 542    const void * const key;
 543    struct brw_stage_prog_data * const prog_data;
 544
 545    unsigned dispatch_width; /**< 8 or 16 */
 546
 547    exec_list discard_halt_patches;
 548    unsigned promoted_constants;
 549    bool runtime_check_aads_emit;
 550    bool debug_flag;
 551    const char *shader_name;
 552    gl_shader_stage stage;
 553    void *mem_ctx;
 554 };
 555
 556 bool brw_do_channel_expressions(struct exec_list *instructions);
 557 bool brw_do_vector_splitting(struct exec_list *instructions);