src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31
  32 extern "C" {
  33
  34 #include <sys/types.h>
  35
  36 #include "main/macros.h"
  37 #include "main/shaderobj.h"
  38 #include "main/uniforms.h"
  39 #include "program/prog_parameter.h"
  40 #include "program/prog_print.h"
  41 #include "program/prog_optimize.h"
  42 #include "program/register_allocate.h"
  43 #include "program/sampler.h"
  44 #include "program/hash_table.h"
  45 #include "brw_context.h"
  46 #include "brw_eu.h"
  47 #include "brw_wm.h"
  48 #include "brw_shader.h"
  49 #include "intel_asm_printer.h"
  50 }
  51 #include "gen8_generator.h"
  52 #include "glsl/glsl_types.h"
  53 #include "glsl/ir.h"
  54
  55 #define MAX_SAMPLER_MESSAGE_SIZE 11
  56
  57 struct bblock_t;
  58 namespace {
  59    struct acp_entry;
  60 }
  61
  62 namespace brw {
  63    class fs_live_variables;
  64 }
  65
  66 class fs_reg {
  67 public:
  68    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  69
  70    void init();
  71
  72    fs_reg();
  73    fs_reg(float f);
  74    fs_reg(int32_t i);
  75    fs_reg(uint32_t u);
  76    fs_reg(struct brw_reg fixed_hw_reg);
  77    fs_reg(enum register_file file, int reg);
  78    fs_reg(enum register_file file, int reg, uint32_t type);
  79    fs_reg(class fs_visitor *v, const struct glsl_type *type);
  80
  81    bool equals(const fs_reg &r) const;
  82    bool is_zero() const;
  83    bool is_one() const;
  84    bool is_null() const;
  85    bool is_valid_3src() const;
  86    bool is_contiguous() const;
  87    bool is_accumulator() const;
  88
  89    fs_reg &apply_stride(unsigned stride);
  90    /** Smear a channel of the reg to all channels. */
  91    fs_reg &set_smear(unsigned subreg);
  92
  93    /** Register file: GRF, MRF, IMM. */
  94    enum register_file file;
  95    /** Register type.  BRW_REGISTER_TYPE_* */
  96    uint8_t type;
  97    /**
  98     * Register number.  For MRF, it's the hardware register.  For
  99     * GRF, it's a virtual register number until register allocation
 100     */
 101    uint16_t reg;
 102    /**
 103     * Offset from the start of the contiguous register block.
 104     *
 105     * For pre-register-allocation GRFs, this is in units of a float per pixel
 106     * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
 107     * For uniforms, this is in units of 1 float.
 108     */
 109    int reg_offset;
 110    /**
 111     * Offset in bytes from the start of the register.  Values up to a
 112     * backend_reg::reg_offset unit are valid.
 113     */
 114    int subreg_offset;
 115
 116    struct brw_reg fixed_hw_reg;
 117
 118    fs_reg *reladdr;
 119
 120    bool negate;
 121    bool abs;
 122
 123    /** Register region horizontal stride */
 124    uint8_t stride;
 125 };
 126
 127 static inline fs_reg
 128 retype(fs_reg reg, unsigned type)
 129 {
 130    reg.fixed_hw_reg.type = reg.type = type;
 131    return reg;
 132 }
 133
 134 static inline fs_reg
 135 offset(fs_reg reg, unsigned delta)
 136 {
 137    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 138    reg.reg_offset += delta;
 139    return reg;
 140 }
 141
 142 static inline fs_reg
 143 byte_offset(fs_reg reg, unsigned delta)
 144 {
 145    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 146    reg.subreg_offset += delta;
 147    return reg;
 148 }
 149
 150 /**
 151  * Get either of the 8-component halves of a 16-component register.
 152  *
 153  * Note: this also works if \c reg represents a SIMD16 pair of registers.
 154  */
 155 static inline fs_reg
 156 half(const fs_reg &reg, unsigned idx)
 157 {
 158    assert(idx < 2);
 159    assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
 160    return byte_offset(reg, 8 * idx * reg.stride * type_sz(reg.type));
 161 }
 162
 163 static const fs_reg reg_undef;
 164 static const fs_reg reg_null_f(retype(brw_null_reg(), BRW_REGISTER_TYPE_F));
 165 static const fs_reg reg_null_d(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 166 static const fs_reg reg_null_ud(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 167
 168 class ip_record : public exec_node {
 169 public:
 170    DECLARE_RALLOC_CXX_OPERATORS(ip_record)
 171
 172    ip_record(int ip)
 173    {
 174       this->ip = ip;
 175    }
 176
 177    int ip;
 178 };
 179
 180 class fs_inst : public backend_instruction {
 181    fs_inst &operator=(const fs_inst &);
 182
 183 public:
 184    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 185
 186    void init(enum opcode opcode, const fs_reg &dst, fs_reg *src, int sources);
 187
 188    fs_inst(enum opcode opcode = BRW_OPCODE_NOP, const fs_reg &dst = reg_undef);
 189    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 190    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 191            const fs_reg &src1);
 192    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 193            const fs_reg &src1, const fs_reg &src2);
 194    fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources);
 195    fs_inst(const fs_inst &that);
 196
 197    void resize_sources(uint8_t num_sources);
 198
 199    bool equals(fs_inst *inst) const;
 200    bool overwrites_reg(const fs_reg &reg) const;
 201    bool is_send_from_grf() const;
 202    bool is_partial_write() const;
 203    int regs_read(fs_visitor *v, int arg) const;
 204    bool can_do_source_mods(struct brw_context *brw);
 205
 206    bool reads_flag() const;
 207    bool writes_flag() const;
 208
 209    fs_reg dst;
 210    fs_reg *src;
 211
 212    uint32_t texture_offset; /**< Texture offset bitfield */
 213    uint32_t offset; /* spill/unspill offset */
 214
 215    uint8_t sources; /**< Number of fs_reg sources. */
 216    uint8_t conditional_mod; /**< BRW_CONDITIONAL_* */
 217
 218    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 219     * mod and predication.
 220     */
 221    uint8_t flag_subreg;
 222
 223    uint8_t mlen; /**< SEND message length */
 224    uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
 225    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 226    uint8_t sampler;
 227    uint8_t target; /**< MRT target. */
 228    bool saturate:1;
 229    bool eot:1;
 230    bool header_present:1;
 231    bool shadow_compare:1;
 232    bool force_uncompressed:1;
 233    bool force_sechalf:1;
 234    bool force_writemask_all:1;
 235    bool no_dd_clear:1;
 236    bool no_dd_check:1;
 237 };
 238
 239 /**
 240  * The fragment shader front-end.
 241  *
 242  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
 243  */
 244 class fs_visitor : public backend_visitor
 245 {
 246 public:
 247
 248    fs_visitor(struct brw_context *brw,
 249               void *mem_ctx,
 250               const struct brw_wm_prog_key *key,
 251               struct brw_wm_prog_data *prog_data,
 252               struct gl_shader_program *shader_prog,
 253               struct gl_fragment_program *fp,
 254               unsigned dispatch_width);
 255    ~fs_visitor();
 256
 257    fs_reg *variable_storage(ir_variable *var);
 258    int virtual_grf_alloc(int size);
 259    void import_uniforms(fs_visitor *v);
 260
 261    void visit(ir_variable *ir);
 262    void visit(ir_assignment *ir);
 263    void visit(ir_dereference_variable *ir);
 264    void visit(ir_dereference_record *ir);
 265    void visit(ir_dereference_array *ir);
 266    void visit(ir_expression *ir);
 267    void visit(ir_texture *ir);
 268    void visit(ir_if *ir);
 269    void visit(ir_constant *ir);
 270    void visit(ir_swizzle *ir);
 271    void visit(ir_return *ir);
 272    void visit(ir_loop *ir);
 273    void visit(ir_loop_jump *ir);
 274    void visit(ir_discard *ir);
 275    void visit(ir_call *ir);
 276    void visit(ir_function *ir);
 277    void visit(ir_function_signature *ir);
 278    void visit(ir_emit_vertex *);
 279    void visit(ir_end_primitive *);
 280
 281    uint32_t gather_channel(ir_texture *ir, int sampler);
 282    void swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler);
 283
 284    fs_inst *emit(fs_inst *inst);
 285    void emit(exec_list list);
 286
 287    fs_inst *emit(enum opcode opcode);
 288    fs_inst *emit(enum opcode opcode, const fs_reg &dst);
 289    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 290    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 291                  const fs_reg &src1);
 292    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 293                  const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 294    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 295                  fs_reg src[], int sources);
 296
 297    fs_inst *MOV(const fs_reg &dst, const fs_reg &src);
 298    fs_inst *NOT(const fs_reg &dst, const fs_reg &src);
 299    fs_inst *RNDD(const fs_reg &dst, const fs_reg &src);
 300    fs_inst *RNDE(const fs_reg &dst, const fs_reg &src);
 301    fs_inst *RNDZ(const fs_reg &dst, const fs_reg &src);
 302    fs_inst *FRC(const fs_reg &dst, const fs_reg &src);
 303    fs_inst *ADD(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 304    fs_inst *MUL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 305    fs_inst *MACH(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 306    fs_inst *MAC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 307    fs_inst *SHL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 308    fs_inst *SHR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 309    fs_inst *ASR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 310    fs_inst *AND(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 311    fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 312    fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 313    fs_inst *IF(uint32_t predicate);
 314    fs_inst *IF(const fs_reg &src0, const fs_reg &src1, uint32_t condition);
 315    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 316                 uint32_t condition);
 317    fs_inst *LRP(const fs_reg &dst, const fs_reg &a, const fs_reg &y,
 318                 const fs_reg &x);
 319    fs_inst *DEP_RESOLVE_MOV(int grf);
 320    fs_inst *BFREV(const fs_reg &dst, const fs_reg &value);
 321    fs_inst *BFE(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset,
 322                 const fs_reg &value);
 323    fs_inst *BFI1(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset);
 324    fs_inst *BFI2(const fs_reg &dst, const fs_reg &bfi1_dst,
 325                  const fs_reg &insert, const fs_reg &base);
 326    fs_inst *FBH(const fs_reg &dst, const fs_reg &value);
 327    fs_inst *FBL(const fs_reg &dst, const fs_reg &value);
 328    fs_inst *CBIT(const fs_reg &dst, const fs_reg &value);
 329    fs_inst *MAD(const fs_reg &dst, const fs_reg &c, const fs_reg &b,
 330                 const fs_reg &a);
 331    fs_inst *ADDC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 332    fs_inst *SUBB(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 333    fs_inst *SEL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 334
 335    int type_size(const struct glsl_type *type);
 336    fs_inst *get_instruction_generating_reg(fs_inst *start,
 337                                            fs_inst *end,
 338                                            const fs_reg &reg);
 339
 340    fs_inst *LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources);
 341
 342    exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
 343                                         const fs_reg &surf_index,
 344                                         const fs_reg &varying_offset,
 345                                         uint32_t const_offset);
 346
 347    bool run();
 348    void assign_binding_table_offsets();
 349    void setup_payload_gen4();
 350    void setup_payload_gen6();
 351    void assign_curb_setup();
 352    void calculate_urb_setup();
 353    void assign_urb_setup();
 354    bool assign_regs(bool allow_spilling);
 355    void assign_regs_trivial();
 356    void get_used_mrfs(bool *mrf_used);
 357    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 358                                    int first_payload_node);
 359    void setup_mrf_hack_interference(struct ra_graph *g,
 360                                     int first_mrf_hack_node);
 361    int choose_spill_reg(struct ra_graph *g);
 362    void spill_reg(int spill_reg);
 363    void split_virtual_grfs();
 364    void compact_virtual_grfs();
 365    void move_uniform_array_access_to_pull_constants();
 366    void assign_constant_locations();
 367    void demote_pull_constants();
 368    void invalidate_live_intervals();
 369    void calculate_live_intervals(const cfg_t *cfg = NULL);
 370    void calculate_register_pressure();
 371    bool opt_algebraic();
 372    bool opt_cse();
 373    bool opt_cse_local(bblock_t *block, exec_list *aeb);
 374    bool opt_copy_propagate();
 375    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 376    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 377                                  exec_list *acp);
 378    void opt_drop_redundant_mov_to_flags();
 379    bool register_coalesce();
 380    bool compute_to_mrf();
 381    bool dead_code_eliminate();
 382    bool remove_duplicate_mrf_writes();
 383    bool virtual_grf_interferes(int a, int b);
 384    void schedule_instructions(instruction_scheduler_mode mode);
 385    void insert_gen4_send_dependency_workarounds();
 386    void insert_gen4_pre_send_dependency_workarounds(fs_inst *inst);
 387    void insert_gen4_post_send_dependency_workarounds(fs_inst *inst);
 388    void vfail(const char *msg, va_list args);
 389    void fail(const char *msg, ...);
 390    void no16(const char *msg, ...);
 391    void lower_uniform_pull_constant_loads();
 392    bool lower_load_payload();
 393
 394    void push_force_uncompressed();
 395    void pop_force_uncompressed();
 396
 397    void emit_dummy_fs();
 398    fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
 399    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 400                          glsl_interp_qualifier interpolation_mode,
 401                          bool is_centroid, bool is_sample);
 402    fs_reg *emit_frontfacing_interpolation(ir_variable *ir);
 403    fs_reg *emit_samplepos_setup(ir_variable *ir);
 404    fs_reg *emit_sampleid_setup(ir_variable *ir);
 405    fs_reg *emit_general_interpolation(ir_variable *ir);
 406    void emit_interpolation_setup_gen4();
 407    void emit_interpolation_setup_gen6();
 408    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
 409    fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
 410                            bool is_rect, int sampler, int texunit);
 411    fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 412                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2);
 413    fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 414                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 415                               fs_reg sample_index);
 416    fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 417                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 418                               fs_reg sample_index, fs_reg mcs, int sampler);
 419    fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, int sampler);
 420    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
 421    fs_reg fix_math_operand(fs_reg src);
 422    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 423    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 424    void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
 425                  const fs_reg &a);
 426    void emit_minmax(uint32_t conditionalmod, const fs_reg &dst,
 427                     const fs_reg &src0, const fs_reg &src1);
 428    bool try_emit_saturate(ir_expression *ir);
 429    bool try_emit_mad(ir_expression *ir);
 430    void try_replace_with_sel();
 431    bool opt_peephole_sel();
 432    bool opt_peephole_predicated_break();
 433    bool opt_saturate_propagation();
 434    void emit_bool_to_cond_code(ir_rvalue *condition);
 435    void emit_if_gen6(ir_if *ir);
 436    void emit_unspill(fs_inst *inst, fs_reg reg, uint32_t spill_offset,
 437                      int count);
 438
 439    void emit_fragment_program_code();
 440    void setup_fp_regs();
 441    fs_reg get_fp_src_reg(const prog_src_register *src);
 442    fs_reg get_fp_dst_reg(const prog_dst_register *dst);
 443    void emit_fp_alu1(enum opcode opcode,
 444                      const struct prog_instruction *fpi,
 445                      fs_reg dst, fs_reg src);
 446    void emit_fp_alu2(enum opcode opcode,
 447                      const struct prog_instruction *fpi,
 448                      fs_reg dst, fs_reg src0, fs_reg src1);
 449    void emit_fp_scalar_write(const struct prog_instruction *fpi,
 450                              fs_reg dst, fs_reg src);
 451    void emit_fp_scalar_math(enum opcode opcode,
 452                             const struct prog_instruction *fpi,
 453                             fs_reg dst, fs_reg src);
 454
 455    void emit_fp_minmax(const struct prog_instruction *fpi,
 456                        fs_reg dst, fs_reg src0, fs_reg src1);
 457
 458    void emit_fp_sop(uint32_t conditional_mod,
 459                     const struct prog_instruction *fpi,
 460                     fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
 461
 462    void emit_color_write(int target, int index, int first_color_mrf);
 463    void emit_alpha_test();
 464    void emit_fb_writes();
 465
 466    void emit_shader_time_begin();
 467    void emit_shader_time_end();
 468    void emit_shader_time_write(enum shader_time_shader_type type,
 469                                fs_reg value);
 470
 471    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 472                             fs_reg dst, fs_reg offset, fs_reg src0,
 473                             fs_reg src1);
 474
 475    void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
 476                                   fs_reg offset);
 477
 478    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 479                                fs_reg dst,
 480                                fs_reg src,
 481                                fs_inst *pre_rhs_inst,
 482                                fs_inst *last_rhs_inst);
 483    void emit_assignment_writes(fs_reg &l, fs_reg &r,
 484                                const glsl_type *type, bool predicated);
 485    void resolve_ud_negate(fs_reg *reg);
 486    void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
 487
 488    fs_reg get_timestamp();
 489
 490    struct brw_reg interp_reg(int location, int channel);
 491    void setup_uniform_values(ir_variable *ir);
 492    void setup_builtin_uniform_values(ir_variable *ir);
 493    int implied_mrf_writes(fs_inst *inst);
 494
 495    virtual void dump_instructions();
 496    virtual void dump_instructions(const char *name);
 497    void dump_instruction(backend_instruction *inst);
 498    void dump_instruction(backend_instruction *inst, FILE *file);
 499
 500    void visit_atomic_counter_intrinsic(ir_call *ir);
 501
 502    struct gl_fragment_program *fp;
 503    const struct brw_wm_prog_key *const key;
 504    struct brw_wm_prog_data *prog_data;
 505    unsigned int sanity_param_count;
 506
 507    int *param_size;
 508
 509    int *virtual_grf_sizes;
 510    int virtual_grf_count;
 511    int virtual_grf_array_size;
 512    int *virtual_grf_start;
 513    int *virtual_grf_end;
 514    brw::fs_live_variables *live_intervals;
 515
 516    int *regs_live_at_ip;
 517
 518    /** Number of uniform variable components visited. */
 519    unsigned uniforms;
 520
 521    /** Byte-offset for the next available spot in the scratch space buffer. */
 522    unsigned last_scratch;
 523
 524    /**
 525     * Array mapping UNIFORM register numbers to the pull parameter index,
 526     * or -1 if this uniform register isn't being uploaded as a pull constant.
 527     */
 528    int *pull_constant_loc;
 529
 530    /**
 531     * Array mapping UNIFORM register numbers to the push parameter index,
 532     * or -1 if this uniform register isn't being uploaded as a push constant.
 533     */
 534    int *push_constant_loc;
 535
 536    struct hash_table *variable_ht;
 537    fs_reg frag_depth;
 538    fs_reg sample_mask;
 539    fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
 540    unsigned output_components[BRW_MAX_DRAW_BUFFERS];
 541    fs_reg dual_src_output;
 542    bool do_dual_src;
 543    int first_non_payload_grf;
 544    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 545    int max_grf;
 546
 547    fs_reg *fp_temp_regs;
 548    fs_reg *fp_input_regs;
 549
 550    /** @{ debug annotation info */
 551    const char *current_annotation;
 552    const void *base_ir;
 553    /** @} */
 554
 555    bool failed;
 556    char *fail_msg;
 557    bool simd16_unsupported;
 558    char *no16_msg;
 559
 560    /* Result of last visit() method. */
 561    fs_reg result;
 562
 563    /** Register numbers for thread payload fields. */
 564    struct {
 565       uint8_t source_depth_reg;
 566       uint8_t source_w_reg;
 567       uint8_t aa_dest_stencil_reg;
 568       uint8_t dest_depth_reg;
 569       uint8_t sample_pos_reg;
 570       uint8_t sample_mask_in_reg;
 571       uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 572
 573       /** The number of thread payload registers the hardware will supply. */
 574       uint8_t num_regs;
 575    } payload;
 576
 577    bool source_depth_to_render_target;
 578    bool runtime_check_aads_emit;
 579
 580    fs_reg pixel_x;
 581    fs_reg pixel_y;
 582    fs_reg wpos_w;
 583    fs_reg pixel_w;
 584    fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 585    fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 586    fs_reg shader_start_time;
 587
 588    int grf_used;
 589    bool spilled_any_registers;
 590
 591    const unsigned dispatch_width; /**< 8 or 16 */
 592
 593    int force_uncompressed_stack;
 594 };
 595
 596 /**
 597  * The fragment shader code generator.
 598  *
 599  * Translates FS IR to actual i965 assembly code.
 600  */
 601 class fs_generator
 602 {
 603 public:
 604    fs_generator(struct brw_context *brw,
 605                 void *mem_ctx,
 606                 const struct brw_wm_prog_key *key,
 607                 struct brw_wm_prog_data *prog_data,
 608                 struct gl_shader_program *prog,
 609                 struct gl_fragment_program *fp,
 610                 bool dual_source_output,
 611                 bool runtime_check_aads_emit,
 612                 bool debug_flag);
 613    ~fs_generator();
 614
 615    const unsigned *generate_assembly(exec_list *simd8_instructions,
 616                                      exec_list *simd16_instructions,
 617                                      unsigned *assembly_size);
 618
 619 private:
 620    void generate_code(exec_list *instructions);
 621    void fire_fb_write(fs_inst *inst,
 622                       GLuint base_reg,
 623                       struct brw_reg implied_header,
 624                       GLuint nr);
 625    void generate_fb_write(fs_inst *inst);
 626    void generate_blorp_fb_write(fs_inst *inst);
 627    void generate_pixel_xy(struct brw_reg dst, bool is_x);
 628    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 629                          struct brw_reg *src);
 630    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 631    void generate_math_gen6(fs_inst *inst,
 632                            struct brw_reg dst,
 633                            struct brw_reg src0,
 634                            struct brw_reg src1);
 635    void generate_math_gen4(fs_inst *inst,
 636                            struct brw_reg dst,
 637                            struct brw_reg src);
 638    void generate_math_g45(fs_inst *inst,
 639                           struct brw_reg dst,
 640                           struct brw_reg src);
 641    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 642    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 643                      bool negate_value);
 644    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 645    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 646    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 647    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 648                                             struct brw_reg index,
 649                                             struct brw_reg offset);
 650    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 651                                                  struct brw_reg dst,
 652                                                  struct brw_reg surf_index,
 653                                                  struct brw_reg offset);
 654    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 655                                             struct brw_reg index,
 656                                             struct brw_reg offset);
 657    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 658                                                  struct brw_reg dst,
 659                                                  struct brw_reg index,
 660                                                  struct brw_reg offset);
 661    void generate_mov_dispatch_to_flags(fs_inst *inst);
 662
 663    void generate_set_omask(fs_inst *inst,
 664                            struct brw_reg dst,
 665                            struct brw_reg sample_mask);
 666
 667    void generate_set_sample_id(fs_inst *inst,
 668                                struct brw_reg dst,
 669                                struct brw_reg src0,
 670                                struct brw_reg src1);
 671
 672    void generate_set_simd4x2_offset(fs_inst *inst,
 673                                     struct brw_reg dst,
 674                                     struct brw_reg offset);
 675    void generate_discard_jump(fs_inst *inst);
 676
 677    void generate_pack_half_2x16_split(fs_inst *inst,
 678                                       struct brw_reg dst,
 679                                       struct brw_reg x,
 680                                       struct brw_reg y);
 681    void generate_unpack_half_2x16_split(fs_inst *inst,
 682                                         struct brw_reg dst,
 683                                         struct brw_reg src);
 684
 685    void generate_shader_time_add(fs_inst *inst,
 686                                  struct brw_reg payload,
 687                                  struct brw_reg offset,
 688                                  struct brw_reg value);
 689
 690    void generate_untyped_atomic(fs_inst *inst,
 691                                 struct brw_reg dst,
 692                                 struct brw_reg atomic_op,
 693                                 struct brw_reg surf_index);
 694
 695    void generate_untyped_surface_read(fs_inst *inst,
 696                                       struct brw_reg dst,
 697                                       struct brw_reg surf_index);
 698
 699    bool patch_discard_jumps_to_fb_writes();
 700
 701    struct brw_context *brw;
 702    struct gl_context *ctx;
 703
 704    struct brw_compile *p;
 705    const struct brw_wm_prog_key *const key;
 706    struct brw_wm_prog_data *prog_data;
 707
 708    struct gl_shader_program *prog;
 709    const struct gl_fragment_program *fp;
 710
 711    unsigned dispatch_width; /**< 8 or 16 */
 712
 713    exec_list discard_halt_patches;
 714    bool dual_source_output;
 715    bool runtime_check_aads_emit;
 716    const bool debug_flag;
 717    void *mem_ctx;
 718 };
 719
 720 /**
 721  * The fragment shader code generator.
 722  *
 723  * Translates FS IR to actual i965 assembly code.
 724  */
 725 class gen8_fs_generator : public gen8_generator
 726 {
 727 public:
 728    gen8_fs_generator(struct brw_context *brw,
 729                      void *mem_ctx,
 730                      const struct brw_wm_prog_key *key,
 731                      struct brw_wm_prog_data *prog_data,
 732                      struct gl_shader_program *prog,
 733                      struct gl_fragment_program *fp,
 734                      bool dual_source_output);
 735    ~gen8_fs_generator();
 736
 737    const unsigned *generate_assembly(exec_list *simd8_instructions,
 738                                      exec_list *simd16_instructions,
 739                                      unsigned *assembly_size);
 740
 741 private:
 742    void generate_code(exec_list *instructions);
 743    void generate_fb_write(fs_inst *inst);
 744    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 745                          struct brw_reg *src);
 746    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 747    void generate_math1(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 748    void generate_math2(fs_inst *inst, struct brw_reg dst,
 749                        struct brw_reg src0, struct brw_reg src1);
 750    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 751    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 752                      bool negate_value);
 753    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 754    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 755    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 756    void generate_uniform_pull_constant_load(fs_inst *inst,
 757                                             struct brw_reg dst,
 758                                             struct brw_reg index,
 759                                             struct brw_reg offset);
 760    void generate_varying_pull_constant_load(fs_inst *inst,
 761                                             struct brw_reg dst,
 762                                             struct brw_reg index,
 763                                             struct brw_reg offset);
 764    void generate_mov_dispatch_to_flags(fs_inst *ir);
 765    void generate_set_omask(fs_inst *ir,
 766                            struct brw_reg dst,
 767                            struct brw_reg sample_mask);
 768    void generate_set_sample_id(fs_inst *ir,
 769                                struct brw_reg dst,
 770                                struct brw_reg src0,
 771                                struct brw_reg src1);
 772    void generate_set_simd4x2_offset(fs_inst *ir,
 773                                     struct brw_reg dst,
 774                                     struct brw_reg offset);
 775    void generate_pack_half_2x16_split(fs_inst *inst,
 776                                       struct brw_reg dst,
 777                                       struct brw_reg x,
 778                                       struct brw_reg y);
 779    void generate_unpack_half_2x16_split(fs_inst *inst,
 780                                         struct brw_reg dst,
 781                                         struct brw_reg src);
 782    void generate_untyped_atomic(fs_inst *inst,
 783                                 struct brw_reg dst,
 784                                 struct brw_reg atomic_op,
 785                                 struct brw_reg surf_index);
 786
 787    void generate_untyped_surface_read(fs_inst *inst,
 788                                       struct brw_reg dst,
 789                                       struct brw_reg surf_index);
 790    void generate_discard_jump(fs_inst *ir);
 791
 792    bool patch_discard_jumps_to_fb_writes();
 793
 794    const struct brw_wm_prog_key *const key;
 795    struct brw_wm_prog_data *prog_data;
 796    const struct gl_fragment_program *fp;
 797
 798    unsigned dispatch_width; /** 8 or 16 */
 799
 800    bool dual_source_output;
 801
 802    exec_list discard_halt_patches;
 803 };
 804
 805 bool brw_do_channel_expressions(struct exec_list *instructions);
 806 bool brw_do_vector_splitting(struct exec_list *instructions);
 807 bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);
 808
 809 struct brw_reg brw_reg_from_fs_reg(fs_reg *reg);