i965: Share the register file enum between the two backends.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs.h
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #pragma once
29
30 #include "brw_shader.h"
31
32 extern "C" {
33
34 #include <sys/types.h>
35
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/uniforms.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/prog_optimize.h"
42 #include "program/register_allocate.h"
43 #include "program/sampler.h"
44 #include "program/hash_table.h"
45 #include "brw_context.h"
46 #include "brw_eu.h"
47 #include "brw_wm.h"
48 #include "brw_shader.h"
49 }
50 #include "glsl/glsl_types.h"
51 #include "glsl/ir.h"
52
53 class bblock_t;
54 namespace {
55 struct acp_entry;
56 }
57
58 class fs_reg {
59 public:
60 /* Callers of this ralloc-based new need not call delete. It's
61 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
62 static void* operator new(size_t size, void *ctx)
63 {
64 void *node;
65
66 node = ralloc_size(ctx, size);
67 assert(node != NULL);
68
69 return node;
70 }
71
72 void init();
73
74 fs_reg();
75 fs_reg(float f);
76 fs_reg(int32_t i);
77 fs_reg(uint32_t u);
78 fs_reg(struct brw_reg fixed_hw_reg);
79 fs_reg(enum register_file file, int reg);
80 fs_reg(enum register_file file, int reg, uint32_t type);
81 fs_reg(class fs_visitor *v, const struct glsl_type *type);
82
83 bool equals(const fs_reg &r) const;
84 bool is_zero() const;
85 bool is_one() const;
86 bool is_valid_3src() const;
87
88 /** Register file: ARF, GRF, MRF, IMM. */
89 enum register_file file;
90 /**
91 * Register number. For ARF/MRF, it's the hardware register. For
92 * GRF, it's a virtual register number until register allocation
93 */
94 int reg;
95 /**
96 * For virtual registers, this is a hardware register offset from
97 * the start of the register block (for example, a constant index
98 * in an array access).
99 */
100 int reg_offset;
101 /** Register type. BRW_REGISTER_TYPE_* */
102 int type;
103 bool negate;
104 bool abs;
105 bool sechalf;
106 struct brw_reg fixed_hw_reg;
107 int smear; /* -1, or a channel of the reg to smear to all channels. */
108
109 /** Value for file == IMM */
110 union {
111 int32_t i;
112 uint32_t u;
113 float f;
114 } imm;
115
116 fs_reg *reladdr;
117 };
118
119 static const fs_reg reg_undef;
120 static const fs_reg reg_null_f(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_F);
121 static const fs_reg reg_null_d(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_D);
122
123 class ip_record : public exec_node {
124 public:
125 static void* operator new(size_t size, void *ctx)
126 {
127 void *node;
128
129 node = rzalloc_size(ctx, size);
130 assert(node != NULL);
131
132 return node;
133 }
134
135 ip_record(int ip)
136 {
137 this->ip = ip;
138 }
139
140 int ip;
141 };
142
143 class fs_inst : public backend_instruction {
144 public:
145 /* Callers of this ralloc-based new need not call delete. It's
146 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
147 static void* operator new(size_t size, void *ctx)
148 {
149 void *node;
150
151 node = rzalloc_size(ctx, size);
152 assert(node != NULL);
153
154 return node;
155 }
156
157 void init();
158
159 fs_inst();
160 fs_inst(enum opcode opcode);
161 fs_inst(enum opcode opcode, fs_reg dst);
162 fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0);
163 fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
164 fs_inst(enum opcode opcode, fs_reg dst,
165 fs_reg src0, fs_reg src1,fs_reg src2);
166
167 bool equals(fs_inst *inst);
168 bool overwrites_reg(const fs_reg &reg);
169 bool is_send_from_grf();
170 bool is_partial_write();
171
172 fs_reg dst;
173 fs_reg src[3];
174 bool saturate;
175 int conditional_mod; /**< BRW_CONDITIONAL_* */
176
177 /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
178 * mod and predication.
179 */
180 uint8_t flag_subreg;
181
182 int mlen; /**< SEND message length */
183 int regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
184 int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
185 uint32_t texture_offset; /**< Texture offset bitfield */
186 int sampler;
187 int target; /**< MRT target. */
188 bool eot;
189 bool header_present;
190 bool shadow_compare;
191 bool force_uncompressed;
192 bool force_sechalf;
193 bool force_writemask_all;
194 uint32_t offset; /* spill/unspill offset */
195
196 /** @{
197 * Annotation for the generated IR. One of the two can be set.
198 */
199 const void *ir;
200 const char *annotation;
201 /** @} */
202 };
203
204 /**
205 * The fragment shader front-end.
206 *
207 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
208 */
209 class fs_visitor : public backend_visitor
210 {
211 public:
212
213 fs_visitor(struct brw_context *brw,
214 struct brw_wm_compile *c,
215 struct gl_shader_program *shader_prog,
216 struct gl_fragment_program *fp,
217 unsigned dispatch_width);
218 ~fs_visitor();
219
220 fs_reg *variable_storage(ir_variable *var);
221 int virtual_grf_alloc(int size);
222 void import_uniforms(fs_visitor *v);
223
224 void visit(ir_variable *ir);
225 void visit(ir_assignment *ir);
226 void visit(ir_dereference_variable *ir);
227 void visit(ir_dereference_record *ir);
228 void visit(ir_dereference_array *ir);
229 void visit(ir_expression *ir);
230 void visit(ir_texture *ir);
231 void visit(ir_if *ir);
232 void visit(ir_constant *ir);
233 void visit(ir_swizzle *ir);
234 void visit(ir_return *ir);
235 void visit(ir_loop *ir);
236 void visit(ir_loop_jump *ir);
237 void visit(ir_discard *ir);
238 void visit(ir_call *ir);
239 void visit(ir_function *ir);
240 void visit(ir_function_signature *ir);
241
242 void swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler);
243
244 bool can_do_source_mods(fs_inst *inst);
245
246 fs_inst *emit(fs_inst inst);
247 fs_inst *emit(fs_inst *inst);
248 void emit(exec_list list);
249
250 fs_inst *emit(enum opcode opcode);
251 fs_inst *emit(enum opcode opcode, fs_reg dst);
252 fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0);
253 fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
254 fs_inst *emit(enum opcode opcode, fs_reg dst,
255 fs_reg src0, fs_reg src1, fs_reg src2);
256
257 fs_inst *MOV(fs_reg dst, fs_reg src);
258 fs_inst *NOT(fs_reg dst, fs_reg src);
259 fs_inst *RNDD(fs_reg dst, fs_reg src);
260 fs_inst *RNDE(fs_reg dst, fs_reg src);
261 fs_inst *RNDZ(fs_reg dst, fs_reg src);
262 fs_inst *FRC(fs_reg dst, fs_reg src);
263 fs_inst *ADD(fs_reg dst, fs_reg src0, fs_reg src1);
264 fs_inst *MUL(fs_reg dst, fs_reg src0, fs_reg src1);
265 fs_inst *MACH(fs_reg dst, fs_reg src0, fs_reg src1);
266 fs_inst *MAC(fs_reg dst, fs_reg src0, fs_reg src1);
267 fs_inst *SHL(fs_reg dst, fs_reg src0, fs_reg src1);
268 fs_inst *SHR(fs_reg dst, fs_reg src0, fs_reg src1);
269 fs_inst *ASR(fs_reg dst, fs_reg src0, fs_reg src1);
270 fs_inst *AND(fs_reg dst, fs_reg src0, fs_reg src1);
271 fs_inst *OR(fs_reg dst, fs_reg src0, fs_reg src1);
272 fs_inst *XOR(fs_reg dst, fs_reg src0, fs_reg src1);
273 fs_inst *IF(uint32_t predicate);
274 fs_inst *IF(fs_reg src0, fs_reg src1, uint32_t condition);
275 fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
276 uint32_t condition);
277 fs_inst *LRP(fs_reg dst, fs_reg a, fs_reg y, fs_reg x);
278 fs_inst *DEP_RESOLVE_MOV(int grf);
279
280 int type_size(const struct glsl_type *type);
281 fs_inst *get_instruction_generating_reg(fs_inst *start,
282 fs_inst *end,
283 fs_reg reg);
284
285 exec_list VARYING_PULL_CONSTANT_LOAD(fs_reg dst, fs_reg surf_index,
286 fs_reg varying_offset,
287 uint32_t const_offset);
288
289 bool run();
290 void setup_payload_gen4();
291 void setup_payload_gen6();
292 void assign_curb_setup();
293 void calculate_urb_setup();
294 void assign_urb_setup();
295 bool assign_regs();
296 void assign_regs_trivial();
297 void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
298 int first_payload_node);
299 void setup_mrf_hack_interference(struct ra_graph *g,
300 int first_mrf_hack_node);
301 int choose_spill_reg(struct ra_graph *g);
302 void spill_reg(int spill_reg);
303 void split_virtual_grfs();
304 void compact_virtual_grfs();
305 void move_uniform_array_access_to_pull_constants();
306 void setup_pull_constants();
307 void calculate_live_intervals();
308 bool opt_algebraic();
309 bool opt_cse();
310 bool opt_cse_local(bblock_t *block, exec_list *aeb);
311 bool opt_copy_propagate();
312 bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
313 bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
314 bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
315 exec_list *acp);
316 bool register_coalesce();
317 bool register_coalesce_2();
318 bool compute_to_mrf();
319 bool dead_code_eliminate();
320 bool dead_code_eliminate_local();
321 bool remove_dead_constants();
322 bool remove_duplicate_mrf_writes();
323 bool virtual_grf_interferes(int a, int b);
324 void schedule_instructions(bool post_reg_alloc);
325 void insert_gen4_send_dependency_workarounds();
326 void insert_gen4_pre_send_dependency_workarounds(fs_inst *inst);
327 void insert_gen4_post_send_dependency_workarounds(fs_inst *inst);
328 void fail(const char *msg, ...);
329 void lower_uniform_pull_constant_loads();
330
331 void push_force_uncompressed();
332 void pop_force_uncompressed();
333 void push_force_sechalf();
334 void pop_force_sechalf();
335
336 void emit_dummy_fs();
337 fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
338 fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
339 glsl_interp_qualifier interpolation_mode,
340 bool is_centroid);
341 fs_reg *emit_frontfacing_interpolation(ir_variable *ir);
342 fs_reg *emit_general_interpolation(ir_variable *ir);
343 void emit_interpolation_setup_gen4();
344 void emit_interpolation_setup_gen6();
345 fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
346 bool is_rect, int sampler, int texunit);
347 fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
348 fs_reg shadow_comp, fs_reg lod, fs_reg lod2);
349 fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
350 fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
351 fs_reg sample_index);
352 fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
353 fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
354 fs_reg sample_index);
355 fs_reg fix_math_operand(fs_reg src);
356 fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
357 fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
358 void emit_lrp(fs_reg dst, fs_reg x, fs_reg y, fs_reg a);
359 void emit_minmax(uint32_t conditionalmod, fs_reg dst,
360 fs_reg src0, fs_reg src1);
361 bool try_emit_saturate(ir_expression *ir);
362 bool try_emit_mad(ir_expression *ir, int mul_arg);
363 void emit_bool_to_cond_code(ir_rvalue *condition);
364 void emit_if_gen6(ir_if *ir);
365 void emit_unspill(fs_inst *inst, fs_reg reg, uint32_t spill_offset);
366
367 void emit_fragment_program_code();
368 void setup_fp_regs();
369 fs_reg get_fp_src_reg(const prog_src_register *src);
370 fs_reg get_fp_dst_reg(const prog_dst_register *dst);
371 void emit_fp_alu1(enum opcode opcode,
372 const struct prog_instruction *fpi,
373 fs_reg dst, fs_reg src);
374 void emit_fp_alu2(enum opcode opcode,
375 const struct prog_instruction *fpi,
376 fs_reg dst, fs_reg src0, fs_reg src1);
377 void emit_fp_scalar_write(const struct prog_instruction *fpi,
378 fs_reg dst, fs_reg src);
379 void emit_fp_scalar_math(enum opcode opcode,
380 const struct prog_instruction *fpi,
381 fs_reg dst, fs_reg src);
382
383 void emit_fp_minmax(const struct prog_instruction *fpi,
384 fs_reg dst, fs_reg src0, fs_reg src1);
385
386 void emit_fp_sop(uint32_t conditional_mod,
387 const struct prog_instruction *fpi,
388 fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
389
390 void emit_color_write(int target, int index, int first_color_mrf);
391 void emit_fb_writes();
392
393 void emit_shader_time_begin();
394 void emit_shader_time_end();
395 void emit_shader_time_write(enum shader_time_shader_type type,
396 fs_reg value);
397
398 bool try_rewrite_rhs_to_dst(ir_assignment *ir,
399 fs_reg dst,
400 fs_reg src,
401 fs_inst *pre_rhs_inst,
402 fs_inst *last_rhs_inst);
403 void emit_assignment_writes(fs_reg &l, fs_reg &r,
404 const glsl_type *type, bool predicated);
405 void resolve_ud_negate(fs_reg *reg);
406 void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
407
408 fs_reg get_timestamp();
409
410 struct brw_reg interp_reg(int location, int channel);
411 void setup_uniform_values(ir_variable *ir);
412 void setup_builtin_uniform_values(ir_variable *ir);
413 int implied_mrf_writes(fs_inst *inst);
414
415 void dump_instruction(backend_instruction *inst);
416
417 struct gl_fragment_program *fp;
418 struct brw_wm_compile *c;
419 unsigned int sanity_param_count;
420
421 int param_size[MAX_UNIFORMS * 4];
422
423 int *virtual_grf_sizes;
424 int virtual_grf_count;
425 int virtual_grf_array_size;
426 int *virtual_grf_def;
427 int *virtual_grf_use;
428 bool live_intervals_valid;
429
430 /* This is the map from UNIFORM hw_reg + reg_offset as generated by
431 * the visitor to the packed uniform number after
432 * remove_dead_constants() that represents the actual uploaded
433 * uniform index.
434 */
435 int *params_remap;
436
437 struct hash_table *variable_ht;
438 fs_reg frag_depth;
439 fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
440 unsigned output_components[BRW_MAX_DRAW_BUFFERS];
441 fs_reg dual_src_output;
442 int first_non_payload_grf;
443 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
444 int max_grf;
445 int urb_setup[VARYING_SLOT_MAX];
446
447 fs_reg *fp_temp_regs;
448 fs_reg *fp_input_regs;
449
450 /** @{ debug annotation info */
451 const char *current_annotation;
452 const void *base_ir;
453 /** @} */
454
455 bool failed;
456 char *fail_msg;
457
458 /* Result of last visit() method. */
459 fs_reg result;
460
461 fs_reg pixel_x;
462 fs_reg pixel_y;
463 fs_reg wpos_w;
464 fs_reg pixel_w;
465 fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
466 fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
467 fs_reg shader_start_time;
468
469 int grf_used;
470
471 const unsigned dispatch_width; /**< 8 or 16 */
472
473 int force_uncompressed_stack;
474 int force_sechalf_stack;
475 };
476
477 /**
478 * The fragment shader code generator.
479 *
480 * Translates FS IR to actual i965 assembly code.
481 */
482 class fs_generator
483 {
484 public:
485 fs_generator(struct brw_context *brw,
486 struct brw_wm_compile *c,
487 struct gl_shader_program *prog,
488 struct gl_fragment_program *fp,
489 bool dual_source_output);
490 ~fs_generator();
491
492 const unsigned *generate_assembly(exec_list *simd8_instructions,
493 exec_list *simd16_instructions,
494 unsigned *assembly_size);
495
496 private:
497 void generate_code(exec_list *instructions);
498 void generate_fb_write(fs_inst *inst);
499 void generate_pixel_xy(struct brw_reg dst, bool is_x);
500 void generate_linterp(fs_inst *inst, struct brw_reg dst,
501 struct brw_reg *src);
502 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
503 void generate_math1_gen7(fs_inst *inst,
504 struct brw_reg dst,
505 struct brw_reg src);
506 void generate_math2_gen7(fs_inst *inst,
507 struct brw_reg dst,
508 struct brw_reg src0,
509 struct brw_reg src1);
510 void generate_math1_gen6(fs_inst *inst,
511 struct brw_reg dst,
512 struct brw_reg src);
513 void generate_math2_gen6(fs_inst *inst,
514 struct brw_reg dst,
515 struct brw_reg src0,
516 struct brw_reg src1);
517 void generate_math_gen4(fs_inst *inst,
518 struct brw_reg dst,
519 struct brw_reg src);
520 void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
521 void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
522 bool negate_value);
523 void generate_spill(fs_inst *inst, struct brw_reg src);
524 void generate_unspill(fs_inst *inst, struct brw_reg dst);
525 void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
526 struct brw_reg index,
527 struct brw_reg offset);
528 void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
529 struct brw_reg dst,
530 struct brw_reg surf_index,
531 struct brw_reg offset);
532 void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
533 struct brw_reg index,
534 struct brw_reg offset);
535 void generate_varying_pull_constant_load_gen7(fs_inst *inst,
536 struct brw_reg dst,
537 struct brw_reg index,
538 struct brw_reg offset);
539 void generate_mov_dispatch_to_flags(fs_inst *inst);
540 void generate_set_simd4x2_offset(fs_inst *inst,
541 struct brw_reg dst,
542 struct brw_reg offset);
543 void generate_discard_jump(fs_inst *inst);
544
545 void generate_pack_half_2x16_split(fs_inst *inst,
546 struct brw_reg dst,
547 struct brw_reg x,
548 struct brw_reg y);
549 void generate_unpack_half_2x16_split(fs_inst *inst,
550 struct brw_reg dst,
551 struct brw_reg src);
552
553 void generate_shader_time_add(fs_inst *inst,
554 struct brw_reg payload,
555 struct brw_reg offset,
556 struct brw_reg value);
557
558 void patch_discard_jumps_to_fb_writes();
559
560 struct brw_context *brw;
561 struct intel_context *intel;
562 struct gl_context *ctx;
563
564 struct brw_compile *p;
565 struct brw_wm_compile *c;
566
567 struct gl_shader_program *prog;
568 struct gl_shader *shader;
569 const struct gl_fragment_program *fp;
570
571 unsigned dispatch_width; /**< 8 or 16 */
572
573 exec_list discard_halt_patches;
574 bool dual_source_output;
575 void *mem_ctx;
576 };
577
578 bool brw_do_channel_expressions(struct exec_list *instructions);
579 bool brw_do_vector_splitting(struct exec_list *instructions);
580 bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);