2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include "brw_shader.h"
34 #include <sys/types.h>
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/uniforms.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/prog_optimize.h"
42 #include "program/register_allocate.h"
43 #include "program/sampler.h"
44 #include "program/hash_table.h"
45 #include "brw_context.h"
48 #include "brw_shader.h"
49 #include "intel_asm_printer.h"
51 #include "gen8_generator.h"
52 #include "glsl/glsl_types.h"
55 #define MAX_SAMPLER_MESSAGE_SIZE 11
63 class fs_live_variables
;
68 DECLARE_RALLOC_CXX_OPERATORS(fs_reg
)
76 fs_reg(struct brw_reg fixed_hw_reg
);
77 fs_reg(enum register_file file
, int reg
);
78 fs_reg(enum register_file file
, int reg
, uint32_t type
);
79 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
81 bool equals(const fs_reg
&r
) const;
85 bool is_valid_3src() const;
86 bool is_contiguous() const;
87 bool is_accumulator() const;
89 fs_reg
&apply_stride(unsigned stride
);
90 /** Smear a channel of the reg to all channels. */
91 fs_reg
&set_smear(unsigned subreg
);
93 /** Register file: GRF, MRF, IMM. */
94 enum register_file file
;
95 /** Register type. BRW_REGISTER_TYPE_* */
98 * Register number. For MRF, it's the hardware register. For
99 * GRF, it's a virtual register number until register allocation
103 * Offset from the start of the contiguous register block.
105 * For pre-register-allocation GRFs, this is in units of a float per pixel
106 * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
107 * For uniforms, this is in units of 1 float.
111 * Offset in bytes from the start of the register. Values up to a
112 * backend_reg::reg_offset unit are valid.
116 /** Value for file == IMM */
123 struct brw_reg fixed_hw_reg
;
130 /** Register region horizontal stride */
135 retype(fs_reg reg
, unsigned type
)
137 reg
.fixed_hw_reg
.type
= reg
.type
= type
;
142 offset(fs_reg reg
, unsigned delta
)
144 assert(delta
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
145 reg
.reg_offset
+= delta
;
150 byte_offset(fs_reg reg
, unsigned delta
)
152 assert(delta
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
153 reg
.subreg_offset
+= delta
;
158 * Get either of the 8-component halves of a 16-component register.
160 * Note: this also works if \c reg represents a SIMD16 pair of registers.
163 half(const fs_reg
®
, unsigned idx
)
166 assert(idx
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
167 return byte_offset(reg
, 8 * idx
* reg
.stride
* type_sz(reg
.type
));
170 static const fs_reg reg_undef
;
171 static const fs_reg
reg_null_f(retype(brw_null_reg(), BRW_REGISTER_TYPE_F
));
172 static const fs_reg
reg_null_d(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
173 static const fs_reg
reg_null_ud(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
175 class ip_record
: public exec_node
{
177 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
187 class fs_inst
: public backend_instruction
{
189 DECLARE_RALLOC_CXX_OPERATORS(fs_inst
)
194 fs_inst(enum opcode opcode
);
195 fs_inst(enum opcode opcode
, fs_reg dst
);
196 fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
);
197 fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
198 fs_inst(enum opcode opcode
, fs_reg dst
,
199 fs_reg src0
, fs_reg src1
,fs_reg src2
);
201 bool equals(fs_inst
*inst
) const;
202 bool overwrites_reg(const fs_reg
®
) const;
203 bool is_send_from_grf() const;
204 bool is_partial_write() const;
205 int regs_read(fs_visitor
*v
, int arg
) const;
207 bool reads_flag() const;
208 bool writes_flag() const;
213 uint32_t texture_offset
; /**< Texture offset bitfield */
214 uint32_t offset
; /* spill/unspill offset */
216 uint8_t conditional_mod
; /**< BRW_CONDITIONAL_* */
218 /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
219 * mod and predication.
223 uint8_t mlen
; /**< SEND message length */
224 uint8_t regs_written
; /**< Number of vgrfs written by a SEND message, or 1 */
225 int8_t base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
227 uint8_t target
; /**< MRT target. */
230 bool header_present
:1;
231 bool shadow_compare
:1;
232 bool force_uncompressed
:1;
233 bool force_sechalf
:1;
234 bool force_writemask_all
:1;
238 * The fragment shader front-end.
240 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
242 class fs_visitor
: public backend_visitor
246 fs_visitor(struct brw_context
*brw
,
248 const struct brw_wm_prog_key
*key
,
249 struct brw_wm_prog_data
*prog_data
,
250 struct gl_shader_program
*shader_prog
,
251 struct gl_fragment_program
*fp
,
252 unsigned dispatch_width
);
255 fs_reg
*variable_storage(ir_variable
*var
);
256 int virtual_grf_alloc(int size
);
257 void import_uniforms(fs_visitor
*v
);
259 void visit(ir_variable
*ir
);
260 void visit(ir_assignment
*ir
);
261 void visit(ir_dereference_variable
*ir
);
262 void visit(ir_dereference_record
*ir
);
263 void visit(ir_dereference_array
*ir
);
264 void visit(ir_expression
*ir
);
265 void visit(ir_texture
*ir
);
266 void visit(ir_if
*ir
);
267 void visit(ir_constant
*ir
);
268 void visit(ir_swizzle
*ir
);
269 void visit(ir_return
*ir
);
270 void visit(ir_loop
*ir
);
271 void visit(ir_loop_jump
*ir
);
272 void visit(ir_discard
*ir
);
273 void visit(ir_call
*ir
);
274 void visit(ir_function
*ir
);
275 void visit(ir_function_signature
*ir
);
276 void visit(ir_emit_vertex
*);
277 void visit(ir_end_primitive
*);
279 uint32_t gather_channel(ir_texture
*ir
, int sampler
);
280 void swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
);
282 bool can_do_source_mods(fs_inst
*inst
);
284 fs_inst
*emit(fs_inst
*inst
);
285 void emit(exec_list list
);
287 fs_inst
*emit(enum opcode opcode
);
288 fs_inst
*emit(enum opcode opcode
, fs_reg dst
);
289 fs_inst
*emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
);
290 fs_inst
*emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
291 fs_inst
*emit(enum opcode opcode
, fs_reg dst
,
292 fs_reg src0
, fs_reg src1
, fs_reg src2
);
294 fs_inst
*MOV(fs_reg dst
, fs_reg src
);
295 fs_inst
*NOT(fs_reg dst
, fs_reg src
);
296 fs_inst
*RNDD(fs_reg dst
, fs_reg src
);
297 fs_inst
*RNDE(fs_reg dst
, fs_reg src
);
298 fs_inst
*RNDZ(fs_reg dst
, fs_reg src
);
299 fs_inst
*FRC(fs_reg dst
, fs_reg src
);
300 fs_inst
*ADD(fs_reg dst
, fs_reg src0
, fs_reg src1
);
301 fs_inst
*MUL(fs_reg dst
, fs_reg src0
, fs_reg src1
);
302 fs_inst
*MACH(fs_reg dst
, fs_reg src0
, fs_reg src1
);
303 fs_inst
*MAC(fs_reg dst
, fs_reg src0
, fs_reg src1
);
304 fs_inst
*SHL(fs_reg dst
, fs_reg src0
, fs_reg src1
);
305 fs_inst
*SHR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
306 fs_inst
*ASR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
307 fs_inst
*AND(fs_reg dst
, fs_reg src0
, fs_reg src1
);
308 fs_inst
*OR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
309 fs_inst
*XOR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
310 fs_inst
*IF(uint32_t predicate
);
311 fs_inst
*IF(fs_reg src0
, fs_reg src1
, uint32_t condition
);
312 fs_inst
*CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
,
314 fs_inst
*LRP(fs_reg dst
, fs_reg a
, fs_reg y
, fs_reg x
);
315 fs_inst
*DEP_RESOLVE_MOV(int grf
);
316 fs_inst
*BFREV(fs_reg dst
, fs_reg value
);
317 fs_inst
*BFE(fs_reg dst
, fs_reg bits
, fs_reg offset
, fs_reg value
);
318 fs_inst
*BFI1(fs_reg dst
, fs_reg bits
, fs_reg offset
);
319 fs_inst
*BFI2(fs_reg dst
, fs_reg bfi1_dst
, fs_reg insert
, fs_reg base
);
320 fs_inst
*FBH(fs_reg dst
, fs_reg value
);
321 fs_inst
*FBL(fs_reg dst
, fs_reg value
);
322 fs_inst
*CBIT(fs_reg dst
, fs_reg value
);
323 fs_inst
*MAD(fs_reg dst
, fs_reg c
, fs_reg b
, fs_reg a
);
324 fs_inst
*ADDC(fs_reg dst
, fs_reg src0
, fs_reg src1
);
325 fs_inst
*SUBB(fs_reg dst
, fs_reg src0
, fs_reg src1
);
326 fs_inst
*SEL(fs_reg dst
, fs_reg src0
, fs_reg src1
);
328 int type_size(const struct glsl_type
*type
);
329 fs_inst
*get_instruction_generating_reg(fs_inst
*start
,
333 exec_list
VARYING_PULL_CONSTANT_LOAD(const fs_reg
&dst
,
334 const fs_reg
&surf_index
,
335 const fs_reg
&varying_offset
,
336 uint32_t const_offset
);
339 void assign_binding_table_offsets();
340 void setup_payload_gen4();
341 void setup_payload_gen6();
342 void assign_curb_setup();
343 void calculate_urb_setup();
344 void assign_urb_setup();
345 bool assign_regs(bool allow_spilling
);
346 void assign_regs_trivial();
347 void get_used_mrfs(bool *mrf_used
);
348 void setup_payload_interference(struct ra_graph
*g
, int payload_reg_count
,
349 int first_payload_node
);
350 void setup_mrf_hack_interference(struct ra_graph
*g
,
351 int first_mrf_hack_node
);
352 int choose_spill_reg(struct ra_graph
*g
);
353 void spill_reg(int spill_reg
);
354 void split_virtual_grfs();
355 void compact_virtual_grfs();
356 void move_uniform_array_access_to_pull_constants();
357 void assign_constant_locations();
358 void demote_pull_constants();
359 void invalidate_live_intervals();
360 void calculate_live_intervals();
361 void calculate_register_pressure();
362 bool opt_algebraic();
364 bool opt_cse_local(bblock_t
*block
, exec_list
*aeb
);
365 bool opt_copy_propagate();
366 bool try_copy_propagate(fs_inst
*inst
, int arg
, acp_entry
*entry
);
367 bool try_constant_propagate(fs_inst
*inst
, acp_entry
*entry
);
368 bool opt_copy_propagate_local(void *mem_ctx
, bblock_t
*block
,
370 void opt_drop_redundant_mov_to_flags();
371 bool register_coalesce();
372 bool compute_to_mrf();
373 bool dead_code_eliminate();
374 bool remove_duplicate_mrf_writes();
375 bool virtual_grf_interferes(int a
, int b
);
376 void schedule_instructions(instruction_scheduler_mode mode
);
377 void insert_gen4_send_dependency_workarounds();
378 void insert_gen4_pre_send_dependency_workarounds(fs_inst
*inst
);
379 void insert_gen4_post_send_dependency_workarounds(fs_inst
*inst
);
380 void vfail(const char *msg
, va_list args
);
381 void fail(const char *msg
, ...);
382 void no16(const char *msg
, ...);
383 void lower_uniform_pull_constant_loads();
385 void push_force_uncompressed();
386 void pop_force_uncompressed();
388 void emit_dummy_fs();
389 fs_reg
*emit_fragcoord_interpolation(ir_variable
*ir
);
390 fs_inst
*emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
391 glsl_interp_qualifier interpolation_mode
,
392 bool is_centroid
, bool is_sample
);
393 fs_reg
*emit_frontfacing_interpolation(ir_variable
*ir
);
394 fs_reg
*emit_samplepos_setup(ir_variable
*ir
);
395 fs_reg
*emit_sampleid_setup(ir_variable
*ir
);
396 fs_reg
*emit_general_interpolation(ir_variable
*ir
);
397 void emit_interpolation_setup_gen4();
398 void emit_interpolation_setup_gen6();
399 void compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
);
400 fs_reg
rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
401 bool is_rect
, int sampler
, int texunit
);
402 fs_inst
*emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
403 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
);
404 fs_inst
*emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
405 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
,
406 fs_reg sample_index
);
407 fs_inst
*emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
408 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
,
409 fs_reg sample_index
, fs_reg mcs
, int sampler
);
410 fs_reg
emit_mcs_fetch(ir_texture
*ir
, fs_reg coordinate
, int sampler
);
411 void emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
);
412 fs_reg
fix_math_operand(fs_reg src
);
413 fs_inst
*emit_math(enum opcode op
, fs_reg dst
, fs_reg src0
);
414 fs_inst
*emit_math(enum opcode op
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
415 void emit_lrp(const fs_reg
&dst
, const fs_reg
&x
, const fs_reg
&y
,
417 void emit_minmax(uint32_t conditionalmod
, const fs_reg
&dst
,
418 const fs_reg
&src0
, const fs_reg
&src1
);
419 bool try_emit_saturate(ir_expression
*ir
);
420 bool try_emit_mad(ir_expression
*ir
);
421 void try_replace_with_sel();
422 bool opt_peephole_sel();
423 bool opt_peephole_predicated_break();
424 bool opt_saturate_propagation();
425 void emit_bool_to_cond_code(ir_rvalue
*condition
);
426 void emit_if_gen6(ir_if
*ir
);
427 void emit_unspill(fs_inst
*inst
, fs_reg reg
, uint32_t spill_offset
,
430 void emit_fragment_program_code();
431 void setup_fp_regs();
432 fs_reg
get_fp_src_reg(const prog_src_register
*src
);
433 fs_reg
get_fp_dst_reg(const prog_dst_register
*dst
);
434 void emit_fp_alu1(enum opcode opcode
,
435 const struct prog_instruction
*fpi
,
436 fs_reg dst
, fs_reg src
);
437 void emit_fp_alu2(enum opcode opcode
,
438 const struct prog_instruction
*fpi
,
439 fs_reg dst
, fs_reg src0
, fs_reg src1
);
440 void emit_fp_scalar_write(const struct prog_instruction
*fpi
,
441 fs_reg dst
, fs_reg src
);
442 void emit_fp_scalar_math(enum opcode opcode
,
443 const struct prog_instruction
*fpi
,
444 fs_reg dst
, fs_reg src
);
446 void emit_fp_minmax(const struct prog_instruction
*fpi
,
447 fs_reg dst
, fs_reg src0
, fs_reg src1
);
449 void emit_fp_sop(uint32_t conditional_mod
,
450 const struct prog_instruction
*fpi
,
451 fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg one
);
453 void emit_color_write(int target
, int index
, int first_color_mrf
);
454 void emit_alpha_test();
455 void emit_fb_writes();
457 void emit_shader_time_begin();
458 void emit_shader_time_end();
459 void emit_shader_time_write(enum shader_time_shader_type type
,
462 void emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
463 fs_reg dst
, fs_reg offset
, fs_reg src0
,
466 void emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
469 bool try_rewrite_rhs_to_dst(ir_assignment
*ir
,
472 fs_inst
*pre_rhs_inst
,
473 fs_inst
*last_rhs_inst
);
474 void emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
475 const glsl_type
*type
, bool predicated
);
476 void resolve_ud_negate(fs_reg
*reg
);
477 void resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
);
479 fs_reg
get_timestamp();
481 struct brw_reg
interp_reg(int location
, int channel
);
482 void setup_uniform_values(ir_variable
*ir
);
483 void setup_builtin_uniform_values(ir_variable
*ir
);
484 int implied_mrf_writes(fs_inst
*inst
);
486 virtual void dump_instructions();
487 virtual void dump_instructions(const char *name
);
488 void dump_instruction(backend_instruction
*inst
);
489 void dump_instruction(backend_instruction
*inst
, FILE *file
);
491 void visit_atomic_counter_intrinsic(ir_call
*ir
);
493 struct gl_fragment_program
*fp
;
494 const struct brw_wm_prog_key
*const key
;
495 struct brw_wm_prog_data
*prog_data
;
496 unsigned int sanity_param_count
;
500 int *virtual_grf_sizes
;
501 int virtual_grf_count
;
502 int virtual_grf_array_size
;
503 int *virtual_grf_start
;
504 int *virtual_grf_end
;
505 brw::fs_live_variables
*live_intervals
;
507 int *regs_live_at_ip
;
509 /** Number of uniform variable components visited. */
512 /** Byte-offset for the next available spot in the scratch space buffer. */
513 unsigned last_scratch
;
516 * Array mapping UNIFORM register numbers to the pull parameter index,
517 * or -1 if this uniform register isn't being uploaded as a pull constant.
519 int *pull_constant_loc
;
522 * Array mapping UNIFORM register numbers to the push parameter index,
523 * or -1 if this uniform register isn't being uploaded as a push constant.
525 int *push_constant_loc
;
527 struct hash_table
*variable_ht
;
530 fs_reg outputs
[BRW_MAX_DRAW_BUFFERS
];
531 unsigned output_components
[BRW_MAX_DRAW_BUFFERS
];
532 fs_reg dual_src_output
;
534 int first_non_payload_grf
;
535 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
538 fs_reg
*fp_temp_regs
;
539 fs_reg
*fp_input_regs
;
541 /** @{ debug annotation info */
542 const char *current_annotation
;
548 bool simd16_unsupported
;
551 /* Result of last visit() method. */
554 /** Register numbers for thread payload fields. */
556 uint8_t source_depth_reg
;
557 uint8_t source_w_reg
;
558 uint8_t aa_dest_stencil_reg
;
559 uint8_t dest_depth_reg
;
560 uint8_t sample_pos_reg
;
561 uint8_t sample_mask_in_reg
;
562 uint8_t barycentric_coord_reg
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
564 /** The number of thread payload registers the hardware will supply. */
568 bool source_depth_to_render_target
;
569 bool runtime_check_aads_emit
;
575 fs_reg delta_x
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
576 fs_reg delta_y
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
577 fs_reg shader_start_time
;
580 bool spilled_any_registers
;
582 const unsigned dispatch_width
; /**< 8 or 16 */
584 int force_uncompressed_stack
;
588 * The fragment shader code generator.
590 * Translates FS IR to actual i965 assembly code.
595 fs_generator(struct brw_context
*brw
,
597 const struct brw_wm_prog_key
*key
,
598 struct brw_wm_prog_data
*prog_data
,
599 struct gl_shader_program
*prog
,
600 struct gl_fragment_program
*fp
,
601 bool dual_source_output
,
605 const unsigned *generate_assembly(exec_list
*simd8_instructions
,
606 exec_list
*simd16_instructions
,
607 unsigned *assembly_size
);
610 void generate_code(exec_list
*instructions
,
611 struct annotation_info
*annotation
);
612 void generate_fb_write(fs_inst
*inst
);
613 void generate_blorp_fb_write(fs_inst
*inst
);
614 void generate_pixel_xy(struct brw_reg dst
, bool is_x
);
615 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
616 struct brw_reg
*src
);
617 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
618 void generate_math1_gen7(fs_inst
*inst
,
621 void generate_math2_gen7(fs_inst
*inst
,
624 struct brw_reg src1
);
625 void generate_math1_gen6(fs_inst
*inst
,
628 void generate_math2_gen6(fs_inst
*inst
,
631 struct brw_reg src1
);
632 void generate_math_gen4(fs_inst
*inst
,
635 void generate_math_g45(fs_inst
*inst
,
638 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
639 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
641 void generate_scratch_write(fs_inst
*inst
, struct brw_reg src
);
642 void generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
);
643 void generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
);
644 void generate_uniform_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
,
645 struct brw_reg index
,
646 struct brw_reg offset
);
647 void generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
649 struct brw_reg surf_index
,
650 struct brw_reg offset
);
651 void generate_varying_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
,
652 struct brw_reg index
,
653 struct brw_reg offset
);
654 void generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
656 struct brw_reg index
,
657 struct brw_reg offset
);
658 void generate_mov_dispatch_to_flags(fs_inst
*inst
);
660 void generate_set_omask(fs_inst
*inst
,
662 struct brw_reg sample_mask
);
664 void generate_set_sample_id(fs_inst
*inst
,
667 struct brw_reg src1
);
669 void generate_set_simd4x2_offset(fs_inst
*inst
,
671 struct brw_reg offset
);
672 void generate_discard_jump(fs_inst
*inst
);
674 void generate_pack_half_2x16_split(fs_inst
*inst
,
678 void generate_unpack_half_2x16_split(fs_inst
*inst
,
682 void generate_shader_time_add(fs_inst
*inst
,
683 struct brw_reg payload
,
684 struct brw_reg offset
,
685 struct brw_reg value
);
687 void generate_untyped_atomic(fs_inst
*inst
,
689 struct brw_reg atomic_op
,
690 struct brw_reg surf_index
);
692 void generate_untyped_surface_read(fs_inst
*inst
,
694 struct brw_reg surf_index
);
696 bool patch_discard_jumps_to_fb_writes();
698 struct brw_context
*brw
;
699 struct gl_context
*ctx
;
701 struct brw_compile
*p
;
702 const struct brw_wm_prog_key
*const key
;
703 struct brw_wm_prog_data
*prog_data
;
705 struct gl_shader_program
*prog
;
706 const struct gl_fragment_program
*fp
;
708 unsigned dispatch_width
; /**< 8 or 16 */
710 exec_list discard_halt_patches
;
711 bool dual_source_output
;
712 const bool debug_flag
;
717 * The fragment shader code generator.
719 * Translates FS IR to actual i965 assembly code.
721 class gen8_fs_generator
: public gen8_generator
724 gen8_fs_generator(struct brw_context
*brw
,
726 const struct brw_wm_prog_key
*key
,
727 struct brw_wm_prog_data
*prog_data
,
728 struct gl_shader_program
*prog
,
729 struct gl_fragment_program
*fp
,
730 bool dual_source_output
);
731 ~gen8_fs_generator();
733 const unsigned *generate_assembly(exec_list
*simd8_instructions
,
734 exec_list
*simd16_instructions
,
735 unsigned *assembly_size
);
738 void generate_code(exec_list
*instructions
,
739 struct annotation_info
*annotation
);
740 void generate_fb_write(fs_inst
*inst
);
741 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
742 struct brw_reg
*src
);
743 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
744 void generate_math1(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
745 void generate_math2(fs_inst
*inst
, struct brw_reg dst
,
746 struct brw_reg src0
, struct brw_reg src1
);
747 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
748 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
750 void generate_scratch_write(fs_inst
*inst
, struct brw_reg src
);
751 void generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
);
752 void generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
);
753 void generate_uniform_pull_constant_load(fs_inst
*inst
,
755 struct brw_reg index
,
756 struct brw_reg offset
);
757 void generate_varying_pull_constant_load(fs_inst
*inst
,
759 struct brw_reg index
,
760 struct brw_reg offset
);
761 void generate_mov_dispatch_to_flags(fs_inst
*ir
);
762 void generate_set_omask(fs_inst
*ir
,
764 struct brw_reg sample_mask
);
765 void generate_set_sample_id(fs_inst
*ir
,
768 struct brw_reg src1
);
769 void generate_set_simd4x2_offset(fs_inst
*ir
,
771 struct brw_reg offset
);
772 void generate_pack_half_2x16_split(fs_inst
*inst
,
776 void generate_unpack_half_2x16_split(fs_inst
*inst
,
779 void generate_untyped_atomic(fs_inst
*inst
,
781 struct brw_reg atomic_op
,
782 struct brw_reg surf_index
);
784 void generate_untyped_surface_read(fs_inst
*inst
,
786 struct brw_reg surf_index
);
787 void generate_discard_jump(fs_inst
*ir
);
789 bool patch_discard_jumps_to_fb_writes();
791 const struct brw_wm_prog_key
*const key
;
792 struct brw_wm_prog_data
*prog_data
;
793 const struct gl_fragment_program
*fp
;
795 unsigned dispatch_width
; /** 8 or 16 */
797 bool dual_source_output
;
799 exec_list discard_halt_patches
;
802 bool brw_do_channel_expressions(struct exec_list
*instructions
);
803 bool brw_do_vector_splitting(struct exec_list
*instructions
);
804 bool brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
);
806 struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
);