2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include "brw_shader.h"
34 #include <sys/types.h>
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/uniforms.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/prog_optimize.h"
42 #include "program/register_allocate.h"
43 #include "program/sampler.h"
44 #include "program/hash_table.h"
45 #include "brw_context.h"
48 #include "brw_shader.h"
50 #include "glsl/glsl_types.h"
64 FIXED_HW_REG
, /* a struct brw_reg */
65 UNIFORM
, /* prog_data->params[reg] */
70 /* Callers of this ralloc-based new need not call delete. It's
71 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
72 static void* operator new(size_t size
, void *ctx
)
76 node
= ralloc_size(ctx
, size
);
88 fs_reg(struct brw_reg fixed_hw_reg
);
89 fs_reg(enum register_file file
, int reg
);
90 fs_reg(enum register_file file
, int reg
, uint32_t type
);
91 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
93 bool equals(const fs_reg
&r
) const;
97 /** Register file: ARF, GRF, MRF, IMM. */
98 enum register_file file
;
100 * Register number. For ARF/MRF, it's the hardware register. For
101 * GRF, it's a virtual register number until register allocation
105 * For virtual registers, this is a hardware register offset from
106 * the start of the register block (for example, a constant index
107 * in an array access).
110 /** Register type. BRW_REGISTER_TYPE_* */
115 struct brw_reg fixed_hw_reg
;
116 int smear
; /* -1, or a channel of the reg to smear to all channels. */
118 /** Value for file == IMM */
128 static const fs_reg reg_undef
;
129 static const fs_reg
reg_null_f(ARF
, BRW_ARF_NULL
, BRW_REGISTER_TYPE_F
);
130 static const fs_reg
reg_null_d(ARF
, BRW_ARF_NULL
, BRW_REGISTER_TYPE_D
);
132 class fs_inst
: public backend_instruction
{
134 /* Callers of this ralloc-based new need not call delete. It's
135 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
136 static void* operator new(size_t size
, void *ctx
)
140 node
= rzalloc_size(ctx
, size
);
141 assert(node
!= NULL
);
149 fs_inst(enum opcode opcode
);
150 fs_inst(enum opcode opcode
, fs_reg dst
);
151 fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
);
152 fs_inst(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
153 fs_inst(enum opcode opcode
, fs_reg dst
,
154 fs_reg src0
, fs_reg src1
,fs_reg src2
);
156 bool equals(fs_inst
*inst
);
158 bool overwrites_reg(const fs_reg
®
);
161 bool is_send_from_grf();
166 int conditional_mod
; /**< BRW_CONDITIONAL_* */
168 int mlen
; /**< SEND message length */
169 int base_mrf
; /**< First MRF in the SEND message, if mlen is nonzero. */
170 uint32_t texture_offset
; /**< Texture offset bitfield */
172 int target
; /**< MRT target. */
176 bool force_uncompressed
;
178 bool force_writemask_all
;
179 uint32_t offset
; /* spill/unspill offset */
182 * Annotation for the generated IR. One of the two can be set.
185 const char *annotation
;
190 * The fragment shader front-end.
192 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
194 class fs_visitor
: public backend_visitor
198 fs_visitor(struct brw_context
*brw
,
199 struct brw_wm_compile
*c
,
200 struct gl_shader_program
*prog
,
201 struct gl_fragment_program
*fp
,
202 unsigned dispatch_width
);
205 fs_reg
*variable_storage(ir_variable
*var
);
206 int virtual_grf_alloc(int size
);
207 void import_uniforms(fs_visitor
*v
);
209 void visit(ir_variable
*ir
);
210 void visit(ir_assignment
*ir
);
211 void visit(ir_dereference_variable
*ir
);
212 void visit(ir_dereference_record
*ir
);
213 void visit(ir_dereference_array
*ir
);
214 void visit(ir_expression
*ir
);
215 void visit(ir_texture
*ir
);
216 void visit(ir_if
*ir
);
217 void visit(ir_constant
*ir
);
218 void visit(ir_swizzle
*ir
);
219 void visit(ir_return
*ir
);
220 void visit(ir_loop
*ir
);
221 void visit(ir_loop_jump
*ir
);
222 void visit(ir_discard
*ir
);
223 void visit(ir_call
*ir
);
224 void visit(ir_function
*ir
);
225 void visit(ir_function_signature
*ir
);
227 void swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
);
229 bool can_do_source_mods(fs_inst
*inst
);
231 fs_inst
*emit(fs_inst inst
);
232 fs_inst
*emit(fs_inst
*inst
);
233 void emit(exec_list list
);
235 fs_inst
*emit(enum opcode opcode
);
236 fs_inst
*emit(enum opcode opcode
, fs_reg dst
);
237 fs_inst
*emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
);
238 fs_inst
*emit(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
239 fs_inst
*emit(enum opcode opcode
, fs_reg dst
,
240 fs_reg src0
, fs_reg src1
, fs_reg src2
);
242 fs_inst
*MOV(fs_reg dst
, fs_reg src
);
243 fs_inst
*NOT(fs_reg dst
, fs_reg src
);
244 fs_inst
*RNDD(fs_reg dst
, fs_reg src
);
245 fs_inst
*RNDE(fs_reg dst
, fs_reg src
);
246 fs_inst
*RNDZ(fs_reg dst
, fs_reg src
);
247 fs_inst
*FRC(fs_reg dst
, fs_reg src
);
248 fs_inst
*ADD(fs_reg dst
, fs_reg src0
, fs_reg src1
);
249 fs_inst
*MUL(fs_reg dst
, fs_reg src0
, fs_reg src1
);
250 fs_inst
*MACH(fs_reg dst
, fs_reg src0
, fs_reg src1
);
251 fs_inst
*MAC(fs_reg dst
, fs_reg src0
, fs_reg src1
);
252 fs_inst
*SHL(fs_reg dst
, fs_reg src0
, fs_reg src1
);
253 fs_inst
*SHR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
254 fs_inst
*ASR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
255 fs_inst
*AND(fs_reg dst
, fs_reg src0
, fs_reg src1
);
256 fs_inst
*OR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
257 fs_inst
*XOR(fs_reg dst
, fs_reg src0
, fs_reg src1
);
258 fs_inst
*IF(uint32_t predicate
);
259 fs_inst
*IF(fs_reg src0
, fs_reg src1
, uint32_t condition
);
260 fs_inst
*CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
,
263 int type_size(const struct glsl_type
*type
);
264 fs_inst
*get_instruction_generating_reg(fs_inst
*start
,
268 exec_list
VARYING_PULL_CONSTANT_LOAD(fs_reg dst
, fs_reg surf_index
,
272 void setup_payload_gen4();
273 void setup_payload_gen6();
274 void setup_paramvalues_refs();
275 void assign_curb_setup();
276 void calculate_urb_setup();
277 void assign_urb_setup();
279 void assign_regs_trivial();
280 void setup_payload_interference(struct ra_graph
*g
, int payload_reg_count
,
281 int first_payload_node
);
282 void setup_mrf_hack_interference(struct ra_graph
*g
,
283 int first_mrf_hack_node
);
284 int choose_spill_reg(struct ra_graph
*g
);
285 void spill_reg(int spill_reg
);
286 void split_virtual_grfs();
287 void compact_virtual_grfs();
288 void move_uniform_array_access_to_pull_constants();
289 void setup_pull_constants();
290 void calculate_live_intervals();
291 bool opt_algebraic();
293 bool opt_cse_local(bblock_t
*block
, exec_list
*aeb
);
294 bool opt_copy_propagate();
295 bool try_copy_propagate(fs_inst
*inst
, int arg
, acp_entry
*entry
);
296 bool try_constant_propagate(fs_inst
*inst
, acp_entry
*entry
);
297 bool opt_copy_propagate_local(void *mem_ctx
, bblock_t
*block
,
299 bool register_coalesce();
300 bool register_coalesce_2();
301 bool compute_to_mrf();
302 bool dead_code_eliminate();
303 bool remove_dead_constants();
304 bool remove_duplicate_mrf_writes();
305 bool virtual_grf_interferes(int a
, int b
);
306 void schedule_instructions();
307 void fail(const char *msg
, ...);
309 void push_force_uncompressed();
310 void pop_force_uncompressed();
311 void push_force_sechalf();
312 void pop_force_sechalf();
314 void emit_dummy_fs();
315 fs_reg
*emit_fragcoord_interpolation(ir_variable
*ir
);
316 fs_inst
*emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
317 glsl_interp_qualifier interpolation_mode
,
319 fs_reg
*emit_frontfacing_interpolation(ir_variable
*ir
);
320 fs_reg
*emit_general_interpolation(ir_variable
*ir
);
321 void emit_interpolation_setup_gen4();
322 void emit_interpolation_setup_gen6();
323 fs_reg
rescale_texcoord(ir_texture
*ir
, fs_reg coordinate
,
324 bool is_rect
, int sampler
, int texunit
);
325 fs_inst
*emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
326 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
);
327 fs_inst
*emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
328 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
);
329 fs_inst
*emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
330 fs_reg shadow_comp
, fs_reg lod
, fs_reg lod2
);
331 fs_inst
*emit_math(enum opcode op
, fs_reg dst
, fs_reg src0
);
332 fs_inst
*emit_math(enum opcode op
, fs_reg dst
, fs_reg src0
, fs_reg src1
);
333 void emit_minmax(uint32_t conditionalmod
, fs_reg dst
,
334 fs_reg src0
, fs_reg src1
);
335 bool try_emit_saturate(ir_expression
*ir
);
336 bool try_emit_mad(ir_expression
*ir
, int mul_arg
);
337 void emit_bool_to_cond_code(ir_rvalue
*condition
);
338 void emit_if_gen6(ir_if
*ir
);
339 void emit_unspill(fs_inst
*inst
, fs_reg reg
, uint32_t spill_offset
);
341 void emit_fragment_program_code();
342 void setup_fp_regs();
343 fs_reg
get_fp_src_reg(const prog_src_register
*src
);
344 fs_reg
get_fp_dst_reg(const prog_dst_register
*dst
);
345 void emit_fp_alu1(enum opcode opcode
,
346 const struct prog_instruction
*fpi
,
347 fs_reg dst
, fs_reg src
);
348 void emit_fp_alu2(enum opcode opcode
,
349 const struct prog_instruction
*fpi
,
350 fs_reg dst
, fs_reg src0
, fs_reg src1
);
351 void emit_fp_scalar_write(const struct prog_instruction
*fpi
,
352 fs_reg dst
, fs_reg src
);
353 void emit_fp_scalar_math(enum opcode opcode
,
354 const struct prog_instruction
*fpi
,
355 fs_reg dst
, fs_reg src
);
357 void emit_fp_minmax(const struct prog_instruction
*fpi
,
358 fs_reg dst
, fs_reg src0
, fs_reg src1
);
360 void emit_fp_sop(uint32_t conditional_mod
,
361 const struct prog_instruction
*fpi
,
362 fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg one
);
364 void emit_color_write(int target
, int index
, int first_color_mrf
);
365 void emit_fb_writes();
366 bool try_rewrite_rhs_to_dst(ir_assignment
*ir
,
369 fs_inst
*pre_rhs_inst
,
370 fs_inst
*last_rhs_inst
);
371 void emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
372 const glsl_type
*type
, bool predicated
);
373 void resolve_ud_negate(fs_reg
*reg
);
374 void resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
);
376 struct brw_reg
interp_reg(int location
, int channel
);
377 int setup_uniform_values(int loc
, const glsl_type
*type
);
378 void setup_builtin_uniform_values(ir_variable
*ir
);
379 int implied_mrf_writes(fs_inst
*inst
);
381 void dump_instructions();
382 void dump_instruction(fs_inst
*inst
);
384 const struct gl_fragment_program
*fp
;
385 struct brw_wm_compile
*c
;
387 /* Delayed setup of c->prog_data.params[] due to realloc of
388 * ParamValues[] during compile.
390 int param_index
[MAX_UNIFORMS
* 4];
391 int param_offset
[MAX_UNIFORMS
* 4];
392 int param_size
[MAX_UNIFORMS
* 4];
394 int *virtual_grf_sizes
;
395 int virtual_grf_count
;
396 int virtual_grf_array_size
;
397 int *virtual_grf_def
;
398 int *virtual_grf_use
;
399 bool live_intervals_valid
;
401 /* This is the map from UNIFORM hw_reg + reg_offset as generated by
402 * the visitor to the packed uniform number after
403 * remove_dead_constants() that represents the actual uploaded
408 struct hash_table
*variable_ht
;
410 fs_reg outputs
[BRW_MAX_DRAW_BUFFERS
];
411 unsigned output_components
[BRW_MAX_DRAW_BUFFERS
];
412 fs_reg dual_src_output
;
413 int first_non_payload_grf
;
414 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
416 int urb_setup
[FRAG_ATTRIB_MAX
];
418 fs_reg
*fp_temp_regs
;
419 fs_reg
*fp_input_regs
;
421 /** @{ debug annotation info */
422 const char *current_annotation
;
429 /* Result of last visit() method. */
436 fs_reg delta_x
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
437 fs_reg delta_y
[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
];
441 const unsigned dispatch_width
; /**< 8 or 16 */
443 int force_uncompressed_stack
;
444 int force_sechalf_stack
;
448 * The fragment shader code generator.
450 * Translates FS IR to actual i965 assembly code.
455 fs_generator(struct brw_context
*brw
,
456 struct brw_wm_compile
*c
,
457 struct gl_shader_program
*prog
,
458 struct gl_fragment_program
*fp
,
459 bool dual_source_output
);
462 const unsigned *generate_assembly(exec_list
*simd8_instructions
,
463 exec_list
*simd16_instructions
,
464 unsigned *assembly_size
);
467 void generate_code(exec_list
*instructions
);
468 void generate_fb_write(fs_inst
*inst
);
469 void generate_pixel_xy(struct brw_reg dst
, bool is_x
);
470 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
471 struct brw_reg
*src
);
472 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
473 void generate_math1_gen7(fs_inst
*inst
,
476 void generate_math2_gen7(fs_inst
*inst
,
479 struct brw_reg src1
);
480 void generate_math1_gen6(fs_inst
*inst
,
483 void generate_math2_gen6(fs_inst
*inst
,
486 struct brw_reg src1
);
487 void generate_math_gen4(fs_inst
*inst
,
490 void generate_discard(fs_inst
*inst
);
491 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
492 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
494 void generate_spill(fs_inst
*inst
, struct brw_reg src
);
495 void generate_unspill(fs_inst
*inst
, struct brw_reg dst
);
496 void generate_uniform_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
,
497 struct brw_reg index
,
498 struct brw_reg offset
);
499 void generate_varying_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
,
500 struct brw_reg index
);
501 void generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
503 struct brw_reg index
,
504 struct brw_reg offset
);
505 void generate_mov_dispatch_to_flags();
507 struct brw_context
*brw
;
508 struct intel_context
*intel
;
509 struct gl_context
*ctx
;
511 struct brw_compile
*p
;
512 struct brw_wm_compile
*c
;
514 struct gl_shader_program
*prog
;
515 struct gl_shader
*shader
;
516 const struct gl_fragment_program
*fp
;
518 unsigned dispatch_width
; /**< 8 or 16 */
520 bool dual_source_output
;
524 bool brw_do_channel_expressions(struct exec_list
*instructions
);
525 bool brw_do_vector_splitting(struct exec_list
*instructions
);
526 bool brw_fs_precompile(struct gl_context
*ctx
, struct gl_shader_program
*prog
);