i965: Remove the emit_linterp() helper.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs.h
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #pragma once
29
30 #include "brw_shader.h"
31 #include "brw_ir_fs.h"
32 #include "brw_fs_builder.h"
33 #include "compiler/nir/nir.h"
34
35 struct bblock_t;
36 namespace {
37 struct acp_entry;
38 }
39
40 namespace brw {
41 class fs_live_variables;
42 }
43
44 struct brw_gs_compile;
45
46 static inline fs_reg
47 offset(const fs_reg &reg, const brw::fs_builder &bld, unsigned delta)
48 {
49 return offset(reg, bld.dispatch_width(), delta);
50 }
51
52 /**
53 * The fragment shader front-end.
54 *
55 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
56 */
57 class fs_visitor : public backend_shader
58 {
59 public:
60 fs_visitor(const struct brw_compiler *compiler, void *log_data,
61 void *mem_ctx,
62 const void *key,
63 struct brw_stage_prog_data *prog_data,
64 struct gl_program *prog,
65 const nir_shader *shader,
66 unsigned dispatch_width,
67 int shader_time_index,
68 const struct brw_vue_map *input_vue_map = NULL);
69 fs_visitor(const struct brw_compiler *compiler, void *log_data,
70 void *mem_ctx,
71 struct brw_gs_compile *gs_compile,
72 struct brw_gs_prog_data *prog_data,
73 const nir_shader *shader,
74 int shader_time_index);
75 void init();
76 ~fs_visitor();
77
78 fs_reg vgrf(const glsl_type *const type);
79 void import_uniforms(fs_visitor *v);
80 void setup_uniform_clipplane_values(gl_clip_plane *clip_planes);
81 void compute_clip_distance(gl_clip_plane *clip_planes);
82
83 fs_inst *get_instruction_generating_reg(fs_inst *start,
84 fs_inst *end,
85 const fs_reg &reg);
86
87 void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld,
88 const fs_reg &dst,
89 const fs_reg &surf_index,
90 const fs_reg &varying_offset,
91 uint32_t const_offset);
92 void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf);
93
94 bool run_fs(bool allow_spilling, bool do_rep_send);
95 bool run_vs(gl_clip_plane *clip_planes);
96 bool run_tcs_single_patch();
97 bool run_tes();
98 bool run_gs();
99 bool run_cs();
100 void optimize();
101 void allocate_registers(bool allow_spilling);
102 void setup_fs_payload_gen4();
103 void setup_fs_payload_gen6();
104 void setup_vs_payload();
105 void setup_gs_payload();
106 void setup_cs_payload();
107 void fixup_3src_null_dest();
108 void assign_curb_setup();
109 void calculate_urb_setup();
110 void assign_urb_setup();
111 void convert_attr_sources_to_hw_regs(fs_inst *inst);
112 void assign_vs_urb_setup();
113 void assign_tcs_single_patch_urb_setup();
114 void assign_tes_urb_setup();
115 void assign_gs_urb_setup();
116 bool assign_regs(bool allow_spilling, bool spill_all);
117 void assign_regs_trivial();
118 void calculate_payload_ranges(int payload_node_count,
119 int *payload_last_use_ip);
120 void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
121 int first_payload_node);
122 int choose_spill_reg(struct ra_graph *g);
123 void spill_reg(int spill_reg);
124 void split_virtual_grfs();
125 bool compact_virtual_grfs();
126 void assign_constant_locations();
127 void lower_constant_loads();
128 void invalidate_live_intervals();
129 void calculate_live_intervals();
130 void calculate_register_pressure();
131 void validate();
132 bool opt_algebraic();
133 bool opt_redundant_discard_jumps();
134 bool opt_cse();
135 bool opt_cse_local(bblock_t *block);
136 bool opt_copy_propagate();
137 bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
138 bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
139 bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
140 exec_list *acp);
141 bool opt_drop_redundant_mov_to_flags();
142 bool opt_register_renaming();
143 bool register_coalesce();
144 bool compute_to_mrf();
145 bool eliminate_find_live_channel();
146 bool dead_code_eliminate();
147 bool remove_duplicate_mrf_writes();
148
149 bool opt_sampler_eot();
150 bool virtual_grf_interferes(int a, int b);
151 void schedule_instructions(instruction_scheduler_mode mode);
152 void insert_gen4_send_dependency_workarounds();
153 void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
154 fs_inst *inst);
155 void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
156 fs_inst *inst);
157 void vfail(const char *msg, va_list args);
158 void fail(const char *msg, ...);
159 void limit_dispatch_width(unsigned n, const char *msg);
160 void lower_uniform_pull_constant_loads();
161 bool lower_load_payload();
162 bool lower_pack();
163 bool lower_d2x();
164 bool lower_logical_sends();
165 bool lower_integer_multiplication();
166 bool lower_minmax();
167 bool lower_simd_width();
168 bool opt_combine_constants();
169
170 void emit_dummy_fs();
171 void emit_repclear_shader();
172 fs_reg *emit_fragcoord_interpolation();
173 fs_reg *emit_frontfacing_interpolation();
174 fs_reg *emit_samplepos_setup();
175 fs_reg *emit_sampleid_setup();
176 fs_reg *emit_samplemaskin_setup();
177 void emit_general_interpolation(fs_reg *attr, const char *name,
178 const glsl_type *type,
179 glsl_interp_qualifier interpolation_mode,
180 int *location, bool mod_centroid,
181 bool mod_sample);
182 fs_reg *emit_vs_system_value(int location);
183 void emit_interpolation_setup_gen4();
184 void emit_interpolation_setup_gen6();
185 void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
186 fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
187 const fs_reg &sampler);
188 void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
189 fs_reg resolve_source_modifiers(const fs_reg &src);
190 void emit_discard_jump();
191 bool opt_peephole_sel();
192 bool opt_peephole_predicated_break();
193 bool opt_saturate_propagation();
194 bool opt_cmod_propagation();
195 bool opt_zero_samples();
196
197 void emit_nir_code();
198 void nir_setup_inputs();
199 void nir_setup_single_output_varying(fs_reg *reg, const glsl_type *type,
200 unsigned *location);
201 void nir_setup_outputs();
202 void nir_setup_uniforms();
203 void nir_emit_system_values();
204 void nir_emit_impl(nir_function_impl *impl);
205 void nir_emit_cf_list(exec_list *list);
206 void nir_emit_if(nir_if *if_stmt);
207 void nir_emit_loop(nir_loop *loop);
208 void nir_emit_block(nir_block *block);
209 void nir_emit_instr(nir_instr *instr);
210 void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr);
211 void nir_emit_load_const(const brw::fs_builder &bld,
212 nir_load_const_instr *instr);
213 void nir_emit_undef(const brw::fs_builder &bld,
214 nir_ssa_undef_instr *instr);
215 void nir_emit_vs_intrinsic(const brw::fs_builder &bld,
216 nir_intrinsic_instr *instr);
217 void nir_emit_tcs_intrinsic(const brw::fs_builder &bld,
218 nir_intrinsic_instr *instr);
219 void nir_emit_gs_intrinsic(const brw::fs_builder &bld,
220 nir_intrinsic_instr *instr);
221 void nir_emit_fs_intrinsic(const brw::fs_builder &bld,
222 nir_intrinsic_instr *instr);
223 void nir_emit_cs_intrinsic(const brw::fs_builder &bld,
224 nir_intrinsic_instr *instr);
225 void nir_emit_intrinsic(const brw::fs_builder &bld,
226 nir_intrinsic_instr *instr);
227 void nir_emit_tes_intrinsic(const brw::fs_builder &bld,
228 nir_intrinsic_instr *instr);
229 void nir_emit_ssbo_atomic(const brw::fs_builder &bld,
230 int op, nir_intrinsic_instr *instr);
231 void nir_emit_shared_atomic(const brw::fs_builder &bld,
232 int op, nir_intrinsic_instr *instr);
233 void nir_emit_texture(const brw::fs_builder &bld,
234 nir_tex_instr *instr);
235 void nir_emit_jump(const brw::fs_builder &bld,
236 nir_jump_instr *instr);
237 fs_reg get_nir_src(const nir_src &src);
238 fs_reg get_nir_src_imm(const nir_src &src);
239 fs_reg get_nir_dest(const nir_dest &dest);
240 fs_reg get_nir_image_deref(const nir_deref_var *deref);
241 fs_reg get_indirect_offset(nir_intrinsic_instr *instr);
242 void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst,
243 unsigned wr_mask);
244
245 bool optimize_extract_to_float(nir_alu_instr *instr,
246 const fs_reg &result);
247 bool optimize_frontfacing_ternary(nir_alu_instr *instr,
248 const fs_reg &result);
249
250 void emit_alpha_test();
251 fs_inst *emit_single_fb_write(const brw::fs_builder &bld,
252 fs_reg color1, fs_reg color2,
253 fs_reg src0_alpha, unsigned components);
254 void emit_fb_writes();
255 void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg());
256 void set_gs_stream_control_data_bits(const fs_reg &vertex_count,
257 unsigned stream_id);
258 void emit_gs_control_data_bits(const fs_reg &vertex_count);
259 void emit_gs_end_primitive(const nir_src &vertex_count_nir_src);
260 void emit_gs_vertex(const nir_src &vertex_count_nir_src,
261 unsigned stream_id);
262 void emit_gs_thread_end();
263 void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src,
264 unsigned base_offset, const nir_src &offset_src,
265 unsigned num_components, unsigned first_component);
266 void emit_cs_terminate();
267 fs_reg *emit_cs_work_group_id_setup();
268
269 void emit_barrier();
270
271 void emit_shader_time_begin();
272 void emit_shader_time_end();
273 void SHADER_TIME_ADD(const brw::fs_builder &bld,
274 int shader_time_subindex,
275 fs_reg value);
276
277 fs_reg get_timestamp(const brw::fs_builder &bld);
278
279 struct brw_reg interp_reg(int location, int channel);
280
281 int implied_mrf_writes(fs_inst *inst);
282
283 virtual void dump_instructions();
284 virtual void dump_instructions(const char *name);
285 void dump_instruction(backend_instruction *inst);
286 void dump_instruction(backend_instruction *inst, FILE *file);
287
288 const void *const key;
289 const struct brw_sampler_prog_key_data *key_tex;
290
291 struct brw_gs_compile *gs_compile;
292
293 struct brw_stage_prog_data *prog_data;
294 struct gl_program *prog;
295
296 const struct brw_vue_map *input_vue_map;
297
298 int *virtual_grf_start;
299 int *virtual_grf_end;
300 brw::fs_live_variables *live_intervals;
301
302 int *regs_live_at_ip;
303
304 /** Number of uniform variable components visited. */
305 unsigned uniforms;
306
307 /** Byte-offset for the next available spot in the scratch space buffer. */
308 unsigned last_scratch;
309
310 /**
311 * Array mapping UNIFORM register numbers to the pull parameter index,
312 * or -1 if this uniform register isn't being uploaded as a pull constant.
313 */
314 int *pull_constant_loc;
315
316 /**
317 * Array mapping UNIFORM register numbers to the push parameter index,
318 * or -1 if this uniform register isn't being uploaded as a push constant.
319 */
320 int *push_constant_loc;
321
322 fs_reg frag_depth;
323 fs_reg frag_stencil;
324 fs_reg sample_mask;
325 fs_reg outputs[VARYING_SLOT_MAX];
326 unsigned output_components[VARYING_SLOT_MAX];
327 fs_reg dual_src_output;
328 bool do_dual_src;
329 int first_non_payload_grf;
330 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
331 unsigned max_grf;
332
333 fs_reg *nir_locals;
334 fs_reg *nir_ssa_values;
335 fs_reg nir_inputs;
336 fs_reg nir_outputs;
337 fs_reg *nir_system_values;
338
339 bool failed;
340 char *fail_msg;
341
342 /** Register numbers for thread payload fields. */
343 struct thread_payload {
344 uint8_t source_depth_reg;
345 uint8_t source_w_reg;
346 uint8_t aa_dest_stencil_reg;
347 uint8_t dest_depth_reg;
348 uint8_t sample_pos_reg;
349 uint8_t sample_mask_in_reg;
350 uint8_t barycentric_coord_reg[BRW_BARYCENTRIC_MODE_COUNT];
351 uint8_t local_invocation_id_reg;
352
353 /** The number of thread payload registers the hardware will supply. */
354 uint8_t num_regs;
355 } payload;
356
357 bool source_depth_to_render_target;
358 bool runtime_check_aads_emit;
359
360 fs_reg pixel_x;
361 fs_reg pixel_y;
362 fs_reg wpos_w;
363 fs_reg pixel_w;
364 fs_reg delta_xy[BRW_BARYCENTRIC_MODE_COUNT];
365 fs_reg shader_start_time;
366 fs_reg userplane[MAX_CLIP_PLANES];
367 fs_reg final_gs_vertex_count;
368 fs_reg control_data_bits;
369 fs_reg invocation_id;
370
371 unsigned grf_used;
372 bool spilled_any_registers;
373
374 const unsigned dispatch_width; /**< 8, 16 or 32 */
375 unsigned min_dispatch_width;
376 unsigned max_dispatch_width;
377
378 int shader_time_index;
379
380 unsigned promoted_constants;
381 brw::fs_builder bld;
382 };
383
384 /**
385 * The fragment shader code generator.
386 *
387 * Translates FS IR to actual i965 assembly code.
388 */
389 class fs_generator
390 {
391 public:
392 fs_generator(const struct brw_compiler *compiler, void *log_data,
393 void *mem_ctx,
394 const void *key,
395 struct brw_stage_prog_data *prog_data,
396 unsigned promoted_constants,
397 bool runtime_check_aads_emit,
398 gl_shader_stage stage);
399 ~fs_generator();
400
401 void enable_debug(const char *shader_name);
402 int generate_code(const cfg_t *cfg, int dispatch_width);
403 const unsigned *get_assembly(unsigned int *assembly_size);
404
405 private:
406 void fire_fb_write(fs_inst *inst,
407 struct brw_reg payload,
408 struct brw_reg implied_header,
409 GLuint nr);
410 void generate_fb_write(fs_inst *inst, struct brw_reg payload);
411 void generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload);
412 void generate_urb_write(fs_inst *inst, struct brw_reg payload);
413 void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
414 void generate_barrier(fs_inst *inst, struct brw_reg src);
415 void generate_linterp(fs_inst *inst, struct brw_reg dst,
416 struct brw_reg *src);
417 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
418 struct brw_reg surface_index,
419 struct brw_reg sampler_index);
420 void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst,
421 struct brw_reg src,
422 struct brw_reg surf_index);
423 void generate_ddx(enum opcode op, struct brw_reg dst, struct brw_reg src);
424 void generate_ddy(enum opcode op, struct brw_reg dst, struct brw_reg src);
425 void generate_scratch_write(fs_inst *inst, struct brw_reg src);
426 void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
427 void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
428 void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
429 struct brw_reg index,
430 struct brw_reg offset);
431 void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
432 struct brw_reg dst,
433 struct brw_reg surf_index,
434 struct brw_reg offset);
435 void generate_varying_pull_constant_load_gen4(fs_inst *inst,
436 struct brw_reg dst,
437 struct brw_reg index);
438 void generate_varying_pull_constant_load_gen7(fs_inst *inst,
439 struct brw_reg dst,
440 struct brw_reg index,
441 struct brw_reg offset);
442 void generate_mov_dispatch_to_flags(fs_inst *inst);
443
444 void generate_pixel_interpolator_query(fs_inst *inst,
445 struct brw_reg dst,
446 struct brw_reg src,
447 struct brw_reg msg_data,
448 unsigned msg_type);
449
450 void generate_set_sample_id(fs_inst *inst,
451 struct brw_reg dst,
452 struct brw_reg src0,
453 struct brw_reg src1);
454
455 void generate_set_simd4x2_offset(fs_inst *inst,
456 struct brw_reg dst,
457 struct brw_reg offset);
458 void generate_discard_jump(fs_inst *inst);
459
460 void generate_pack_half_2x16_split(fs_inst *inst,
461 struct brw_reg dst,
462 struct brw_reg x,
463 struct brw_reg y);
464 void generate_unpack_half_2x16_split(fs_inst *inst,
465 struct brw_reg dst,
466 struct brw_reg src);
467
468 void generate_shader_time_add(fs_inst *inst,
469 struct brw_reg payload,
470 struct brw_reg offset,
471 struct brw_reg value);
472
473 void generate_mov_indirect(fs_inst *inst,
474 struct brw_reg dst,
475 struct brw_reg reg,
476 struct brw_reg indirect_byte_offset);
477
478 bool patch_discard_jumps_to_fb_writes();
479
480 const struct brw_compiler *compiler;
481 void *log_data; /* Passed to compiler->*_log functions */
482
483 const struct brw_device_info *devinfo;
484
485 struct brw_codegen *p;
486 const void * const key;
487 struct brw_stage_prog_data * const prog_data;
488
489 unsigned dispatch_width; /**< 8, 16 or 32 */
490
491 exec_list discard_halt_patches;
492 unsigned promoted_constants;
493 bool runtime_check_aads_emit;
494 bool debug_flag;
495 const char *shader_name;
496 gl_shader_stage stage;
497 void *mem_ctx;
498 };
499
500 bool brw_do_channel_expressions(struct exec_list *instructions);
501 bool brw_do_vector_splitting(struct exec_list *instructions);
502
503 void shuffle_32bit_load_result_to_64bit_data(const brw::fs_builder &bld,
504 const fs_reg &dst,
505 const fs_reg &src,
506 uint32_t components);
507
508 void shuffle_64bit_data_for_32bit_write(const brw::fs_builder &bld,
509 const fs_reg &dst,
510 const fs_reg &src,
511 uint32_t components);
512 fs_reg setup_imm_df(const brw::fs_builder &bld,
513 double v);