src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31
  32 extern "C" {
  33
  34 #include <sys/types.h>
  35
  36 #include "main/macros.h"
  37 #include "main/shaderobj.h"
  38 #include "main/uniforms.h"
  39 #include "program/prog_parameter.h"
  40 #include "program/prog_print.h"
  41 #include "program/prog_optimize.h"
  42 #include "program/register_allocate.h"
  43 #include "program/sampler.h"
  44 #include "program/hash_table.h"
  45 #include "brw_context.h"
  46 #include "brw_eu.h"
  47 #include "brw_wm.h"
  48 #include "brw_shader.h"
  49 }
  50 #include "glsl/glsl_types.h"
  51 #include "glsl/ir.h"
  52
  53 class bblock_t;
  54 namespace {
  55    class acp_entry;
  56 }
  57
  58 enum register_file {
  59    BAD_FILE,
  60    ARF,
  61    GRF,
  62    MRF,
  63    IMM,
  64    FIXED_HW_REG, /* a struct brw_reg */
  65    UNIFORM, /* prog_data->params[reg] */
  66 };
  67
  68 class fs_reg {
  69 public:
  70    /* Callers of this ralloc-based new need not call delete. It's
  71     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
  72    static void* operator new(size_t size, void *ctx)
  73    {
  74       void *node;
  75
  76       node = ralloc_size(ctx, size);
  77       assert(node != NULL);
  78
  79       return node;
  80    }
  81
  82    void init();
  83
  84    fs_reg();
  85    fs_reg(float f);
  86    fs_reg(int32_t i);
  87    fs_reg(uint32_t u);
  88    fs_reg(struct brw_reg fixed_hw_reg);
  89    fs_reg(enum register_file file, int reg);
  90    fs_reg(enum register_file file, int reg, uint32_t type);
  91    fs_reg(class fs_visitor *v, const struct glsl_type *type);
  92
  93    bool equals(const fs_reg &r) const;
  94    bool is_zero() const;
  95    bool is_one() const;
  96
  97    /** Register file: ARF, GRF, MRF, IMM. */
  98    enum register_file file;
  99    /**
 100     * Register number.  For ARF/MRF, it's the hardware register.  For
 101     * GRF, it's a virtual register number until register allocation
 102     */
 103    int reg;
 104    /**
 105     * For virtual registers, this is a hardware register offset from
 106     * the start of the register block (for example, a constant index
 107     * in an array access).
 108     */
 109    int reg_offset;
 110    /** Register type.  BRW_REGISTER_TYPE_* */
 111    int type;
 112    bool negate;
 113    bool abs;
 114    bool sechalf;
 115    struct brw_reg fixed_hw_reg;
 116    int smear; /* -1, or a channel of the reg to smear to all channels. */
 117
 118    /** Value for file == IMM */
 119    union {
 120       int32_t i;
 121       uint32_t u;
 122       float f;
 123    } imm;
 124 };
 125
 126 static const fs_reg reg_undef;
 127 static const fs_reg reg_null_f(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_F);
 128 static const fs_reg reg_null_d(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_D);
 129
 130 class fs_inst : public backend_instruction {
 131 public:
 132    /* Callers of this ralloc-based new need not call delete. It's
 133     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 134    static void* operator new(size_t size, void *ctx)
 135    {
 136       void *node;
 137
 138       node = rzalloc_size(ctx, size);
 139       assert(node != NULL);
 140
 141       return node;
 142    }
 143
 144    void init();
 145
 146    fs_inst();
 147    fs_inst(enum opcode opcode);
 148    fs_inst(enum opcode opcode, fs_reg dst);
 149    fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0);
 150    fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
 151    fs_inst(enum opcode opcode, fs_reg dst,
 152            fs_reg src0, fs_reg src1,fs_reg src2);
 153
 154    bool equals(fs_inst *inst);
 155    int regs_written();
 156    bool overwrites_reg(const fs_reg &reg);
 157    bool is_tex();
 158    bool is_math();
 159    bool is_send_from_grf();
 160
 161    fs_reg dst;
 162    fs_reg src[3];
 163    bool saturate;
 164    int conditional_mod; /**< BRW_CONDITIONAL_* */
 165
 166    int mlen; /**< SEND message length */
 167    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 168    uint32_t texture_offset; /**< Texture offset bitfield */
 169    int sampler;
 170    int target; /**< MRT target. */
 171    bool eot;
 172    bool header_present;
 173    bool shadow_compare;
 174    bool force_uncompressed;
 175    bool force_sechalf;
 176    uint32_t offset; /* spill/unspill offset */
 177
 178    /** @{
 179     * Annotation for the generated IR.  One of the two can be set.
 180     */
 181    const void *ir;
 182    const char *annotation;
 183    /** @} */
 184 };
 185
 186 /**
 187  * The fragment shader front-end.
 188  *
 189  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
 190  */
 191 class fs_visitor : public backend_visitor
 192 {
 193 public:
 194
 195    fs_visitor(struct brw_context *brw,
 196               struct brw_wm_compile *c,
 197               struct gl_shader_program *prog,
 198               struct gl_fragment_program *fp,
 199               unsigned dispatch_width);
 200    ~fs_visitor();
 201
 202    fs_reg *variable_storage(ir_variable *var);
 203    int virtual_grf_alloc(int size);
 204    void import_uniforms(fs_visitor *v);
 205
 206    void visit(ir_variable *ir);
 207    void visit(ir_assignment *ir);
 208    void visit(ir_dereference_variable *ir);
 209    void visit(ir_dereference_record *ir);
 210    void visit(ir_dereference_array *ir);
 211    void visit(ir_expression *ir);
 212    void visit(ir_texture *ir);
 213    void visit(ir_if *ir);
 214    void visit(ir_constant *ir);
 215    void visit(ir_swizzle *ir);
 216    void visit(ir_return *ir);
 217    void visit(ir_loop *ir);
 218    void visit(ir_loop_jump *ir);
 219    void visit(ir_discard *ir);
 220    void visit(ir_call *ir);
 221    void visit(ir_function *ir);
 222    void visit(ir_function_signature *ir);
 223
 224    void swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler);
 225
 226    bool can_do_source_mods(fs_inst *inst);
 227
 228    fs_inst *emit(fs_inst inst);
 229    fs_inst *emit(fs_inst *inst);
 230
 231    fs_inst *emit(enum opcode opcode);
 232    fs_inst *emit(enum opcode opcode, fs_reg dst);
 233    fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0);
 234    fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
 235    fs_inst *emit(enum opcode opcode, fs_reg dst,
 236                  fs_reg src0, fs_reg src1, fs_reg src2);
 237
 238    fs_inst *MOV(fs_reg dst, fs_reg src);
 239    fs_inst *NOT(fs_reg dst, fs_reg src);
 240    fs_inst *RNDD(fs_reg dst, fs_reg src);
 241    fs_inst *RNDE(fs_reg dst, fs_reg src);
 242    fs_inst *RNDZ(fs_reg dst, fs_reg src);
 243    fs_inst *FRC(fs_reg dst, fs_reg src);
 244    fs_inst *ADD(fs_reg dst, fs_reg src0, fs_reg src1);
 245    fs_inst *MUL(fs_reg dst, fs_reg src0, fs_reg src1);
 246    fs_inst *MACH(fs_reg dst, fs_reg src0, fs_reg src1);
 247    fs_inst *MAC(fs_reg dst, fs_reg src0, fs_reg src1);
 248    fs_inst *SHL(fs_reg dst, fs_reg src0, fs_reg src1);
 249    fs_inst *SHR(fs_reg dst, fs_reg src0, fs_reg src1);
 250    fs_inst *ASR(fs_reg dst, fs_reg src0, fs_reg src1);
 251    fs_inst *AND(fs_reg dst, fs_reg src0, fs_reg src1);
 252    fs_inst *OR(fs_reg dst, fs_reg src0, fs_reg src1);
 253    fs_inst *XOR(fs_reg dst, fs_reg src0, fs_reg src1);
 254    fs_inst *IF(uint32_t predicate);
 255    fs_inst *IF(fs_reg src0, fs_reg src1, uint32_t condition);
 256    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 257                 uint32_t condition);
 258
 259    int type_size(const struct glsl_type *type);
 260    fs_inst *get_instruction_generating_reg(fs_inst *start,
 261                                            fs_inst *end,
 262                                            fs_reg reg);
 263
 264    bool run();
 265    void setup_payload_gen4();
 266    void setup_payload_gen6();
 267    void setup_paramvalues_refs();
 268    void assign_curb_setup();
 269    void calculate_urb_setup();
 270    void assign_urb_setup();
 271    bool assign_regs();
 272    void assign_regs_trivial();
 273    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 274                                    int first_payload_node);
 275    void setup_mrf_hack_interference(struct ra_graph *g,
 276                                     int first_mrf_hack_node);
 277    int choose_spill_reg(struct ra_graph *g);
 278    void spill_reg(int spill_reg);
 279    void split_virtual_grfs();
 280    void compact_virtual_grfs();
 281    void setup_pull_constants();
 282    void calculate_live_intervals();
 283    bool opt_algebraic();
 284    bool opt_cse();
 285    bool opt_cse_local(bblock_t *block, exec_list *aeb);
 286    bool opt_copy_propagate();
 287    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 288    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 289    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 290                                  exec_list *acp);
 291    bool register_coalesce();
 292    bool register_coalesce_2();
 293    bool compute_to_mrf();
 294    bool dead_code_eliminate();
 295    bool remove_dead_constants();
 296    bool remove_duplicate_mrf_writes();
 297    bool virtual_grf_interferes(int a, int b);
 298    void schedule_instructions();
 299    void fail(const char *msg, ...);
 300
 301    void push_force_uncompressed();
 302    void pop_force_uncompressed();
 303    void push_force_sechalf();
 304    void pop_force_sechalf();
 305
 306    void emit_dummy_fs();
 307    fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
 308    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 309                          glsl_interp_qualifier interpolation_mode,
 310                          bool is_centroid);
 311    fs_reg *emit_frontfacing_interpolation(ir_variable *ir);
 312    fs_reg *emit_general_interpolation(ir_variable *ir);
 313    void emit_interpolation_setup_gen4();
 314    void emit_interpolation_setup_gen6();
 315    fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
 316                            bool is_rect, int sampler, int texunit);
 317    fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 318                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2);
 319    fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 320                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2);
 321    fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 322                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2);
 323    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 324    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 325    void emit_minmax(uint32_t conditionalmod, fs_reg dst,
 326                     fs_reg src0, fs_reg src1);
 327    bool try_emit_saturate(ir_expression *ir);
 328    bool try_emit_mad(ir_expression *ir, int mul_arg);
 329    void emit_bool_to_cond_code(ir_rvalue *condition);
 330    void emit_if_gen6(ir_if *ir);
 331    void emit_unspill(fs_inst *inst, fs_reg reg, uint32_t spill_offset);
 332
 333    void emit_fragment_program_code();
 334    void setup_fp_regs();
 335    fs_reg get_fp_src_reg(const prog_src_register *src);
 336    fs_reg get_fp_dst_reg(const prog_dst_register *dst);
 337    void emit_fp_alu1(enum opcode opcode,
 338                      const struct prog_instruction *fpi,
 339                      fs_reg dst, fs_reg src);
 340    void emit_fp_alu2(enum opcode opcode,
 341                      const struct prog_instruction *fpi,
 342                      fs_reg dst, fs_reg src0, fs_reg src1);
 343    void emit_fp_scalar_write(const struct prog_instruction *fpi,
 344                              fs_reg dst, fs_reg src);
 345    void emit_fp_scalar_math(enum opcode opcode,
 346                             const struct prog_instruction *fpi,
 347                             fs_reg dst, fs_reg src);
 348
 349    void emit_fp_minmax(const struct prog_instruction *fpi,
 350                        fs_reg dst, fs_reg src0, fs_reg src1);
 351
 352    void emit_fp_sop(uint32_t conditional_mod,
 353                     const struct prog_instruction *fpi,
 354                     fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
 355
 356    void emit_color_write(int target, int index, int first_color_mrf);
 357    void emit_fb_writes();
 358    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 359                                fs_reg dst,
 360                                fs_reg src,
 361                                fs_inst *pre_rhs_inst,
 362                                fs_inst *last_rhs_inst);
 363    void emit_assignment_writes(fs_reg &l, fs_reg &r,
 364                                const glsl_type *type, bool predicated);
 365    void resolve_ud_negate(fs_reg *reg);
 366    void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
 367
 368    struct brw_reg interp_reg(int location, int channel);
 369    int setup_uniform_values(int loc, const glsl_type *type);
 370    void setup_builtin_uniform_values(ir_variable *ir);
 371    int implied_mrf_writes(fs_inst *inst);
 372
 373    void dump_instructions();
 374    void dump_instruction(fs_inst *inst);
 375
 376    const struct gl_fragment_program *fp;
 377    struct brw_wm_compile *c;
 378
 379    /* Delayed setup of c->prog_data.params[] due to realloc of
 380     * ParamValues[] during compile.
 381     */
 382    int param_index[MAX_UNIFORMS * 4];
 383    int param_offset[MAX_UNIFORMS * 4];
 384
 385    int *virtual_grf_sizes;
 386    int virtual_grf_count;
 387    int virtual_grf_array_size;
 388    int *virtual_grf_def;
 389    int *virtual_grf_use;
 390    bool live_intervals_valid;
 391
 392    /* This is the map from UNIFORM hw_reg + reg_offset as generated by
 393     * the visitor to the packed uniform number after
 394     * remove_dead_constants() that represents the actual uploaded
 395     * uniform index.
 396     */
 397    int *params_remap;
 398
 399    struct hash_table *variable_ht;
 400    fs_reg frag_depth;
 401    fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
 402    unsigned output_components[BRW_MAX_DRAW_BUFFERS];
 403    fs_reg dual_src_output;
 404    int first_non_payload_grf;
 405    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 406    int max_grf;
 407    int urb_setup[FRAG_ATTRIB_MAX];
 408
 409    fs_reg *fp_temp_regs;
 410    fs_reg *fp_input_regs;
 411
 412    /** @{ debug annotation info */
 413    const char *current_annotation;
 414    const void *base_ir;
 415    /** @} */
 416
 417    bool failed;
 418    char *fail_msg;
 419
 420    /* Result of last visit() method. */
 421    fs_reg result;
 422
 423    fs_reg pixel_x;
 424    fs_reg pixel_y;
 425    fs_reg wpos_w;
 426    fs_reg pixel_w;
 427    fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 428    fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 429
 430    int grf_used;
 431
 432    const unsigned dispatch_width; /**< 8 or 16 */
 433
 434    int force_uncompressed_stack;
 435    int force_sechalf_stack;
 436 };
 437
 438 /**
 439  * The fragment shader code generator.
 440  *
 441  * Translates FS IR to actual i965 assembly code.
 442  */
 443 class fs_generator
 444 {
 445 public:
 446    fs_generator(struct brw_context *brw,
 447                 struct brw_wm_compile *c,
 448                 struct gl_shader_program *prog,
 449                 struct gl_fragment_program *fp,
 450                 bool dual_source_output);
 451    ~fs_generator();
 452
 453    const unsigned *generate_assembly(exec_list *simd8_instructions,
 454                                      exec_list *simd16_instructions,
 455                                      unsigned *assembly_size);
 456
 457 private:
 458    void generate_code(exec_list *instructions);
 459    void generate_fb_write(fs_inst *inst);
 460    void generate_pixel_xy(struct brw_reg dst, bool is_x);
 461    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 462                          struct brw_reg *src);
 463    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 464    void generate_math1_gen7(fs_inst *inst,
 465                             struct brw_reg dst,
 466                             struct brw_reg src);
 467    void generate_math2_gen7(fs_inst *inst,
 468                             struct brw_reg dst,
 469                             struct brw_reg src0,
 470                             struct brw_reg src1);
 471    void generate_math1_gen6(fs_inst *inst,
 472                             struct brw_reg dst,
 473                             struct brw_reg src);
 474    void generate_math2_gen6(fs_inst *inst,
 475                             struct brw_reg dst,
 476                             struct brw_reg src0,
 477                             struct brw_reg src1);
 478    void generate_math_gen4(fs_inst *inst,
 479                            struct brw_reg dst,
 480                            struct brw_reg src);
 481    void generate_discard(fs_inst *inst);
 482    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 483    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 484                      bool negate_value);
 485    void generate_spill(fs_inst *inst, struct brw_reg src);
 486    void generate_unspill(fs_inst *inst, struct brw_reg dst);
 487    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 488                                             struct brw_reg index,
 489                                             struct brw_reg offset);
 490    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 491                                             struct brw_reg index);
 492    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 493                                                  struct brw_reg dst,
 494                                                  struct brw_reg index,
 495                                                  struct brw_reg offset);
 496    void generate_mov_dispatch_to_flags();
 497
 498    struct brw_context *brw;
 499    struct intel_context *intel;
 500    struct gl_context *ctx;
 501
 502    struct brw_compile *p;
 503    struct brw_wm_compile *c;
 504
 505    struct gl_shader_program *prog;
 506    struct gl_shader *shader;
 507    const struct gl_fragment_program *fp;
 508
 509    unsigned dispatch_width; /**< 8 or 16 */
 510
 511    bool dual_source_output;
 512    void *mem_ctx;
 513 };
 514
 515 bool brw_do_channel_expressions(struct exec_list *instructions);
 516 bool brw_do_vector_splitting(struct exec_list *instructions);
 517 bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);