src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31
  32 extern "C" {
  33
  34 #include <sys/types.h>
  35
  36 #include "main/macros.h"
  37 #include "main/shaderobj.h"
  38 #include "main/uniforms.h"
  39 #include "program/prog_parameter.h"
  40 #include "program/prog_print.h"
  41 #include "program/prog_optimize.h"
  42 #include "program/register_allocate.h"
  43 #include "program/sampler.h"
  44 #include "program/hash_table.h"
  45 #include "brw_context.h"
  46 #include "brw_eu.h"
  47 #include "brw_wm.h"
  48 #include "brw_shader.h"
  49 }
  50 #include "glsl/glsl_types.h"
  51 #include "glsl/ir.h"
  52
  53 class bblock_t;
  54 namespace {
  55    struct acp_entry;
  56 }
  57
  58 namespace brw {
  59    class fs_live_variables;
  60 }
  61
  62 class fs_reg {
  63 public:
  64    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  65
  66    void init();
  67
  68    fs_reg();
  69    fs_reg(float f);
  70    fs_reg(int32_t i);
  71    fs_reg(uint32_t u);
  72    fs_reg(struct brw_reg fixed_hw_reg);
  73    fs_reg(enum register_file file, int reg);
  74    fs_reg(enum register_file file, int reg, uint32_t type);
  75    fs_reg(class fs_visitor *v, const struct glsl_type *type);
  76
  77    bool equals(const fs_reg &r) const;
  78    bool is_zero() const;
  79    bool is_one() const;
  80    bool is_null() const;
  81    bool is_valid_3src() const;
  82    fs_reg retype(uint32_t type);
  83
  84    /** Register file: GRF, MRF, IMM. */
  85    enum register_file file;
  86    /**
  87     * Register number.  For MRF, it's the hardware register.  For
  88     * GRF, it's a virtual register number until register allocation
  89     */
  90    int reg;
  91    /**
  92     * Offset from the start of the contiguous register block.
  93     *
  94     * For pre-register-allocation GRFs, this is in units of a float per pixel
  95     * (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode).
  96     * For uniforms, this is in units of 1 float.
  97     */
  98    int reg_offset;
  99    /** Register type.  BRW_REGISTER_TYPE_* */
 100    int type;
 101    bool negate;
 102    bool abs;
 103    bool sechalf;
 104    struct brw_reg fixed_hw_reg;
 105    int smear; /* -1, or a channel of the reg to smear to all channels. */
 106
 107    /** Value for file == IMM */
 108    union {
 109       int32_t i;
 110       uint32_t u;
 111       float f;
 112    } imm;
 113
 114    fs_reg *reladdr;
 115 };
 116
 117 static const fs_reg reg_undef;
 118 static const fs_reg reg_null_f(retype(brw_null_reg(), BRW_REGISTER_TYPE_F));
 119 static const fs_reg reg_null_d(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 120 static const fs_reg reg_null_ud(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 121
 122 class ip_record : public exec_node {
 123 public:
 124    DECLARE_RALLOC_CXX_OPERATORS(ip_record)
 125
 126    ip_record(int ip)
 127    {
 128       this->ip = ip;
 129    }
 130
 131    int ip;
 132 };
 133
 134 class fs_inst : public backend_instruction {
 135 public:
 136    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 137
 138    void init();
 139
 140    fs_inst();
 141    fs_inst(enum opcode opcode);
 142    fs_inst(enum opcode opcode, fs_reg dst);
 143    fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0);
 144    fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
 145    fs_inst(enum opcode opcode, fs_reg dst,
 146            fs_reg src0, fs_reg src1,fs_reg src2);
 147
 148    bool equals(fs_inst *inst);
 149    bool overwrites_reg(const fs_reg &reg);
 150    bool is_send_from_grf();
 151    bool is_partial_write();
 152    int regs_read(fs_visitor *v, int arg);
 153
 154    fs_reg dst;
 155    fs_reg src[3];
 156    bool saturate;
 157    int conditional_mod; /**< BRW_CONDITIONAL_* */
 158
 159    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 160     * mod and predication.
 161     */
 162    uint8_t flag_subreg;
 163
 164    int mlen; /**< SEND message length */
 165    int regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
 166    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 167    uint32_t texture_offset; /**< Texture offset bitfield */
 168    int sampler;
 169    int target; /**< MRT target. */
 170    bool eot;
 171    bool header_present;
 172    bool shadow_compare;
 173    bool force_uncompressed;
 174    bool force_sechalf;
 175    bool force_writemask_all;
 176    uint32_t offset; /* spill/unspill offset */
 177
 178    /** @{
 179     * Annotation for the generated IR.  One of the two can be set.
 180     */
 181    const void *ir;
 182    const char *annotation;
 183    /** @} */
 184 };
 185
 186 /**
 187  * The fragment shader front-end.
 188  *
 189  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
 190  */
 191 class fs_visitor : public backend_visitor
 192 {
 193 public:
 194
 195    fs_visitor(struct brw_context *brw,
 196               struct brw_wm_compile *c,
 197               struct gl_shader_program *shader_prog,
 198               struct gl_fragment_program *fp,
 199               unsigned dispatch_width);
 200    ~fs_visitor();
 201
 202    fs_reg *variable_storage(ir_variable *var);
 203    int virtual_grf_alloc(int size);
 204    void import_uniforms(fs_visitor *v);
 205
 206    void visit(ir_variable *ir);
 207    void visit(ir_assignment *ir);
 208    void visit(ir_dereference_variable *ir);
 209    void visit(ir_dereference_record *ir);
 210    void visit(ir_dereference_array *ir);
 211    void visit(ir_expression *ir);
 212    void visit(ir_texture *ir);
 213    void visit(ir_if *ir);
 214    void visit(ir_constant *ir);
 215    void visit(ir_swizzle *ir);
 216    void visit(ir_return *ir);
 217    void visit(ir_loop *ir);
 218    void visit(ir_loop_jump *ir);
 219    void visit(ir_discard *ir);
 220    void visit(ir_call *ir);
 221    void visit(ir_function *ir);
 222    void visit(ir_function_signature *ir);
 223    void visit(ir_emit_vertex *);
 224    void visit(ir_end_primitive *);
 225
 226    uint32_t gather_channel(ir_texture *ir, int sampler);
 227    void swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler);
 228
 229    bool can_do_source_mods(fs_inst *inst);
 230
 231    fs_inst *emit(fs_inst inst);
 232    fs_inst *emit(fs_inst *inst);
 233    void emit(exec_list list);
 234
 235    fs_inst *emit(enum opcode opcode);
 236    fs_inst *emit(enum opcode opcode, fs_reg dst);
 237    fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0);
 238    fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
 239    fs_inst *emit(enum opcode opcode, fs_reg dst,
 240                  fs_reg src0, fs_reg src1, fs_reg src2);
 241
 242    fs_inst *MOV(fs_reg dst, fs_reg src);
 243    fs_inst *NOT(fs_reg dst, fs_reg src);
 244    fs_inst *RNDD(fs_reg dst, fs_reg src);
 245    fs_inst *RNDE(fs_reg dst, fs_reg src);
 246    fs_inst *RNDZ(fs_reg dst, fs_reg src);
 247    fs_inst *FRC(fs_reg dst, fs_reg src);
 248    fs_inst *ADD(fs_reg dst, fs_reg src0, fs_reg src1);
 249    fs_inst *MUL(fs_reg dst, fs_reg src0, fs_reg src1);
 250    fs_inst *MACH(fs_reg dst, fs_reg src0, fs_reg src1);
 251    fs_inst *MAC(fs_reg dst, fs_reg src0, fs_reg src1);
 252    fs_inst *SHL(fs_reg dst, fs_reg src0, fs_reg src1);
 253    fs_inst *SHR(fs_reg dst, fs_reg src0, fs_reg src1);
 254    fs_inst *ASR(fs_reg dst, fs_reg src0, fs_reg src1);
 255    fs_inst *AND(fs_reg dst, fs_reg src0, fs_reg src1);
 256    fs_inst *OR(fs_reg dst, fs_reg src0, fs_reg src1);
 257    fs_inst *XOR(fs_reg dst, fs_reg src0, fs_reg src1);
 258    fs_inst *IF(uint32_t predicate);
 259    fs_inst *IF(fs_reg src0, fs_reg src1, uint32_t condition);
 260    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 261                 uint32_t condition);
 262    fs_inst *LRP(fs_reg dst, fs_reg a, fs_reg y, fs_reg x);
 263    fs_inst *DEP_RESOLVE_MOV(int grf);
 264    fs_inst *BFREV(fs_reg dst, fs_reg value);
 265    fs_inst *BFE(fs_reg dst, fs_reg bits, fs_reg offset, fs_reg value);
 266    fs_inst *BFI1(fs_reg dst, fs_reg bits, fs_reg offset);
 267    fs_inst *BFI2(fs_reg dst, fs_reg bfi1_dst, fs_reg insert, fs_reg base);
 268    fs_inst *FBH(fs_reg dst, fs_reg value);
 269    fs_inst *FBL(fs_reg dst, fs_reg value);
 270    fs_inst *CBIT(fs_reg dst, fs_reg value);
 271    fs_inst *MAD(fs_reg dst, fs_reg c, fs_reg b, fs_reg a);
 272    fs_inst *ADDC(fs_reg dst, fs_reg src0, fs_reg src1);
 273    fs_inst *SUBB(fs_reg dst, fs_reg src0, fs_reg src1);
 274
 275    int type_size(const struct glsl_type *type);
 276    fs_inst *get_instruction_generating_reg(fs_inst *start,
 277                                            fs_inst *end,
 278                                            fs_reg reg);
 279
 280    exec_list VARYING_PULL_CONSTANT_LOAD(fs_reg dst, fs_reg surf_index,
 281                                         fs_reg varying_offset,
 282                                         uint32_t const_offset);
 283
 284    bool run();
 285    void assign_binding_table_offsets();
 286    void setup_payload_gen4();
 287    void setup_payload_gen6();
 288    void assign_curb_setup();
 289    void calculate_urb_setup();
 290    void assign_urb_setup();
 291    bool assign_regs();
 292    void assign_regs_trivial();
 293    void get_used_mrfs(bool *mrf_used);
 294    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 295                                    int first_payload_node);
 296    void setup_mrf_hack_interference(struct ra_graph *g,
 297                                     int first_mrf_hack_node);
 298    int choose_spill_reg(struct ra_graph *g);
 299    void spill_reg(int spill_reg);
 300    void split_virtual_grfs();
 301    void compact_virtual_grfs();
 302    void move_uniform_array_access_to_pull_constants();
 303    void setup_pull_constants();
 304    void invalidate_live_intervals();
 305    void calculate_live_intervals();
 306    bool opt_algebraic();
 307    bool opt_cse();
 308    bool opt_cse_local(bblock_t *block, exec_list *aeb);
 309    bool opt_copy_propagate();
 310    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 311    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 312    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 313                                  exec_list *acp);
 314    bool register_coalesce();
 315    bool register_coalesce_2();
 316    bool compute_to_mrf();
 317    bool dead_code_eliminate();
 318    bool dead_code_eliminate_local();
 319    bool remove_dead_constants();
 320    bool remove_duplicate_mrf_writes();
 321    bool virtual_grf_interferes(int a, int b);
 322    void schedule_instructions(bool post_reg_alloc);
 323    void insert_gen4_send_dependency_workarounds();
 324    void insert_gen4_pre_send_dependency_workarounds(fs_inst *inst);
 325    void insert_gen4_post_send_dependency_workarounds(fs_inst *inst);
 326    void fail(const char *msg, ...);
 327    void lower_uniform_pull_constant_loads();
 328
 329    void push_force_uncompressed();
 330    void pop_force_uncompressed();
 331    void push_force_sechalf();
 332    void pop_force_sechalf();
 333
 334    void emit_dummy_fs();
 335    fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
 336    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 337                          glsl_interp_qualifier interpolation_mode,
 338                          bool is_centroid);
 339    fs_reg *emit_frontfacing_interpolation(ir_variable *ir);
 340    fs_reg *emit_general_interpolation(ir_variable *ir);
 341    void emit_interpolation_setup_gen4();
 342    void emit_interpolation_setup_gen6();
 343    fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
 344                            bool is_rect, int sampler, int texunit);
 345    fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 346                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2);
 347    fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 348                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 349                               fs_reg sample_index);
 350    fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
 351                               fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
 352                               fs_reg sample_index);
 353    fs_reg fix_math_operand(fs_reg src);
 354    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 355    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 356    void emit_lrp(fs_reg dst, fs_reg x, fs_reg y, fs_reg a);
 357    void emit_minmax(uint32_t conditionalmod, fs_reg dst,
 358                     fs_reg src0, fs_reg src1);
 359    bool try_emit_saturate(ir_expression *ir);
 360    bool try_emit_mad(ir_expression *ir, int mul_arg);
 361    void try_replace_with_sel();
 362    void emit_bool_to_cond_code(ir_rvalue *condition);
 363    void emit_if_gen6(ir_if *ir);
 364    void emit_unspill(fs_inst *inst, fs_reg reg, uint32_t spill_offset,
 365                      int count);
 366
 367    void emit_fragment_program_code();
 368    void setup_fp_regs();
 369    fs_reg get_fp_src_reg(const prog_src_register *src);
 370    fs_reg get_fp_dst_reg(const prog_dst_register *dst);
 371    void emit_fp_alu1(enum opcode opcode,
 372                      const struct prog_instruction *fpi,
 373                      fs_reg dst, fs_reg src);
 374    void emit_fp_alu2(enum opcode opcode,
 375                      const struct prog_instruction *fpi,
 376                      fs_reg dst, fs_reg src0, fs_reg src1);
 377    void emit_fp_scalar_write(const struct prog_instruction *fpi,
 378                              fs_reg dst, fs_reg src);
 379    void emit_fp_scalar_math(enum opcode opcode,
 380                             const struct prog_instruction *fpi,
 381                             fs_reg dst, fs_reg src);
 382
 383    void emit_fp_minmax(const struct prog_instruction *fpi,
 384                        fs_reg dst, fs_reg src0, fs_reg src1);
 385
 386    void emit_fp_sop(uint32_t conditional_mod,
 387                     const struct prog_instruction *fpi,
 388                     fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
 389
 390    void emit_color_write(int target, int index, int first_color_mrf);
 391    void emit_fb_writes();
 392
 393    void emit_shader_time_begin();
 394    void emit_shader_time_end();
 395    void emit_shader_time_write(enum shader_time_shader_type type,
 396                                fs_reg value);
 397
 398    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 399                                fs_reg dst,
 400                                fs_reg src,
 401                                fs_inst *pre_rhs_inst,
 402                                fs_inst *last_rhs_inst);
 403    void emit_assignment_writes(fs_reg &l, fs_reg &r,
 404                                const glsl_type *type, bool predicated);
 405    void resolve_ud_negate(fs_reg *reg);
 406    void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
 407
 408    fs_reg get_timestamp();
 409
 410    struct brw_reg interp_reg(int location, int channel);
 411    void setup_uniform_values(ir_variable *ir);
 412    void setup_builtin_uniform_values(ir_variable *ir);
 413    int implied_mrf_writes(fs_inst *inst);
 414
 415    void dump_instruction(backend_instruction *inst);
 416
 417    struct gl_fragment_program *fp;
 418    struct brw_wm_compile *c;
 419    unsigned int sanity_param_count;
 420
 421    int param_size[MAX_UNIFORMS * 4];
 422
 423    int *virtual_grf_sizes;
 424    int virtual_grf_count;
 425    int virtual_grf_array_size;
 426    int *virtual_grf_start;
 427    int *virtual_grf_end;
 428    brw::fs_live_variables *live_intervals;
 429
 430    /* This is the map from UNIFORM hw_reg + reg_offset as generated by
 431     * the visitor to the packed uniform number after
 432     * remove_dead_constants() that represents the actual uploaded
 433     * uniform index.
 434     */
 435    int *params_remap;
 436    int nr_params_remap;
 437
 438    struct hash_table *variable_ht;
 439    fs_reg frag_depth;
 440    fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
 441    unsigned output_components[BRW_MAX_DRAW_BUFFERS];
 442    fs_reg dual_src_output;
 443    int first_non_payload_grf;
 444    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 445    int max_grf;
 446
 447    fs_reg *fp_temp_regs;
 448    fs_reg *fp_input_regs;
 449
 450    /** @{ debug annotation info */
 451    const char *current_annotation;
 452    const void *base_ir;
 453    /** @} */
 454
 455    bool failed;
 456    char *fail_msg;
 457
 458    /* Result of last visit() method. */
 459    fs_reg result;
 460
 461    fs_reg pixel_x;
 462    fs_reg pixel_y;
 463    fs_reg wpos_w;
 464    fs_reg pixel_w;
 465    fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 466    fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 467    fs_reg shader_start_time;
 468
 469    int grf_used;
 470    bool spilled_any_registers;
 471
 472    const unsigned dispatch_width; /**< 8 or 16 */
 473
 474    int force_uncompressed_stack;
 475    int force_sechalf_stack;
 476 };
 477
 478 /**
 479  * The fragment shader code generator.
 480  *
 481  * Translates FS IR to actual i965 assembly code.
 482  */
 483 class fs_generator
 484 {
 485 public:
 486    fs_generator(struct brw_context *brw,
 487                 struct brw_wm_compile *c,
 488                 struct gl_shader_program *prog,
 489                 struct gl_fragment_program *fp,
 490                 bool dual_source_output);
 491    ~fs_generator();
 492
 493    const unsigned *generate_assembly(exec_list *simd8_instructions,
 494                                      exec_list *simd16_instructions,
 495                                      unsigned *assembly_size);
 496
 497 private:
 498    void generate_code(exec_list *instructions);
 499    void generate_fb_write(fs_inst *inst);
 500    void generate_pixel_xy(struct brw_reg dst, bool is_x);
 501    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 502                          struct brw_reg *src);
 503    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 504    void generate_math1_gen7(fs_inst *inst,
 505                             struct brw_reg dst,
 506                             struct brw_reg src);
 507    void generate_math2_gen7(fs_inst *inst,
 508                             struct brw_reg dst,
 509                             struct brw_reg src0,
 510                             struct brw_reg src1);
 511    void generate_math1_gen6(fs_inst *inst,
 512                             struct brw_reg dst,
 513                             struct brw_reg src);
 514    void generate_math2_gen6(fs_inst *inst,
 515                             struct brw_reg dst,
 516                             struct brw_reg src0,
 517                             struct brw_reg src1);
 518    void generate_math_gen4(fs_inst *inst,
 519                            struct brw_reg dst,
 520                            struct brw_reg src);
 521    void generate_math_g45(fs_inst *inst,
 522                           struct brw_reg dst,
 523                           struct brw_reg src);
 524    void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
 525    void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 526                      bool negate_value);
 527    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 528    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 529    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 530    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 531                                             struct brw_reg index,
 532                                             struct brw_reg offset);
 533    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 534                                                  struct brw_reg dst,
 535                                                  struct brw_reg surf_index,
 536                                                  struct brw_reg offset);
 537    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 538                                             struct brw_reg index,
 539                                             struct brw_reg offset);
 540    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 541                                                  struct brw_reg dst,
 542                                                  struct brw_reg index,
 543                                                  struct brw_reg offset);
 544    void generate_mov_dispatch_to_flags(fs_inst *inst);
 545    void generate_set_simd4x2_offset(fs_inst *inst,
 546                                     struct brw_reg dst,
 547                                     struct brw_reg offset);
 548    void generate_discard_jump(fs_inst *inst);
 549
 550    void generate_pack_half_2x16_split(fs_inst *inst,
 551                                       struct brw_reg dst,
 552                                       struct brw_reg x,
 553                                       struct brw_reg y);
 554    void generate_unpack_half_2x16_split(fs_inst *inst,
 555                                         struct brw_reg dst,
 556                                         struct brw_reg src);
 557
 558    void generate_shader_time_add(fs_inst *inst,
 559                                  struct brw_reg payload,
 560                                  struct brw_reg offset,
 561                                  struct brw_reg value);
 562
 563    void generate_untyped_atomic(fs_inst *inst,
 564                                 struct brw_reg dst,
 565                                 struct brw_reg atomic_op,
 566                                 struct brw_reg surf_index);
 567
 568    void generate_untyped_surface_read(fs_inst *inst,
 569                                       struct brw_reg dst,
 570                                       struct brw_reg surf_index);
 571
 572    void mark_surface_used(unsigned surf_index);
 573
 574    void patch_discard_jumps_to_fb_writes();
 575
 576    struct brw_context *brw;
 577    struct gl_context *ctx;
 578
 579    struct brw_compile *p;
 580    struct brw_wm_compile *c;
 581
 582    struct gl_shader_program *prog;
 583    struct gl_shader *shader;
 584    const struct gl_fragment_program *fp;
 585
 586    unsigned dispatch_width; /**< 8 or 16 */
 587
 588    exec_list discard_halt_patches;
 589    bool dual_source_output;
 590    void *mem_ctx;
 591 };
 592
 593 bool brw_do_channel_expressions(struct exec_list *instructions);
 594 bool brw_do_vector_splitting(struct exec_list *instructions);
 595 bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);