i965/fs: Move class functions from the header to .cpp files.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs.h
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #pragma once
29
30 #include "brw_shader.h"
31
32 extern "C" {
33
34 #include <sys/types.h>
35
36 #include "main/macros.h"
37 #include "main/shaderobj.h"
38 #include "main/uniforms.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/prog_optimize.h"
42 #include "program/register_allocate.h"
43 #include "program/sampler.h"
44 #include "program/hash_table.h"
45 #include "brw_context.h"
46 #include "brw_eu.h"
47 #include "brw_wm.h"
48 }
49 #include "glsl/glsl_types.h"
50 #include "glsl/ir.h"
51
52 class fs_bblock;
53 namespace {
54 class acp_entry;
55 }
56
57 enum register_file {
58 BAD_FILE,
59 ARF,
60 GRF,
61 MRF,
62 IMM,
63 FIXED_HW_REG, /* a struct brw_reg */
64 UNIFORM, /* prog_data->params[reg] */
65 };
66
67 class fs_reg {
68 public:
69 /* Callers of this ralloc-based new need not call delete. It's
70 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
71 static void* operator new(size_t size, void *ctx)
72 {
73 void *node;
74
75 node = ralloc_size(ctx, size);
76 assert(node != NULL);
77
78 return node;
79 }
80
81 void init();
82
83 fs_reg();
84 fs_reg(float f);
85 fs_reg(int32_t i);
86 fs_reg(uint32_t u);
87 fs_reg(struct brw_reg fixed_hw_reg);
88 fs_reg(enum register_file file, int reg);
89 fs_reg(enum register_file file, int reg, uint32_t type);
90 fs_reg(class fs_visitor *v, const struct glsl_type *type);
91
92 bool equals(const fs_reg &r) const;
93
94 /** Register file: ARF, GRF, MRF, IMM. */
95 enum register_file file;
96 /**
97 * Register number. For ARF/MRF, it's the hardware register. For
98 * GRF, it's a virtual register number until register allocation
99 */
100 int reg;
101 /**
102 * For virtual registers, this is a hardware register offset from
103 * the start of the register block (for example, a constant index
104 * in an array access).
105 */
106 int reg_offset;
107 /** Register type. BRW_REGISTER_TYPE_* */
108 int type;
109 bool negate;
110 bool abs;
111 bool sechalf;
112 struct brw_reg fixed_hw_reg;
113 int smear; /* -1, or a channel of the reg to smear to all channels. */
114
115 /** Value for file == IMM */
116 union {
117 int32_t i;
118 uint32_t u;
119 float f;
120 } imm;
121 };
122
123 static const fs_reg reg_undef;
124 static const fs_reg reg_null_f(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_F);
125 static const fs_reg reg_null_d(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_D);
126
127 class fs_inst : public exec_node {
128 public:
129 /* Callers of this ralloc-based new need not call delete. It's
130 * easier to just ralloc_free 'ctx' (or any of its ancestors). */
131 static void* operator new(size_t size, void *ctx)
132 {
133 void *node;
134
135 node = rzalloc_size(ctx, size);
136 assert(node != NULL);
137
138 return node;
139 }
140
141 void init();
142
143 fs_inst();
144 fs_inst(enum opcode opcode);
145 fs_inst(enum opcode opcode, fs_reg dst);
146 fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0);
147 fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
148 fs_inst(enum opcode opcode, fs_reg dst,
149 fs_reg src0, fs_reg src1,fs_reg src2);
150
151 bool equals(fs_inst *inst);
152 int regs_written();
153 bool is_tex();
154 bool is_math();
155
156 enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
157 fs_reg dst;
158 fs_reg src[3];
159 bool saturate;
160 bool predicated;
161 bool predicate_inverse;
162 int conditional_mod; /**< BRW_CONDITIONAL_* */
163
164 int mlen; /**< SEND message length */
165 int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
166 int sampler;
167 int target; /**< MRT target. */
168 bool eot;
169 bool header_present;
170 bool shadow_compare;
171 bool force_uncompressed;
172 bool force_sechalf;
173 uint32_t offset; /* spill/unspill offset */
174
175 /** @{
176 * Annotation for the generated IR. One of the two can be set.
177 */
178 ir_instruction *ir;
179 const char *annotation;
180 /** @} */
181 };
182
183 class fs_visitor : public ir_visitor
184 {
185 public:
186
187 fs_visitor(struct brw_wm_compile *c, struct gl_shader_program *prog,
188 struct brw_shader *shader);
189 ~fs_visitor();
190
191 fs_reg *variable_storage(ir_variable *var);
192 int virtual_grf_alloc(int size);
193 void import_uniforms(fs_visitor *v);
194
195 void visit(ir_variable *ir);
196 void visit(ir_assignment *ir);
197 void visit(ir_dereference_variable *ir);
198 void visit(ir_dereference_record *ir);
199 void visit(ir_dereference_array *ir);
200 void visit(ir_expression *ir);
201 void visit(ir_texture *ir);
202 void visit(ir_if *ir);
203 void visit(ir_constant *ir);
204 void visit(ir_swizzle *ir);
205 void visit(ir_return *ir);
206 void visit(ir_loop *ir);
207 void visit(ir_loop_jump *ir);
208 void visit(ir_discard *ir);
209 void visit(ir_call *ir);
210 void visit(ir_function *ir);
211 void visit(ir_function_signature *ir);
212
213 void swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler);
214
215 fs_inst *emit(fs_inst inst);
216
217 fs_inst *emit(enum opcode opcode);
218 fs_inst *emit(enum opcode opcode, fs_reg dst);
219 fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0);
220 fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
221 fs_inst *emit(enum opcode opcode, fs_reg dst,
222 fs_reg src0, fs_reg src1, fs_reg src2);
223
224 int type_size(const struct glsl_type *type);
225 fs_inst *get_instruction_generating_reg(fs_inst *start,
226 fs_inst *end,
227 fs_reg reg);
228
229 bool run();
230 void setup_paramvalues_refs();
231 void assign_curb_setup();
232 void calculate_urb_setup();
233 void assign_urb_setup();
234 bool assign_regs();
235 void assign_regs_trivial();
236 int choose_spill_reg(struct ra_graph *g);
237 void spill_reg(int spill_reg);
238 void split_virtual_grfs();
239 void setup_pull_constants();
240 void calculate_live_intervals();
241 bool propagate_constants();
242 bool opt_algebraic();
243 bool opt_cse();
244 bool opt_cse_local(fs_bblock *block, exec_list *aeb);
245 bool opt_copy_propagate();
246 bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
247 bool opt_copy_propagate_local(void *mem_ctx, fs_bblock *block,
248 exec_list *acp);
249 bool register_coalesce();
250 bool register_coalesce_2();
251 bool compute_to_mrf();
252 bool dead_code_eliminate();
253 bool remove_dead_constants();
254 bool remove_duplicate_mrf_writes();
255 bool virtual_grf_interferes(int a, int b);
256 void schedule_instructions();
257 void fail(const char *msg, ...);
258
259 void push_force_uncompressed();
260 void pop_force_uncompressed();
261 void push_force_sechalf();
262 void pop_force_sechalf();
263
264 void generate_code();
265 void generate_fb_write(fs_inst *inst);
266 void generate_pixel_xy(struct brw_reg dst, bool is_x);
267 void generate_linterp(fs_inst *inst, struct brw_reg dst,
268 struct brw_reg *src);
269 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
270 void generate_math1_gen7(fs_inst *inst,
271 struct brw_reg dst,
272 struct brw_reg src);
273 void generate_math2_gen7(fs_inst *inst,
274 struct brw_reg dst,
275 struct brw_reg src0,
276 struct brw_reg src1);
277 void generate_math1_gen6(fs_inst *inst,
278 struct brw_reg dst,
279 struct brw_reg src);
280 void generate_math2_gen6(fs_inst *inst,
281 struct brw_reg dst,
282 struct brw_reg src0,
283 struct brw_reg src1);
284 void generate_math_gen4(fs_inst *inst,
285 struct brw_reg dst,
286 struct brw_reg src);
287 void generate_discard(fs_inst *inst);
288 void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
289 void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
290 bool negate_value);
291 void generate_spill(fs_inst *inst, struct brw_reg src);
292 void generate_unspill(fs_inst *inst, struct brw_reg dst);
293 void generate_pull_constant_load(fs_inst *inst, struct brw_reg dst);
294 void generate_mov_dispatch_to_flags();
295
296 void emit_dummy_fs();
297 fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
298 fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
299 glsl_interp_qualifier interpolation_mode,
300 bool is_centroid);
301 fs_reg *emit_frontfacing_interpolation(ir_variable *ir);
302 fs_reg *emit_general_interpolation(ir_variable *ir);
303 void emit_interpolation_setup_gen4();
304 void emit_interpolation_setup_gen6();
305 fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
306 int sampler);
307 fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
308 int sampler);
309 fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
310 int sampler);
311 fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
312 fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
313 bool try_emit_saturate(ir_expression *ir);
314 bool try_emit_mad(ir_expression *ir, int mul_arg);
315 void emit_bool_to_cond_code(ir_rvalue *condition);
316 void emit_if_gen6(ir_if *ir);
317 void emit_unspill(fs_inst *inst, fs_reg reg, uint32_t spill_offset);
318
319 void emit_color_write(int target, int index, int first_color_mrf);
320 void emit_fb_writes();
321 bool try_rewrite_rhs_to_dst(ir_assignment *ir,
322 fs_reg dst,
323 fs_reg src,
324 fs_inst *pre_rhs_inst,
325 fs_inst *last_rhs_inst);
326 void emit_assignment_writes(fs_reg &l, fs_reg &r,
327 const glsl_type *type, bool predicated);
328 void resolve_ud_negate(fs_reg *reg);
329 void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
330
331 struct brw_reg interp_reg(int location, int channel);
332 int setup_uniform_values(int loc, const glsl_type *type);
333 void setup_builtin_uniform_values(ir_variable *ir);
334 int implied_mrf_writes(fs_inst *inst);
335
336 struct brw_context *brw;
337 const struct gl_fragment_program *fp;
338 struct intel_context *intel;
339 struct gl_context *ctx;
340 struct brw_wm_compile *c;
341 struct brw_compile *p;
342 struct brw_shader *shader;
343 struct gl_shader_program *prog;
344 void *mem_ctx;
345 exec_list instructions;
346
347 /* Delayed setup of c->prog_data.params[] due to realloc of
348 * ParamValues[] during compile.
349 */
350 int param_index[MAX_UNIFORMS * 4];
351 int param_offset[MAX_UNIFORMS * 4];
352
353 int *virtual_grf_sizes;
354 int virtual_grf_next;
355 int virtual_grf_array_size;
356 int *virtual_grf_def;
357 int *virtual_grf_use;
358 bool live_intervals_valid;
359
360 /* This is the map from UNIFORM hw_reg + reg_offset as generated by
361 * the visitor to the packed uniform number after
362 * remove_dead_constants() that represents the actual uploaded
363 * uniform index.
364 */
365 int *params_remap;
366
367 struct hash_table *variable_ht;
368 ir_variable *frag_depth;
369 fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
370 unsigned output_components[BRW_MAX_DRAW_BUFFERS];
371 fs_reg dual_src_output;
372 int first_non_payload_grf;
373 int max_grf;
374 int urb_setup[FRAG_ATTRIB_MAX];
375 bool kill_emitted;
376
377 /** @{ debug annotation info */
378 const char *current_annotation;
379 ir_instruction *base_ir;
380 /** @} */
381
382 bool failed;
383 char *fail_msg;
384
385 /* Result of last visit() method. */
386 fs_reg result;
387
388 fs_reg pixel_x;
389 fs_reg pixel_y;
390 fs_reg wpos_w;
391 fs_reg pixel_w;
392 fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
393 fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
394 fs_reg reg_null_cmp;
395
396 int grf_used;
397
398 int force_uncompressed_stack;
399 int force_sechalf_stack;
400
401 class fs_bblock *bblock;
402 };
403
404 bool brw_do_channel_expressions(struct exec_list *instructions);
405 bool brw_do_vector_splitting(struct exec_list *instructions);
406 bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);