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25 * \file brw_wm_channel_expressions.cpp
27 * Breaks vector operations down into operations on each component.
29 * The 965 fragment shader receives 8 or 16 pixels at a time, so each
30 * channel of a vector is laid out as 1 or 2 8-float registers. Each
31 * ALU operation operates on one of those channel registers. As a
32 * result, there is no value to the 965 fragment shader in tracking
33 * "vector" expressions in the sense of GLSL fragment shaders, when
34 * doing a channel at a time may help in constant folding, algebraic
35 * simplification, and reducing the liveness of channel registers.
37 * The exception to the desire to break everything down to floats is
38 * texturing. The texture sampler returns a writemasked masked
39 * 4/8-register sequence containing the texture values. We don't want
40 * to dispatch to the sampler separately for each channel we need, so
41 * we do retain the vector types in that case.
44 #include "compiler/glsl/ir.h"
45 #include "compiler/glsl/ir_expression_flattening.h"
46 #include "compiler/glsl_types.h"
48 class ir_channel_expressions_visitor
: public ir_hierarchical_visitor
{
50 ir_channel_expressions_visitor()
52 this->progress
= false;
56 ir_visitor_status
visit_leave(ir_assignment
*);
58 ir_rvalue
*get_element(ir_variable
*var
, unsigned int element
);
59 void assign(ir_assignment
*ir
, int elem
, ir_rvalue
*val
);
66 channel_expressions_predicate(ir_instruction
*ir
)
68 ir_expression
*expr
= ir
->as_expression();
74 switch (expr
->operation
) {
75 case ir_unop_pack_half_2x16
:
76 case ir_unop_pack_snorm_2x16
:
77 case ir_unop_pack_snorm_4x8
:
78 case ir_unop_pack_unorm_2x16
:
79 case ir_unop_pack_unorm_4x8
:
82 /* these opcodes need to act on the whole vector,
83 * just like texturing.
85 case ir_unop_interpolate_at_centroid
:
86 case ir_binop_interpolate_at_offset
:
87 case ir_binop_interpolate_at_sample
:
88 case ir_unop_pack_double_2x32
:
94 for (i
= 0; i
< expr
->get_num_operands(); i
++) {
95 if (expr
->operands
[i
]->type
->is_vector())
103 brw_do_channel_expressions(exec_list
*instructions
)
105 ir_channel_expressions_visitor v
;
107 /* Pull out any matrix expression to a separate assignment to a
108 * temp. This will make our handling of the breakdown to
109 * operations on the matrix's vector components much easier.
111 do_expression_flattening(instructions
, channel_expressions_predicate
);
113 visit_list_elements(&v
, instructions
);
119 ir_channel_expressions_visitor::get_element(ir_variable
*var
, unsigned int elem
)
121 ir_dereference
*deref
;
123 if (var
->type
->is_scalar())
124 return new(mem_ctx
) ir_dereference_variable(var
);
126 assert(elem
< var
->type
->components());
127 deref
= new(mem_ctx
) ir_dereference_variable(var
);
128 return new(mem_ctx
) ir_swizzle(deref
, elem
, 0, 0, 0, 1);
132 ir_channel_expressions_visitor::assign(ir_assignment
*ir
, int elem
, ir_rvalue
*val
)
134 ir_dereference
*lhs
= ir
->lhs
->clone(mem_ctx
, NULL
);
135 ir_assignment
*assign
;
137 /* This assign-of-expression should have been generated by the
138 * expression flattening visitor (since we never short circit to
139 * not flatten, even for plain assignments of variables), so the
140 * writemask is always full.
142 assert(ir
->write_mask
== (1 << ir
->lhs
->type
->components()) - 1);
144 assign
= new(mem_ctx
) ir_assignment(lhs
, val
, NULL
, (1 << elem
));
145 ir
->insert_before(assign
);
149 ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir
)
151 ir_expression
*expr
= ir
->rhs
->as_expression();
152 bool found_vector
= false;
153 unsigned int i
, vector_elements
= 1;
154 ir_variable
*op_var
[4];
157 return visit_continue
;
160 this->mem_ctx
= ralloc_parent(ir
);
162 for (i
= 0; i
< expr
->get_num_operands(); i
++) {
163 if (expr
->operands
[i
]->type
->is_vector()) {
165 vector_elements
= expr
->operands
[i
]->type
->vector_elements
;
170 return visit_continue
;
172 switch (expr
->operation
) {
173 case ir_unop_pack_half_2x16
:
174 case ir_unop_pack_snorm_2x16
:
175 case ir_unop_pack_snorm_4x8
:
176 case ir_unop_pack_unorm_2x16
:
177 case ir_unop_pack_unorm_4x8
:
178 case ir_unop_interpolate_at_centroid
:
179 case ir_binop_interpolate_at_offset
:
180 case ir_binop_interpolate_at_sample
:
181 /* We scalarize these in NIR, so no need to do it here */
182 case ir_unop_pack_double_2x32
:
183 return visit_continue
;
189 /* Store the expression operands in temps so we can use them
192 for (i
= 0; i
< expr
->get_num_operands(); i
++) {
193 ir_assignment
*assign
;
194 ir_dereference
*deref
;
196 assert(!expr
->operands
[i
]->type
->is_matrix());
198 op_var
[i
] = new(mem_ctx
) ir_variable(expr
->operands
[i
]->type
,
199 "channel_expressions",
201 ir
->insert_before(op_var
[i
]);
203 deref
= new(mem_ctx
) ir_dereference_variable(op_var
[i
]);
204 assign
= new(mem_ctx
) ir_assignment(deref
,
207 ir
->insert_before(assign
);
210 const glsl_type
*element_type
= glsl_type::get_instance(ir
->lhs
->type
->base_type
,
213 /* OK, time to break down this vector operation. */
214 switch (expr
->operation
) {
215 case ir_unop_bit_not
:
216 case ir_unop_logic_not
:
227 case ir_unop_bitcast_i2f
:
228 case ir_unop_bitcast_f2i
:
229 case ir_unop_bitcast_f2u
:
230 case ir_unop_bitcast_u2f
:
252 case ir_unop_round_even
:
256 case ir_unop_dFdx_coarse
:
257 case ir_unop_dFdx_fine
:
259 case ir_unop_dFdy_coarse
:
260 case ir_unop_dFdy_fine
:
261 case ir_unop_bitfield_reverse
:
262 case ir_unop_bit_count
:
263 case ir_unop_find_msb
:
264 case ir_unop_find_lsb
:
265 case ir_unop_saturate
:
266 case ir_unop_subroutine_to_int
:
267 for (i
= 0; i
< vector_elements
; i
++) {
268 ir_rvalue
*op0
= get_element(op_var
[0], i
);
270 assign(ir
, i
, new(mem_ctx
) ir_expression(expr
->operation
,
280 case ir_binop_imul_high
:
283 case ir_binop_borrow
:
288 case ir_binop_lshift
:
289 case ir_binop_rshift
:
290 case ir_binop_bit_and
:
291 case ir_binop_bit_xor
:
292 case ir_binop_bit_or
:
293 case ir_binop_logic_and
:
294 case ir_binop_logic_xor
:
295 case ir_binop_logic_or
:
297 case ir_binop_greater
:
298 case ir_binop_lequal
:
299 case ir_binop_gequal
:
301 case ir_binop_nequal
:
303 for (i
= 0; i
< vector_elements
; i
++) {
304 ir_rvalue
*op0
= get_element(op_var
[0], i
);
305 ir_rvalue
*op1
= get_element(op_var
[1], i
);
307 assign(ir
, i
, new(mem_ctx
) ir_expression(expr
->operation
,
315 ir_expression
*last
= NULL
;
316 for (i
= 0; i
< vector_elements
; i
++) {
317 ir_rvalue
*op0
= get_element(op_var
[0], i
);
318 ir_rvalue
*op1
= get_element(op_var
[1], i
);
321 temp
= new(mem_ctx
) ir_expression(ir_binop_mul
,
326 last
= new(mem_ctx
) ir_expression(ir_binop_add
,
338 case ir_binop_all_equal
:
339 case ir_binop_any_nequal
: {
340 ir_expression
*last
= NULL
;
341 for (i
= 0; i
< vector_elements
; i
++) {
342 ir_rvalue
*op0
= get_element(op_var
[0], i
);
343 ir_rvalue
*op1
= get_element(op_var
[1], i
);
345 ir_expression_operation join
;
347 if (expr
->operation
== ir_binop_all_equal
)
348 join
= ir_binop_logic_and
;
350 join
= ir_binop_logic_or
;
352 temp
= new(mem_ctx
) ir_expression(expr
->operation
,
357 last
= new(mem_ctx
) ir_expression(join
,
369 unreachable("noise should have been broken down to function call");
371 case ir_binop_ubo_load
:
372 case ir_unop_get_buffer_size
:
373 unreachable("not yet supported");
378 case ir_triop_bitfield_extract
:
379 for (i
= 0; i
< vector_elements
; i
++) {
380 ir_rvalue
*op0
= get_element(op_var
[0], i
);
381 ir_rvalue
*op1
= get_element(op_var
[1], i
);
382 ir_rvalue
*op2
= get_element(op_var
[2], i
);
384 assign(ir
, i
, new(mem_ctx
) ir_expression(expr
->operation
,
392 case ir_quadop_bitfield_insert
:
393 for (i
= 0; i
< vector_elements
; i
++) {
394 ir_rvalue
*op0
= get_element(op_var
[0], i
);
395 ir_rvalue
*op1
= get_element(op_var
[1], i
);
396 ir_rvalue
*op2
= get_element(op_var
[2], i
);
397 ir_rvalue
*op3
= get_element(op_var
[3], i
);
399 assign(ir
, i
, new(mem_ctx
) ir_expression(expr
->operation
,
408 case ir_unop_pack_snorm_2x16
:
409 case ir_unop_pack_snorm_4x8
:
410 case ir_unop_pack_unorm_2x16
:
411 case ir_unop_pack_unorm_4x8
:
412 case ir_unop_pack_half_2x16
:
413 case ir_unop_unpack_snorm_2x16
:
414 case ir_unop_unpack_snorm_4x8
:
415 case ir_unop_unpack_unorm_2x16
:
416 case ir_unop_unpack_unorm_4x8
:
417 case ir_unop_unpack_half_2x16
:
418 case ir_binop_vector_extract
:
419 case ir_triop_vector_insert
:
420 case ir_quadop_vector
:
421 case ir_unop_ssbo_unsized_array_length
:
422 unreachable("should have been lowered");
424 case ir_unop_interpolate_at_centroid
:
425 case ir_binop_interpolate_at_offset
:
426 case ir_binop_interpolate_at_sample
:
427 case ir_unop_unpack_double_2x32
:
428 unreachable("not reached: expression operates on scalars only");
430 case ir_unop_pack_double_2x32
:
431 unreachable("not reached: to be lowered in NIR, should've been skipped");
433 case ir_unop_frexp_sig
:
434 case ir_unop_frexp_exp
:
435 unreachable("should have been lowered by lower_instructions");
437 case ir_unop_vote_any
:
438 case ir_unop_vote_all
:
439 case ir_unop_vote_eq
:
440 unreachable("unsupported");
444 this->progress
= true;
446 return visit_continue
;