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25 * \file brw_wm_channel_expressions.cpp
27 * Breaks vector operations down into operations on each component.
29 * The 965 fragment shader receives 8 or 16 pixels at a time, so each
30 * channel of a vector is laid out as 1 or 2 8-float registers. Each
31 * ALU operation operates on one of those channel registers. As a
32 * result, there is no value to the 965 fragment shader in tracking
33 * "vector" expressions in the sense of GLSL fragment shaders, when
34 * doing a channel at a time may help in constant folding, algebraic
35 * simplification, and reducing the liveness of channel registers.
37 * The exception to the desire to break everything down to floats is
38 * texturing. The texture sampler returns a writemasked masked
39 * 4/8-register sequence containing the texture values. We don't want
40 * to dispatch to the sampler separately for each channel we need, so
41 * we do retain the vector types in that case.
44 #include "main/core.h"
47 #include "glsl/ir_expression_flattening.h"
48 #include "glsl/glsl_types.h"
50 class ir_channel_expressions_visitor
: public ir_hierarchical_visitor
{
52 ir_channel_expressions_visitor()
54 this->progress
= false;
58 ir_visitor_status
visit_leave(ir_assignment
*);
60 ir_rvalue
*get_element(ir_variable
*var
, unsigned int element
);
61 void assign(ir_assignment
*ir
, int elem
, ir_rvalue
*val
);
68 channel_expressions_predicate(ir_instruction
*ir
)
70 ir_expression
*expr
= ir
->as_expression();
76 switch (expr
->operation
) {
77 /* these opcodes need to act on the whole vector,
78 * just like texturing.
80 case ir_unop_interpolate_at_centroid
:
81 case ir_binop_interpolate_at_offset
:
82 case ir_binop_interpolate_at_sample
:
88 for (i
= 0; i
< expr
->get_num_operands(); i
++) {
89 if (expr
->operands
[i
]->type
->is_vector())
97 brw_do_channel_expressions(exec_list
*instructions
)
99 ir_channel_expressions_visitor v
;
101 /* Pull out any matrix expression to a separate assignment to a
102 * temp. This will make our handling of the breakdown to
103 * operations on the matrix's vector components much easier.
105 do_expression_flattening(instructions
, channel_expressions_predicate
);
107 visit_list_elements(&v
, instructions
);
113 ir_channel_expressions_visitor::get_element(ir_variable
*var
, unsigned int elem
)
115 ir_dereference
*deref
;
117 if (var
->type
->is_scalar())
118 return new(mem_ctx
) ir_dereference_variable(var
);
120 assert(elem
< var
->type
->components());
121 deref
= new(mem_ctx
) ir_dereference_variable(var
);
122 return new(mem_ctx
) ir_swizzle(deref
, elem
, 0, 0, 0, 1);
126 ir_channel_expressions_visitor::assign(ir_assignment
*ir
, int elem
, ir_rvalue
*val
)
128 ir_dereference
*lhs
= ir
->lhs
->clone(mem_ctx
, NULL
);
129 ir_assignment
*assign
;
131 /* This assign-of-expression should have been generated by the
132 * expression flattening visitor (since we never short circit to
133 * not flatten, even for plain assignments of variables), so the
134 * writemask is always full.
136 assert(ir
->write_mask
== (1 << ir
->lhs
->type
->components()) - 1);
138 assign
= new(mem_ctx
) ir_assignment(lhs
, val
, NULL
, (1 << elem
));
139 ir
->insert_before(assign
);
143 ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir
)
145 ir_expression
*expr
= ir
->rhs
->as_expression();
146 bool found_vector
= false;
147 unsigned int i
, vector_elements
= 1;
148 ir_variable
*op_var
[3];
151 return visit_continue
;
154 this->mem_ctx
= ralloc_parent(ir
);
156 for (i
= 0; i
< expr
->get_num_operands(); i
++) {
157 if (expr
->operands
[i
]->type
->is_vector()) {
159 vector_elements
= expr
->operands
[i
]->type
->vector_elements
;
164 return visit_continue
;
166 switch (expr
->operation
) {
167 case ir_unop_interpolate_at_centroid
:
168 case ir_binop_interpolate_at_offset
:
169 case ir_binop_interpolate_at_sample
:
170 return visit_continue
;
176 /* Store the expression operands in temps so we can use them
179 for (i
= 0; i
< expr
->get_num_operands(); i
++) {
180 ir_assignment
*assign
;
181 ir_dereference
*deref
;
183 assert(!expr
->operands
[i
]->type
->is_matrix());
185 op_var
[i
] = new(mem_ctx
) ir_variable(expr
->operands
[i
]->type
,
186 "channel_expressions",
188 ir
->insert_before(op_var
[i
]);
190 deref
= new(mem_ctx
) ir_dereference_variable(op_var
[i
]);
191 assign
= new(mem_ctx
) ir_assignment(deref
,
194 ir
->insert_before(assign
);
197 const glsl_type
*element_type
= glsl_type::get_instance(ir
->lhs
->type
->base_type
,
200 /* OK, time to break down this vector operation. */
201 switch (expr
->operation
) {
202 case ir_unop_bit_not
:
203 case ir_unop_logic_not
:
214 case ir_unop_bitcast_i2f
:
215 case ir_unop_bitcast_f2i
:
216 case ir_unop_bitcast_f2u
:
217 case ir_unop_bitcast_u2f
:
232 case ir_unop_round_even
:
235 case ir_unop_sin_reduced
:
236 case ir_unop_cos_reduced
:
238 case ir_unop_dFdx_coarse
:
239 case ir_unop_dFdx_fine
:
241 case ir_unop_dFdy_coarse
:
242 case ir_unop_dFdy_fine
:
243 case ir_unop_bitfield_reverse
:
244 case ir_unop_bit_count
:
245 case ir_unop_find_msb
:
246 case ir_unop_find_lsb
:
247 case ir_unop_saturate
:
248 for (i
= 0; i
< vector_elements
; i
++) {
249 ir_rvalue
*op0
= get_element(op_var
[0], i
);
251 assign(ir
, i
, new(mem_ctx
) ir_expression(expr
->operation
,
261 case ir_binop_imul_high
:
264 case ir_binop_borrow
:
269 case ir_binop_lshift
:
270 case ir_binop_rshift
:
271 case ir_binop_bit_and
:
272 case ir_binop_bit_xor
:
273 case ir_binop_bit_or
:
275 case ir_binop_greater
:
276 case ir_binop_lequal
:
277 case ir_binop_gequal
:
279 case ir_binop_nequal
:
280 for (i
= 0; i
< vector_elements
; i
++) {
281 ir_rvalue
*op0
= get_element(op_var
[0], i
);
282 ir_rvalue
*op1
= get_element(op_var
[1], i
);
284 assign(ir
, i
, new(mem_ctx
) ir_expression(expr
->operation
,
293 temp
= new(mem_ctx
) ir_expression(ir_binop_logic_or
,
295 get_element(op_var
[0], 0),
296 get_element(op_var
[0], 1));
298 for (i
= 2; i
< vector_elements
; i
++) {
299 temp
= new(mem_ctx
) ir_expression(ir_binop_logic_or
,
301 get_element(op_var
[0], i
),
309 ir_expression
*last
= NULL
;
310 for (i
= 0; i
< vector_elements
; i
++) {
311 ir_rvalue
*op0
= get_element(op_var
[0], i
);
312 ir_rvalue
*op1
= get_element(op_var
[1], i
);
315 temp
= new(mem_ctx
) ir_expression(ir_binop_mul
,
320 last
= new(mem_ctx
) ir_expression(ir_binop_add
,
332 case ir_binop_logic_and
:
333 case ir_binop_logic_xor
:
334 case ir_binop_logic_or
:
336 fprintf(stderr
, "\n");
337 unreachable("not reached: expression operates on scalars only");
338 case ir_binop_all_equal
:
339 case ir_binop_any_nequal
: {
340 ir_expression
*last
= NULL
;
341 for (i
= 0; i
< vector_elements
; i
++) {
342 ir_rvalue
*op0
= get_element(op_var
[0], i
);
343 ir_rvalue
*op1
= get_element(op_var
[1], i
);
345 ir_expression_operation join
;
347 if (expr
->operation
== ir_binop_all_equal
)
348 join
= ir_binop_logic_and
;
350 join
= ir_binop_logic_or
;
352 temp
= new(mem_ctx
) ir_expression(expr
->operation
,
357 last
= new(mem_ctx
) ir_expression(join
,
369 unreachable("noise should have been broken down to function call");
372 /* Does not need to be scalarized, since its result will be identical
375 ir_rvalue
*op0
= get_element(op_var
[0], 0);
376 ir_rvalue
*op1
= get_element(op_var
[1], 0);
378 assign(ir
, 0, new(mem_ctx
) ir_expression(expr
->operation
,
385 case ir_binop_ubo_load
:
386 unreachable("not yet supported");
391 case ir_triop_bitfield_extract
:
392 for (i
= 0; i
< vector_elements
; i
++) {
393 ir_rvalue
*op0
= get_element(op_var
[0], i
);
394 ir_rvalue
*op1
= get_element(op_var
[1], i
);
395 ir_rvalue
*op2
= get_element(op_var
[2], i
);
397 assign(ir
, i
, new(mem_ctx
) ir_expression(expr
->operation
,
406 /* Only a single BFM is needed for multiple BFIs. */
407 ir_rvalue
*op0
= get_element(op_var
[0], 0);
409 for (i
= 0; i
< vector_elements
; i
++) {
410 ir_rvalue
*op1
= get_element(op_var
[1], i
);
411 ir_rvalue
*op2
= get_element(op_var
[2], i
);
413 assign(ir
, i
, new(mem_ctx
) ir_expression(expr
->operation
,
415 op0
->clone(mem_ctx
, NULL
),
422 case ir_unop_pack_snorm_2x16
:
423 case ir_unop_pack_snorm_4x8
:
424 case ir_unop_pack_unorm_2x16
:
425 case ir_unop_pack_unorm_4x8
:
426 case ir_unop_pack_half_2x16
:
427 case ir_unop_unpack_snorm_2x16
:
428 case ir_unop_unpack_snorm_4x8
:
429 case ir_unop_unpack_unorm_2x16
:
430 case ir_unop_unpack_unorm_4x8
:
431 case ir_unop_unpack_half_2x16
:
433 case ir_binop_vector_extract
:
434 case ir_triop_vector_insert
:
435 case ir_quadop_bitfield_insert
:
436 case ir_quadop_vector
:
437 unreachable("should have been lowered");
439 case ir_unop_unpack_half_2x16_split_x
:
440 case ir_unop_unpack_half_2x16_split_y
:
441 case ir_binop_pack_half_2x16_split
:
442 case ir_unop_interpolate_at_centroid
:
443 case ir_binop_interpolate_at_offset
:
444 case ir_binop_interpolate_at_sample
:
445 unreachable("not reached: expression operates on scalars only");
447 case ir_unop_pack_double_2x32
:
448 case ir_unop_unpack_double_2x32
:
449 case ir_unop_frexp_sig
:
450 case ir_unop_frexp_exp
:
458 unreachable("no fp64 support yet");
462 this->progress
= true;
464 return visit_continue
;