src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /** @file brw_fs_combine_constants.cpp
  25  *
  26  * This file contains the opt_combine_constants() pass that runs after the
  27  * regular optimization loop. It passes over the instruction list and
  28  * selectively promotes immediate values to registers by emitting a mov(1)
  29  * instruction.
  30  *
  31  * This is useful on Gen 7 particularly, because a few instructions can be
  32  * coissued (i.e., issued in the same cycle as another thread on the same EU
  33  * issues an instruction) under some circumstances, one of which is that they
  34  * cannot use immediate values.
  35  */
  36
  37 #include "brw_fs.h"
  38 #include "brw_cfg.h"
  39
  40 using namespace brw;
  41
  42 /* Returns whether an instruction could co-issue if its immediate source were
  43  * replaced with a GRF source.
  44  */
  45 static bool
  46 could_coissue(const struct brw_device_info *devinfo, const fs_inst *inst)
  47 {
  48    if (devinfo->gen != 7)
  49       return false;
  50
  51    switch (inst->opcode) {
  52    case BRW_OPCODE_MOV:
  53    case BRW_OPCODE_CMP:
  54    case BRW_OPCODE_ADD:
  55    case BRW_OPCODE_MUL:
  56       return true;
  57    default:
  58       return false;
  59    }
  60 }
  61
  62 /**
  63  * Returns true for instructions that don't support immediate sources.
  64  */
  65 static bool
  66 must_promote_imm(const struct brw_device_info *devinfo, const fs_inst *inst)
  67 {
  68    switch (inst->opcode) {
  69    case SHADER_OPCODE_POW:
  70       return devinfo->gen < 8;
  71    case BRW_OPCODE_MAD:
  72    case BRW_OPCODE_LRP:
  73       return true;
  74    default:
  75       return false;
  76    }
  77 }
  78
  79 /** A box for putting fs_regs in a linked list. */
  80 struct reg_link {
  81    DECLARE_RALLOC_CXX_OPERATORS(reg_link)
  82
  83    reg_link(fs_reg *reg) : reg(reg) {}
  84
  85    struct exec_node link;
  86    fs_reg *reg;
  87 };
  88
  89 static struct exec_node *
  90 link(void *mem_ctx, fs_reg *reg)
  91 {
  92    reg_link *l = new(mem_ctx) reg_link(reg);
  93    return &l->link;
  94 }
  95
  96 /**
  97  * Information about an immediate value.
  98  */
  99 struct imm {
 100    /** The common ancestor of all blocks using this immediate value. */
 101    bblock_t *block;
 102
 103    /**
 104     * The instruction generating the immediate value, if all uses are contained
 105     * within a single basic block. Otherwise, NULL.
 106     */
 107    fs_inst *inst;
 108
 109    /**
 110     * A list of fs_regs that refer to this immediate.  If we promote it, we'll
 111     * have to patch these up to refer to the new GRF.
 112     */
 113    exec_list *uses;
 114
 115    /** The immediate value.  We currently only handle floats. */
 116    float val;
 117
 118    /**
 119     * The GRF register and subregister number where we've decided to store the
 120     * constant value.
 121     */
 122    uint8_t subreg_offset;
 123    uint16_t nr;
 124
 125    /** The number of coissuable instructions using this immediate. */
 126    uint16_t uses_by_coissue;
 127
 128    /**
 129     * Whether this constant is used by an instruction that can't handle an
 130     * immediate source (and already has to be promoted to a GRF).
 131     */
 132    bool must_promote;
 133
 134    uint16_t first_use_ip;
 135    uint16_t last_use_ip;
 136 };
 137
 138 /** The working set of information about immediates. */
 139 struct table {
 140    struct imm *imm;
 141    int size;
 142    int len;
 143 };
 144
 145 static struct imm *
 146 find_imm(struct table *table, float val)
 147 {
 148    assert(signbit(val) == 0);
 149
 150    for (int i = 0; i < table->len; i++) {
 151       if (table->imm[i].val == val) {
 152          return &table->imm[i];
 153       }
 154    }
 155    return NULL;
 156 }
 157
 158 static struct imm *
 159 new_imm(struct table *table, void *mem_ctx)
 160 {
 161    if (table->len == table->size) {
 162       table->size *= 2;
 163       table->imm = reralloc(mem_ctx, table->imm, struct imm, table->size);
 164    }
 165    return &table->imm[table->len++];
 166 }
 167
 168 /**
 169  * Comparator used for sorting an array of imm structures.
 170  *
 171  * We sort by basic block number, then last use IP, then first use IP (least
 172  * to greatest). This sorting causes immediates live in the same area to be
 173  * allocated to the same register in the hopes that all values will be dead
 174  * about the same time and the register can be reused.
 175  */
 176 static int
 177 compare(const void *_a, const void *_b)
 178 {
 179    const struct imm *a = (const struct imm *)_a,
 180                     *b = (const struct imm *)_b;
 181
 182    int block_diff = a->block->num - b->block->num;
 183    if (block_diff)
 184       return block_diff;
 185
 186    int end_diff = a->last_use_ip - b->last_use_ip;
 187    if (end_diff)
 188       return end_diff;
 189
 190    return a->first_use_ip - b->first_use_ip;
 191 }
 192
 193 bool
 194 fs_visitor::opt_combine_constants()
 195 {
 196    void *const_ctx = ralloc_context(NULL);
 197
 198    struct table table;
 199    table.size = 8;
 200    table.len = 0;
 201    table.imm = ralloc_array(const_ctx, struct imm, table.size);
 202
 203    cfg->calculate_idom();
 204    unsigned ip = -1;
 205
 206    /* Make a pass through all instructions and count the number of times each
 207     * constant is used by coissueable instructions or instructions that cannot
 208     * take immediate arguments.
 209     */
 210    foreach_block_and_inst(block, fs_inst, inst, cfg) {
 211       ip++;
 212
 213       if (!could_coissue(devinfo, inst) && !must_promote_imm(devinfo, inst))
 214          continue;
 215
 216       for (int i = 0; i < inst->sources; i++) {
 217          if (inst->src[i].file != IMM ||
 218              inst->src[i].type != BRW_REGISTER_TYPE_F)
 219             continue;
 220
 221          float val = fabsf(inst->src[i].f);
 222          struct imm *imm = find_imm(&table, val);
 223
 224          if (imm) {
 225             bblock_t *intersection = cfg_t::intersect(block, imm->block);
 226             if (intersection != imm->block)
 227                imm->inst = NULL;
 228             imm->block = intersection;
 229             imm->uses->push_tail(link(const_ctx, &inst->src[i]));
 230             imm->uses_by_coissue += could_coissue(devinfo, inst);
 231             imm->must_promote = imm->must_promote || must_promote_imm(devinfo, inst);
 232             imm->last_use_ip = ip;
 233          } else {
 234             imm = new_imm(&table, const_ctx);
 235             imm->block = block;
 236             imm->inst = inst;
 237             imm->uses = new(const_ctx) exec_list();
 238             imm->uses->push_tail(link(const_ctx, &inst->src[i]));
 239             imm->val = val;
 240             imm->uses_by_coissue = could_coissue(devinfo, inst);
 241             imm->must_promote = must_promote_imm(devinfo, inst);
 242             imm->first_use_ip = ip;
 243             imm->last_use_ip = ip;
 244          }
 245       }
 246    }
 247
 248    /* Remove constants from the table that don't have enough uses to make them
 249     * profitable to store in a register.
 250     */
 251    for (int i = 0; i < table.len;) {
 252       struct imm *imm = &table.imm[i];
 253
 254       if (!imm->must_promote && imm->uses_by_coissue < 4) {
 255          table.imm[i] = table.imm[table.len - 1];
 256          table.len--;
 257          continue;
 258       }
 259       i++;
 260    }
 261    if (table.len == 0) {
 262       ralloc_free(const_ctx);
 263       return false;
 264    }
 265    if (cfg->num_blocks != 1)
 266       qsort(table.imm, table.len, sizeof(struct imm), compare);
 267
 268
 269    /* Insert MOVs to load the constant values into GRFs. */
 270    fs_reg reg(VGRF, alloc.allocate(dispatch_width / 8));
 271    reg.stride = 0;
 272    for (int i = 0; i < table.len; i++) {
 273       struct imm *imm = &table.imm[i];
 274       /* Insert it either before the instruction that generated the immediate
 275        * or after the last non-control flow instruction of the common ancestor.
 276        */
 277       exec_node *n = (imm->inst ? imm->inst :
 278                       imm->block->last_non_control_flow_inst()->next);
 279       const fs_builder ibld = bld.at(imm->block, n).exec_all().group(1, 0);
 280
 281       ibld.MOV(reg, brw_imm_f(imm->val));
 282       imm->nr = reg.nr;
 283       imm->subreg_offset = reg.subreg_offset;
 284
 285       reg.subreg_offset += sizeof(float);
 286       if ((unsigned)reg.subreg_offset == dispatch_width * sizeof(float)) {
 287          reg.nr = alloc.allocate(dispatch_width / 8);
 288          reg.subreg_offset = 0;
 289       }
 290    }
 291    promoted_constants = table.len;
 292
 293    /* Rewrite the immediate sources to refer to the new GRFs. */
 294    for (int i = 0; i < table.len; i++) {
 295       foreach_list_typed(reg_link, link, link, table.imm[i].uses) {
 296          fs_reg *reg = link->reg;
 297          reg->file = VGRF;
 298          reg->nr = table.imm[i].nr;
 299          reg->subreg_offset = table.imm[i].subreg_offset;
 300          reg->stride = 0;
 301          reg->negate = signbit(reg->f) != signbit(table.imm[i].val);
 302          assert(fabsf(reg->f) == table.imm[i].val);
 303       }
 304    }
 305
 306    ralloc_free(const_ctx);
 307    invalidate_live_intervals();
 308
 309    return true;
 310 }