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24 /** @file brw_fs_copy_propagation.cpp
26 * Support for global copy propagation in two passes: A local pass that does
27 * intra-block copy (and constant) propagation, and a global pass that uses
28 * dataflow analysis on the copies available at the end of each block to re-do
29 * local copy propagation with more copies available.
31 * See Muchnick's Advanced Compiler Design and Implementation, section
35 #define ACP_HASH_SIZE 16
37 #include "util/bitset.h"
42 namespace { /* avoid conflict with opt_copy_propagation_elements */
43 struct acp_entry
: public exec_node
{
54 * Which entries in the fs_copy_prop_dataflow acp table are live at the
55 * start of this block. This is the useful output of the analysis, since
56 * it lets us plug those into the local copy propagation on the second
62 * Which entries in the fs_copy_prop_dataflow acp table are live at the end
63 * of this block. This is done in initial setup from the per-block acps
64 * returned by the first local copy prop pass.
69 * Which entries in the fs_copy_prop_dataflow acp table are generated by
70 * instructions in this block which reach the end of the block without
76 * Which entries in the fs_copy_prop_dataflow acp table are killed over the
77 * course of this block.
82 class fs_copy_prop_dataflow
85 fs_copy_prop_dataflow(void *mem_ctx
, cfg_t
*cfg
,
86 exec_list
*out_acp
[ACP_HASH_SIZE
]);
88 void setup_initial_values();
91 void dump_block_data() const UNUSED
;
100 struct block_data
*bd
;
102 } /* anonymous namespace */
104 fs_copy_prop_dataflow::fs_copy_prop_dataflow(void *mem_ctx
, cfg_t
*cfg
,
105 exec_list
*out_acp
[ACP_HASH_SIZE
])
106 : mem_ctx(mem_ctx
), cfg(cfg
)
108 bd
= rzalloc_array(mem_ctx
, struct block_data
, cfg
->num_blocks
);
111 foreach_block (block
, cfg
) {
112 for (int i
= 0; i
< ACP_HASH_SIZE
; i
++) {
113 num_acp
+= out_acp
[block
->num
][i
].length();
117 acp
= rzalloc_array(mem_ctx
, struct acp_entry
*, num_acp
);
119 bitset_words
= BITSET_WORDS(num_acp
);
122 foreach_block (block
, cfg
) {
123 bd
[block
->num
].livein
= rzalloc_array(bd
, BITSET_WORD
, bitset_words
);
124 bd
[block
->num
].liveout
= rzalloc_array(bd
, BITSET_WORD
, bitset_words
);
125 bd
[block
->num
].copy
= rzalloc_array(bd
, BITSET_WORD
, bitset_words
);
126 bd
[block
->num
].kill
= rzalloc_array(bd
, BITSET_WORD
, bitset_words
);
128 for (int i
= 0; i
< ACP_HASH_SIZE
; i
++) {
129 foreach_in_list(acp_entry
, entry
, &out_acp
[block
->num
][i
]) {
130 acp
[next_acp
] = entry
;
132 /* opt_copy_propagate_local populates out_acp with copies created
133 * in a block which are still live at the end of the block. This
134 * is exactly what we want in the COPY set.
136 BITSET_SET(bd
[block
->num
].copy
, next_acp
);
143 assert(next_acp
== num_acp
);
145 setup_initial_values();
150 * Set up initial values for each of the data flow sets, prior to running
151 * the fixed-point algorithm.
154 fs_copy_prop_dataflow::setup_initial_values()
156 /* Initialize the COPY and KILL sets. */
157 foreach_block (block
, cfg
) {
158 foreach_inst_in_block(fs_inst
, inst
, block
) {
159 if (inst
->dst
.file
!= VGRF
)
162 /* Mark ACP entries which are killed by this instruction. */
163 for (int i
= 0; i
< num_acp
; i
++) {
164 if (inst
->overwrites_reg(acp
[i
]->dst
) ||
165 inst
->overwrites_reg(acp
[i
]->src
)) {
166 BITSET_SET(bd
[block
->num
].kill
, i
);
172 /* Populate the initial values for the livein and liveout sets. For the
173 * block at the start of the program, livein = 0 and liveout = copy.
174 * For the others, set liveout to 0 (the empty set) and livein to ~0
175 * (the universal set).
177 foreach_block (block
, cfg
) {
178 if (block
->parents
.is_empty()) {
179 for (int i
= 0; i
< bitset_words
; i
++) {
180 bd
[block
->num
].livein
[i
] = 0u;
181 bd
[block
->num
].liveout
[i
] = bd
[block
->num
].copy
[i
];
184 for (int i
= 0; i
< bitset_words
; i
++) {
185 bd
[block
->num
].liveout
[i
] = 0u;
186 bd
[block
->num
].livein
[i
] = ~0u;
193 * Walk the set of instructions in the block, marking which entries in the acp
194 * are killed by the block.
197 fs_copy_prop_dataflow::run()
204 /* Update liveout for all blocks. */
205 foreach_block (block
, cfg
) {
206 if (block
->parents
.is_empty())
209 for (int i
= 0; i
< bitset_words
; i
++) {
210 const BITSET_WORD old_liveout
= bd
[block
->num
].liveout
[i
];
212 bd
[block
->num
].liveout
[i
] =
213 bd
[block
->num
].copy
[i
] | (bd
[block
->num
].livein
[i
] &
214 ~bd
[block
->num
].kill
[i
]);
216 if (old_liveout
!= bd
[block
->num
].liveout
[i
])
221 /* Update livein for all blocks. If a copy is live out of all parent
222 * blocks, it's live coming in to this block.
224 foreach_block (block
, cfg
) {
225 if (block
->parents
.is_empty())
228 for (int i
= 0; i
< bitset_words
; i
++) {
229 const BITSET_WORD old_livein
= bd
[block
->num
].livein
[i
];
231 bd
[block
->num
].livein
[i
] = ~0u;
232 foreach_list_typed(bblock_link
, parent_link
, link
, &block
->parents
) {
233 bblock_t
*parent
= parent_link
->block
;
234 bd
[block
->num
].livein
[i
] &= bd
[parent
->num
].liveout
[i
];
237 if (old_livein
!= bd
[block
->num
].livein
[i
])
245 fs_copy_prop_dataflow::dump_block_data() const
247 foreach_block (block
, cfg
) {
248 fprintf(stderr
, "Block %d [%d, %d] (parents ", block
->num
,
249 block
->start_ip
, block
->end_ip
);
250 foreach_list_typed(bblock_link
, link
, link
, &block
->parents
) {
251 bblock_t
*parent
= link
->block
;
252 fprintf(stderr
, "%d ", parent
->num
);
254 fprintf(stderr
, "):\n");
255 fprintf(stderr
, " livein = 0x");
256 for (int i
= 0; i
< bitset_words
; i
++)
257 fprintf(stderr
, "%08x", bd
[block
->num
].livein
[i
]);
258 fprintf(stderr
, ", liveout = 0x");
259 for (int i
= 0; i
< bitset_words
; i
++)
260 fprintf(stderr
, "%08x", bd
[block
->num
].liveout
[i
]);
261 fprintf(stderr
, ",\n copy = 0x");
262 for (int i
= 0; i
< bitset_words
; i
++)
263 fprintf(stderr
, "%08x", bd
[block
->num
].copy
[i
]);
264 fprintf(stderr
, ", kill = 0x");
265 for (int i
= 0; i
< bitset_words
; i
++)
266 fprintf(stderr
, "%08x", bd
[block
->num
].kill
[i
]);
267 fprintf(stderr
, "\n");
272 is_logic_op(enum opcode opcode
)
274 return (opcode
== BRW_OPCODE_AND
||
275 opcode
== BRW_OPCODE_OR
||
276 opcode
== BRW_OPCODE_XOR
||
277 opcode
== BRW_OPCODE_NOT
);
281 can_take_stride(fs_inst
*inst
, unsigned arg
, unsigned stride
,
282 const brw_device_info
*devinfo
)
287 /* 3-source instructions can only be Align16, which restricts what strides
288 * they can take. They can only take a stride of 1 (the usual case), or 0
289 * with a special "repctrl" bit. But the repctrl bit doesn't work for
290 * 64-bit datatypes, so if the source type is 64-bit then only a stride of
291 * 1 is allowed. From the Broadwell PRM, Volume 7 "3D Media GPGPU", page
294 * This is applicable to 32b datatypes and 16b datatype. 64b datatypes
295 * cannot use the replicate control.
297 if (inst
->is_3src(devinfo
)) {
298 if (type_sz(inst
->src
[arg
].type
) > 4)
301 return stride
== 1 || stride
== 0;
304 /* From the Broadwell PRM, Volume 2a "Command Reference - Instructions",
305 * page 391 ("Extended Math Function"):
307 * The following restrictions apply for align1 mode: Scalar source is
308 * supported. Source and destination horizontal stride must be the
311 * From the Haswell PRM Volume 2b "Command Reference - Instructions", page
312 * 134 ("Extended Math Function"):
314 * Scalar source is supported. Source and destination horizontal stride
317 * and similar language exists for IVB and SNB. Pre-SNB, math instructions
318 * are sends, so the sources are moved to MRF's and there are no
321 if (inst
->is_math()) {
322 if (devinfo
->gen
== 6 || devinfo
->gen
== 7) {
323 assert(inst
->dst
.stride
== 1);
324 return stride
== 1 || stride
== 0;
325 } else if (devinfo
->gen
>= 8) {
326 return stride
== inst
->dst
.stride
|| stride
== 0;
334 * Check that the register region read by src [src.reg_offset,
335 * src.reg_offset + regs_read] is contained inside the register
336 * region written by dst [dst.reg_offset, dst.reg_offset + regs_written]
337 * Both src and dst must have the same register number and file.
340 region_contained_in(const fs_reg
&src
, unsigned regs_read
,
341 const fs_reg
&dst
, unsigned regs_written
)
343 return src
.file
== dst
.file
&& src
.nr
== dst
.nr
&&
344 (src
.reg_offset
* REG_SIZE
+ src
.subreg_offset
>=
345 dst
.reg_offset
* REG_SIZE
+ dst
.subreg_offset
) &&
346 src
.reg_offset
+ regs_read
<= dst
.reg_offset
+ regs_written
;
350 fs_visitor::try_copy_propagate(fs_inst
*inst
, int arg
, acp_entry
*entry
)
352 if (inst
->src
[arg
].file
!= VGRF
)
355 if (entry
->src
.file
== IMM
)
357 assert(entry
->src
.file
== VGRF
|| entry
->src
.file
== UNIFORM
||
358 entry
->src
.file
== ATTR
);
360 if (entry
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
&&
361 inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
)
364 assert(entry
->dst
.file
== VGRF
);
365 if (inst
->src
[arg
].nr
!= entry
->dst
.nr
)
368 /* Bail if inst is reading a range that isn't contained in the range
369 * that entry is writing.
371 if (!region_contained_in(inst
->src
[arg
], inst
->regs_read(arg
),
372 entry
->dst
, entry
->regs_written
))
375 /* we can't generally copy-propagate UD negations because we
376 * can end up accessing the resulting values as signed integers
377 * instead. See also resolve_ud_negate() and comment in
378 * fs_generator::generate_code.
380 if (entry
->src
.type
== BRW_REGISTER_TYPE_UD
&&
384 bool has_source_modifiers
= entry
->src
.abs
|| entry
->src
.negate
;
386 if ((has_source_modifiers
|| entry
->src
.file
== UNIFORM
||
387 !entry
->src
.is_contiguous()) &&
388 !inst
->can_do_source_mods(devinfo
))
391 if (has_source_modifiers
&&
392 inst
->opcode
== SHADER_OPCODE_GEN4_SCRATCH_WRITE
)
395 /* Bail if the result of composing both strides would exceed the
398 if (!can_take_stride(inst
, arg
, entry
->src
.stride
* inst
->src
[arg
].stride
,
402 /* Bail if the instruction type is larger than the execution type of the
403 * copy, what implies that each channel is reading multiple channels of the
404 * destination of the copy, and simply replacing the sources would give a
405 * program with different semantics.
407 if (type_sz(entry
->dst
.type
) < type_sz(inst
->src
[arg
].type
))
410 /* Bail if the result of composing both strides cannot be expressed
411 * as another stride. This avoids, for example, trying to transform
414 * MOV (8) rX<1>UD rY<0;1,0>UD
415 * FOO (8) ... rX<8;8,1>UW
419 * FOO (8) ... rY<0;1,0>UW
421 * Which would have different semantics.
423 if (entry
->src
.stride
!= 1 &&
424 (inst
->src
[arg
].stride
*
425 type_sz(inst
->src
[arg
].type
)) % type_sz(entry
->src
.type
) != 0)
428 /* Since semantics of source modifiers are type-dependent we need to
429 * ensure that the meaning of the instruction remains the same if we
430 * change the type. If the sizes of the types are different the new
431 * instruction will read a different amount of data than the original
432 * and the semantics will always be different.
434 if (has_source_modifiers
&&
435 entry
->dst
.type
!= inst
->src
[arg
].type
&&
436 (!inst
->can_change_types() ||
437 type_sz(entry
->dst
.type
) != type_sz(inst
->src
[arg
].type
)))
440 if (devinfo
->gen
>= 8 && (entry
->src
.negate
|| entry
->src
.abs
) &&
441 is_logic_op(inst
->opcode
)) {
445 if (entry
->saturate
) {
446 switch(inst
->opcode
) {
448 if (inst
->src
[1].file
!= IMM
||
449 inst
->src
[1].f
< 0.0 ||
450 inst
->src
[1].f
> 1.0) {
459 inst
->src
[arg
].file
= entry
->src
.file
;
460 inst
->src
[arg
].nr
= entry
->src
.nr
;
461 inst
->src
[arg
].stride
*= entry
->src
.stride
;
462 inst
->saturate
= inst
->saturate
|| entry
->saturate
;
464 /* Compute the offset of inst->src[arg] relative to entry->dst */
465 const unsigned rel_offset
= (inst
->src
[arg
].reg_offset
466 - entry
->dst
.reg_offset
) * REG_SIZE
+
467 inst
->src
[arg
].subreg_offset
;
469 /* Compute the first component of the copy that the instruction is
470 * reading, and the base byte offset within that component.
472 assert(entry
->dst
.subreg_offset
== 0 && entry
->dst
.stride
== 1);
473 const unsigned component
= rel_offset
/ type_sz(entry
->dst
.type
);
474 const unsigned suboffset
= rel_offset
% type_sz(entry
->dst
.type
);
476 /* Account for the inconsistent units reg_offset is expressed in.
477 * FINISHME -- Make the units of reg_offset consistent (e.g. bytes?) for
478 * all register files.
480 const unsigned reg_size
= (entry
->src
.file
== UNIFORM
? 4 : REG_SIZE
);
482 /* Calculate the byte offset at the origin of the copy of the given
483 * component and suboffset.
485 const unsigned offset
= suboffset
+
486 component
* entry
->src
.stride
* type_sz(entry
->src
.type
) +
487 entry
->src
.reg_offset
* reg_size
+ entry
->src
.subreg_offset
;
488 inst
->src
[arg
].reg_offset
= offset
/ reg_size
;
489 inst
->src
[arg
].subreg_offset
= offset
% reg_size
;
491 if (has_source_modifiers
) {
492 if (entry
->dst
.type
!= inst
->src
[arg
].type
) {
493 /* We are propagating source modifiers from a MOV with a different
494 * type. If we got here, then we can just change the source and
495 * destination types of the instruction and keep going.
497 assert(inst
->can_change_types());
498 for (int i
= 0; i
< inst
->sources
; i
++) {
499 inst
->src
[i
].type
= entry
->dst
.type
;
501 inst
->dst
.type
= entry
->dst
.type
;
504 if (!inst
->src
[arg
].abs
) {
505 inst
->src
[arg
].abs
= entry
->src
.abs
;
506 inst
->src
[arg
].negate
^= entry
->src
.negate
;
515 fs_visitor::try_constant_propagate(fs_inst
*inst
, acp_entry
*entry
)
517 bool progress
= false;
519 if (entry
->src
.file
!= IMM
)
521 if (type_sz(entry
->src
.type
) > 4)
526 for (int i
= inst
->sources
- 1; i
>= 0; i
--) {
527 if (inst
->src
[i
].file
!= VGRF
)
530 assert(entry
->dst
.file
== VGRF
);
531 if (inst
->src
[i
].nr
!= entry
->dst
.nr
)
534 /* Bail if inst is reading a range that isn't contained in the range
535 * that entry is writing.
537 if (!region_contained_in(inst
->src
[i
], inst
->regs_read(i
),
538 entry
->dst
, entry
->regs_written
))
541 fs_reg val
= entry
->src
;
542 val
.type
= inst
->src
[i
].type
;
544 if (inst
->src
[i
].abs
) {
545 if ((devinfo
->gen
>= 8 && is_logic_op(inst
->opcode
)) ||
546 !brw_abs_immediate(val
.type
, &val
.as_brw_reg())) {
551 if (inst
->src
[i
].negate
) {
552 if ((devinfo
->gen
>= 8 && is_logic_op(inst
->opcode
)) ||
553 !brw_negate_immediate(val
.type
, &val
.as_brw_reg())) {
558 switch (inst
->opcode
) {
560 case SHADER_OPCODE_LOAD_PAYLOAD
:
566 case SHADER_OPCODE_INT_QUOTIENT
:
567 case SHADER_OPCODE_INT_REMAINDER
:
568 /* FINISHME: Promote non-float constants and remove this. */
569 if (devinfo
->gen
< 8)
572 case SHADER_OPCODE_POW
:
573 /* Allow constant propagation into src1 (except on Gen 6), and let
574 * constant combining promote the constant on Gen < 8.
576 * While Gen 6 MATH can take a scalar source, its source and
577 * destination offsets must be equal and we cannot ensure that.
579 if (devinfo
->gen
== 6)
582 case BRW_OPCODE_BFI1
:
586 case BRW_OPCODE_SUBB
:
593 case BRW_OPCODE_MACH
:
595 case SHADER_OPCODE_MULH
:
600 case BRW_OPCODE_ADDC
:
604 } else if (i
== 0 && inst
->src
[1].file
!= IMM
) {
605 /* Fit this constant in by commuting the operands.
606 * Exception: we can't do this for 32-bit integer MUL/MACH
607 * because it's asymmetric.
609 * The BSpec says for Broadwell that
611 * "When multiplying DW x DW, the dst cannot be accumulator."
613 * Integer MUL with a non-accumulator destination will be lowered
614 * by lower_integer_multiplication(), so don't restrict it.
616 if (((inst
->opcode
== BRW_OPCODE_MUL
&&
617 inst
->dst
.is_accumulator()) ||
618 inst
->opcode
== BRW_OPCODE_MACH
) &&
619 (inst
->src
[1].type
== BRW_REGISTER_TYPE_D
||
620 inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
))
622 inst
->src
[0] = inst
->src
[1];
633 } else if (i
== 0 && inst
->src
[1].file
!= IMM
) {
634 enum brw_conditional_mod new_cmod
;
636 new_cmod
= brw_swap_cmod(inst
->conditional_mod
);
637 if (new_cmod
!= BRW_CONDITIONAL_NONE
) {
638 /* Fit this constant in by swapping the operands and
641 inst
->src
[0] = inst
->src
[1];
643 inst
->conditional_mod
= new_cmod
;
653 } else if (i
== 0 && inst
->src
[1].file
!= IMM
) {
654 inst
->src
[0] = inst
->src
[1];
657 /* If this was predicated, flipping operands means
658 * we also need to flip the predicate.
660 if (inst
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
661 inst
->predicate_inverse
=
662 !inst
->predicate_inverse
;
668 case SHADER_OPCODE_UNTYPED_ATOMIC
:
669 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
670 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
671 case SHADER_OPCODE_TYPED_ATOMIC
:
672 case SHADER_OPCODE_TYPED_SURFACE_READ
:
673 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
674 /* We only propagate into the surface argument of the
675 * instruction. Everything else goes through LOAD_PAYLOAD.
683 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
684 case SHADER_OPCODE_BROADCAST
:
704 can_propagate_from(fs_inst
*inst
)
706 return (inst
->opcode
== BRW_OPCODE_MOV
&&
707 inst
->dst
.file
== VGRF
&&
708 ((inst
->src
[0].file
== VGRF
&&
709 (inst
->src
[0].nr
!= inst
->dst
.nr
||
710 inst
->src
[0].reg_offset
!= inst
->dst
.reg_offset
)) ||
711 inst
->src
[0].file
== ATTR
||
712 inst
->src
[0].file
== UNIFORM
||
713 inst
->src
[0].file
== IMM
) &&
714 inst
->src
[0].type
== inst
->dst
.type
&&
715 !inst
->is_partial_write());
719 regions_overlap(const fs_reg
&r
, unsigned n
, const fs_reg
&s
, unsigned m
)
721 return r
.file
== s
.file
&& r
.nr
== s
.nr
&&
722 !(r
.reg_offset
+ n
< s
.reg_offset
||
723 s
.reg_offset
+ m
< r
.reg_offset
);
726 /* Walks a basic block and does copy propagation on it using the acp
730 fs_visitor::opt_copy_propagate_local(void *copy_prop_ctx
, bblock_t
*block
,
733 bool progress
= false;
735 foreach_inst_in_block(fs_inst
, inst
, block
) {
736 /* Try propagating into this instruction. */
737 for (int i
= 0; i
< inst
->sources
; i
++) {
738 if (inst
->src
[i
].file
!= VGRF
)
741 foreach_in_list(acp_entry
, entry
, &acp
[inst
->src
[i
].nr
% ACP_HASH_SIZE
]) {
742 if (try_constant_propagate(inst
, entry
))
744 else if (try_copy_propagate(inst
, i
, entry
))
749 /* kill the destination from the ACP */
750 if (inst
->dst
.file
== VGRF
) {
751 foreach_in_list_safe(acp_entry
, entry
, &acp
[inst
->dst
.nr
% ACP_HASH_SIZE
]) {
752 if (regions_overlap(entry
->dst
, entry
->regs_written
,
753 inst
->dst
, inst
->regs_written
)) {
759 /* Oops, we only have the chaining hash based on the destination, not
760 * the source, so walk across the entire table.
762 for (int i
= 0; i
< ACP_HASH_SIZE
; i
++) {
763 foreach_in_list_safe(acp_entry
, entry
, &acp
[i
]) {
764 /* Make sure we kill the entry if this instruction overwrites
765 * _any_ of the registers that it reads
767 if (regions_overlap(entry
->src
, entry
->regs_read
,
768 inst
->dst
, inst
->regs_written
)) {
776 /* If this instruction's source could potentially be folded into the
777 * operand of another instruction, add it to the ACP.
779 if (can_propagate_from(inst
)) {
780 acp_entry
*entry
= ralloc(copy_prop_ctx
, acp_entry
);
781 entry
->dst
= inst
->dst
;
782 entry
->src
= inst
->src
[0];
783 entry
->regs_written
= inst
->regs_written
;
784 entry
->regs_read
= inst
->regs_read(0);
785 entry
->opcode
= inst
->opcode
;
786 entry
->saturate
= inst
->saturate
;
787 acp
[entry
->dst
.nr
% ACP_HASH_SIZE
].push_tail(entry
);
788 } else if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
&&
789 inst
->dst
.file
== VGRF
) {
791 for (int i
= 0; i
< inst
->sources
; i
++) {
792 int effective_width
= i
< inst
->header_size
? 8 : inst
->exec_size
;
793 assert(effective_width
* type_sz(inst
->src
[i
].type
) % REG_SIZE
== 0);
794 int regs_written
= effective_width
*
795 type_sz(inst
->src
[i
].type
) / REG_SIZE
;
796 if (inst
->src
[i
].file
== VGRF
) {
797 acp_entry
*entry
= ralloc(copy_prop_ctx
, acp_entry
);
798 entry
->dst
= inst
->dst
;
799 entry
->dst
.reg_offset
+= offset
;
800 entry
->src
= inst
->src
[i
];
801 entry
->regs_written
= regs_written
;
802 entry
->regs_read
= inst
->regs_read(i
);
803 entry
->opcode
= inst
->opcode
;
804 if (!entry
->dst
.equals(inst
->src
[i
])) {
805 acp
[entry
->dst
.nr
% ACP_HASH_SIZE
].push_tail(entry
);
810 offset
+= regs_written
;
819 fs_visitor::opt_copy_propagate()
821 bool progress
= false;
822 void *copy_prop_ctx
= ralloc_context(NULL
);
823 exec_list
*out_acp
[cfg
->num_blocks
];
825 for (int i
= 0; i
< cfg
->num_blocks
; i
++)
826 out_acp
[i
] = new exec_list
[ACP_HASH_SIZE
];
828 /* First, walk through each block doing local copy propagation and getting
829 * the set of copies available at the end of the block.
831 foreach_block (block
, cfg
) {
832 progress
= opt_copy_propagate_local(copy_prop_ctx
, block
,
833 out_acp
[block
->num
]) || progress
;
836 /* Do dataflow analysis for those available copies. */
837 fs_copy_prop_dataflow
dataflow(copy_prop_ctx
, cfg
, out_acp
);
839 /* Next, re-run local copy propagation, this time with the set of copies
840 * provided by the dataflow analysis available at the start of a block.
842 foreach_block (block
, cfg
) {
843 exec_list in_acp
[ACP_HASH_SIZE
];
845 for (int i
= 0; i
< dataflow
.num_acp
; i
++) {
846 if (BITSET_TEST(dataflow
.bd
[block
->num
].livein
, i
)) {
847 struct acp_entry
*entry
= dataflow
.acp
[i
];
848 in_acp
[entry
->dst
.nr
% ACP_HASH_SIZE
].push_tail(entry
);
852 progress
= opt_copy_propagate_local(copy_prop_ctx
, block
, in_acp
) || progress
;
855 for (int i
= 0; i
< cfg
->num_blocks
; i
++)
856 delete [] out_acp
[i
];
857 ralloc_free(copy_prop_ctx
);
860 invalidate_live_intervals();