2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 /** @file brw_fs_cse.cpp
29 * Support for local common subexpression elimination.
31 * See Muchnick's Advanced Compiler Design and Implementation, section
36 struct aeb_entry
: public exec_node
{
37 /** The instruction that generates the expression value. */
40 /** The temporary where the value is stored. */
46 is_copy_payload(const fs_inst
*inst
)
48 const int reg
= inst
->src
[0].reg
;
49 if (inst
->src
[0].reg_offset
!= 0)
52 for (int i
= 1; i
< inst
->sources
; i
++) {
53 if (inst
->src
[i
].reg
!= reg
||
54 inst
->src
[i
].reg_offset
!= i
) {
62 is_expression(const fs_inst
*const inst
)
64 switch (inst
->opcode
) {
86 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
87 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
88 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
89 case FS_OPCODE_CINTERP
:
90 case FS_OPCODE_LINTERP
:
92 case SHADER_OPCODE_RCP
:
93 case SHADER_OPCODE_RSQ
:
94 case SHADER_OPCODE_SQRT
:
95 case SHADER_OPCODE_EXP2
:
96 case SHADER_OPCODE_LOG2
:
97 case SHADER_OPCODE_POW
:
98 case SHADER_OPCODE_INT_QUOTIENT
:
99 case SHADER_OPCODE_INT_REMAINDER
:
100 case SHADER_OPCODE_SIN
:
101 case SHADER_OPCODE_COS
:
102 return inst
->mlen
< 2;
103 case SHADER_OPCODE_LOAD_PAYLOAD
:
104 return !is_copy_payload(inst
);
106 return inst
->is_send_from_grf() && !inst
->has_side_effects();
111 is_expression_commutative(enum opcode op
)
126 operands_match(fs_inst
*a
, fs_inst
*b
)
131 if (a
->opcode
== BRW_OPCODE_MAD
) {
132 return xs
[0].equals(ys
[0]) &&
133 ((xs
[1].equals(ys
[1]) && xs
[2].equals(ys
[2])) ||
134 (xs
[2].equals(ys
[1]) && xs
[1].equals(ys
[2])));
135 } else if (!is_expression_commutative(a
->opcode
)) {
137 for (int i
= 0; i
< a
->sources
; i
++) {
138 if (!xs
[i
].equals(ys
[i
])) {
145 return (xs
[0].equals(ys
[0]) && xs
[1].equals(ys
[1])) ||
146 (xs
[1].equals(ys
[0]) && xs
[0].equals(ys
[1]));
151 instructions_match(fs_inst
*a
, fs_inst
*b
)
153 return a
->opcode
== b
->opcode
&&
154 a
->saturate
== b
->saturate
&&
155 a
->predicate
== b
->predicate
&&
156 a
->predicate_inverse
== b
->predicate_inverse
&&
157 a
->conditional_mod
== b
->conditional_mod
&&
158 a
->dst
.type
== b
->dst
.type
&&
159 a
->sources
== b
->sources
&&
160 (a
->is_tex() ? (a
->texture_offset
== b
->texture_offset
&&
161 a
->mlen
== b
->mlen
&&
162 a
->regs_written
== b
->regs_written
&&
163 a
->base_mrf
== b
->base_mrf
&&
165 a
->header_present
== b
->header_present
&&
166 a
->shadow_compare
== b
->shadow_compare
)
168 operands_match(a
, b
);
172 fs_visitor::opt_cse_local(bblock_t
*block
)
174 bool progress
= false;
177 void *cse_ctx
= ralloc_context(NULL
);
179 int ip
= block
->start_ip
;
180 foreach_inst_in_block(fs_inst
, inst
, block
) {
181 /* Skip some cases. */
182 if (is_expression(inst
) && !inst
->is_partial_write() &&
183 (inst
->dst
.file
!= HW_REG
|| inst
->dst
.is_null()))
187 foreach_in_list_use_after(aeb_entry
, entry
, &aeb
) {
188 /* Match current instruction's expression against those in AEB. */
189 if (instructions_match(inst
, entry
->generator
)) {
197 /* Our first sighting of this expression. Create an entry. */
198 aeb_entry
*entry
= ralloc(cse_ctx
, aeb_entry
);
199 entry
->tmp
= reg_undef
;
200 entry
->generator
= inst
;
201 aeb
.push_tail(entry
);
203 /* This is at least our second sighting of this expression.
204 * If we don't have a temporary already, make one.
206 bool no_existing_temp
= entry
->tmp
.file
== BAD_FILE
;
207 if (no_existing_temp
&& !entry
->generator
->dst
.is_null()) {
208 int written
= entry
->generator
->regs_written
;
209 int dst_width
= entry
->generator
->dst
.width
/ 8;
210 assert(written
% dst_width
== 0);
212 fs_reg orig_dst
= entry
->generator
->dst
;
213 fs_reg tmp
= fs_reg(GRF
, virtual_grf_alloc(written
),
214 orig_dst
.type
, orig_dst
.width
);
216 entry
->generator
->dst
= tmp
;
219 if (written
> dst_width
) {
220 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, written
/ dst_width
);
221 for (int i
= 0; i
< written
/ dst_width
; i
++)
222 sources
[i
] = offset(tmp
, i
);
223 copy
= LOAD_PAYLOAD(orig_dst
, sources
, written
/ dst_width
);
225 copy
= MOV(orig_dst
, tmp
);
226 copy
->force_writemask_all
=
227 entry
->generator
->force_writemask_all
;
229 entry
->generator
->insert_after(block
, copy
);
233 if (!inst
->dst
.is_null()) {
234 int written
= inst
->regs_written
;
235 int dst_width
= inst
->dst
.width
/ 8;
236 assert(written
== entry
->generator
->regs_written
);
237 assert(dst_width
== entry
->generator
->dst
.width
/ 8);
238 assert(inst
->dst
.type
== entry
->tmp
.type
);
239 fs_reg dst
= inst
->dst
;
240 fs_reg tmp
= entry
->tmp
;
242 if (written
> dst_width
) {
243 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, written
/ dst_width
);
244 for (int i
= 0; i
< written
/ dst_width
; i
++)
245 sources
[i
] = offset(tmp
, i
);
246 copy
= LOAD_PAYLOAD(dst
, sources
, written
/ dst_width
);
248 copy
= MOV(dst
, tmp
);
249 copy
->force_writemask_all
= inst
->force_writemask_all
;
251 inst
->insert_before(block
, copy
);
254 /* Set our iterator so that next time through the loop inst->next
255 * will get the instruction in the basic block after the one we've
258 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
265 foreach_in_list_safe(aeb_entry
, entry
, &aeb
) {
266 /* Kill all AEB entries that write a different value to or read from
267 * the flag register if we just wrote it.
269 if (inst
->writes_flag()) {
270 if (entry
->generator
->reads_flag() ||
271 (entry
->generator
->writes_flag() &&
272 !instructions_match(inst
, entry
->generator
))) {
279 for (int i
= 0; i
< entry
->generator
->sources
; i
++) {
280 fs_reg
*src_reg
= &entry
->generator
->src
[i
];
282 /* Kill all AEB entries that use the destination we just
285 if (inst
->overwrites_reg(entry
->generator
->src
[i
])) {
291 /* Kill any AEB entries using registers that don't get reused any
292 * more -- a sure sign they'll fail operands_match().
294 if (src_reg
->file
== GRF
&& virtual_grf_end
[src_reg
->reg
] < ip
) {
305 ralloc_free(cse_ctx
);
311 fs_visitor::opt_cse()
313 bool progress
= false;
315 calculate_live_intervals();
317 foreach_block (block
, cfg
) {
318 progress
= opt_cse_local(block
) || progress
;
322 invalidate_live_intervals();