i965/nir/vec4: Prepare source and destination registers for ALU operations
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_cse.cpp
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_fs.h"
25 #include "brw_cfg.h"
26
27 /** @file brw_fs_cse.cpp
28 *
29 * Support for local common subexpression elimination.
30 *
31 * See Muchnick's Advanced Compiler Design and Implementation, section
32 * 13.1 (p378).
33 */
34
35 using namespace brw;
36
37 namespace {
38 struct aeb_entry : public exec_node {
39 /** The instruction that generates the expression value. */
40 fs_inst *generator;
41
42 /** The temporary where the value is stored. */
43 fs_reg tmp;
44 };
45 }
46
47 static bool
48 is_expression(const fs_visitor *v, const fs_inst *const inst)
49 {
50 switch (inst->opcode) {
51 case BRW_OPCODE_MOV:
52 case BRW_OPCODE_SEL:
53 case BRW_OPCODE_NOT:
54 case BRW_OPCODE_AND:
55 case BRW_OPCODE_OR:
56 case BRW_OPCODE_XOR:
57 case BRW_OPCODE_SHR:
58 case BRW_OPCODE_SHL:
59 case BRW_OPCODE_ASR:
60 case BRW_OPCODE_CMP:
61 case BRW_OPCODE_CMPN:
62 case BRW_OPCODE_ADD:
63 case BRW_OPCODE_MUL:
64 case BRW_OPCODE_FRC:
65 case BRW_OPCODE_RNDU:
66 case BRW_OPCODE_RNDD:
67 case BRW_OPCODE_RNDE:
68 case BRW_OPCODE_RNDZ:
69 case BRW_OPCODE_LINE:
70 case BRW_OPCODE_PLN:
71 case BRW_OPCODE_MAD:
72 case BRW_OPCODE_LRP:
73 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
74 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
75 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
76 case FS_OPCODE_CINTERP:
77 case FS_OPCODE_LINTERP:
78 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
79 case SHADER_OPCODE_BROADCAST:
80 return true;
81 case SHADER_OPCODE_RCP:
82 case SHADER_OPCODE_RSQ:
83 case SHADER_OPCODE_SQRT:
84 case SHADER_OPCODE_EXP2:
85 case SHADER_OPCODE_LOG2:
86 case SHADER_OPCODE_POW:
87 case SHADER_OPCODE_INT_QUOTIENT:
88 case SHADER_OPCODE_INT_REMAINDER:
89 case SHADER_OPCODE_SIN:
90 case SHADER_OPCODE_COS:
91 return inst->mlen < 2;
92 case SHADER_OPCODE_LOAD_PAYLOAD:
93 return !inst->is_copy_payload(v->alloc);
94 default:
95 return inst->is_send_from_grf() && !inst->has_side_effects();
96 }
97 }
98
99 static bool
100 operands_match(const fs_inst *a, const fs_inst *b, bool *negate)
101 {
102 fs_reg *xs = a->src;
103 fs_reg *ys = b->src;
104
105 if (a->opcode == BRW_OPCODE_MAD) {
106 return xs[0].equals(ys[0]) &&
107 ((xs[1].equals(ys[1]) && xs[2].equals(ys[2])) ||
108 (xs[2].equals(ys[1]) && xs[1].equals(ys[2])));
109 } else if (a->opcode == BRW_OPCODE_MUL && a->dst.type == BRW_REGISTER_TYPE_F) {
110 bool xs0_negate = xs[0].negate;
111 bool xs1_negate = xs[1].file == IMM ? xs[1].fixed_hw_reg.dw1.f < 0.0f
112 : xs[1].negate;
113 bool ys0_negate = ys[0].negate;
114 bool ys1_negate = ys[1].file == IMM ? ys[1].fixed_hw_reg.dw1.f < 0.0f
115 : ys[1].negate;
116 float xs1_imm = xs[1].fixed_hw_reg.dw1.f;
117 float ys1_imm = ys[1].fixed_hw_reg.dw1.f;
118
119 xs[0].negate = false;
120 xs[1].negate = false;
121 ys[0].negate = false;
122 ys[1].negate = false;
123 xs[1].fixed_hw_reg.dw1.f = fabsf(xs[1].fixed_hw_reg.dw1.f);
124 ys[1].fixed_hw_reg.dw1.f = fabsf(ys[1].fixed_hw_reg.dw1.f);
125
126 bool ret = (xs[0].equals(ys[0]) && xs[1].equals(ys[1])) ||
127 (xs[1].equals(ys[0]) && xs[0].equals(ys[1]));
128
129 xs[0].negate = xs0_negate;
130 xs[1].negate = xs[1].file == IMM ? false : xs1_negate;
131 ys[0].negate = ys0_negate;
132 ys[1].negate = ys[1].file == IMM ? false : ys1_negate;
133 xs[1].fixed_hw_reg.dw1.f = xs1_imm;
134 ys[1].fixed_hw_reg.dw1.f = ys1_imm;
135
136 *negate = (xs0_negate != xs1_negate) != (ys0_negate != ys1_negate);
137 return ret;
138 } else if (!a->is_commutative()) {
139 bool match = true;
140 for (int i = 0; i < a->sources; i++) {
141 if (!xs[i].equals(ys[i])) {
142 match = false;
143 break;
144 }
145 }
146 return match;
147 } else {
148 return (xs[0].equals(ys[0]) && xs[1].equals(ys[1])) ||
149 (xs[1].equals(ys[0]) && xs[0].equals(ys[1]));
150 }
151 }
152
153 static bool
154 instructions_match(fs_inst *a, fs_inst *b, bool *negate)
155 {
156 return a->opcode == b->opcode &&
157 a->force_writemask_all == b->force_writemask_all &&
158 a->exec_size == b->exec_size &&
159 a->force_sechalf == b->force_sechalf &&
160 a->saturate == b->saturate &&
161 a->predicate == b->predicate &&
162 a->predicate_inverse == b->predicate_inverse &&
163 a->conditional_mod == b->conditional_mod &&
164 a->flag_subreg == b->flag_subreg &&
165 a->dst.type == b->dst.type &&
166 a->offset == b->offset &&
167 a->mlen == b->mlen &&
168 a->regs_written == b->regs_written &&
169 a->base_mrf == b->base_mrf &&
170 a->eot == b->eot &&
171 a->header_size == b->header_size &&
172 a->shadow_compare == b->shadow_compare &&
173 a->pi_noperspective == b->pi_noperspective &&
174 a->sources == b->sources &&
175 operands_match(a, b, negate);
176 }
177
178 static void
179 create_copy_instr(const fs_builder &bld, fs_inst *inst, fs_reg src, bool negate)
180 {
181 int written = inst->regs_written;
182 int dst_width = inst->exec_size / 8;
183 fs_inst *copy;
184
185 if (written > dst_width) {
186 fs_reg *payload;
187 int sources, header_size;
188 if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
189 sources = inst->sources;
190 header_size = inst->header_size;
191 } else {
192 assert(written % dst_width == 0);
193 sources = written / dst_width;
194 header_size = 0;
195 }
196
197 assert(src.file == GRF);
198 payload = ralloc_array(bld.shader->mem_ctx, fs_reg, sources);
199 for (int i = 0; i < header_size; i++) {
200 payload[i] = src;
201 src.reg_offset++;
202 }
203 for (int i = header_size; i < sources; i++) {
204 payload[i] = src;
205 src = offset(src, bld, 1);
206 }
207 copy = bld.LOAD_PAYLOAD(inst->dst, payload, sources, header_size);
208 } else {
209 copy = bld.MOV(inst->dst, src);
210 copy->src[0].negate = negate;
211 }
212 assert(copy->regs_written == written);
213 }
214
215 bool
216 fs_visitor::opt_cse_local(bblock_t *block)
217 {
218 bool progress = false;
219 exec_list aeb;
220
221 void *cse_ctx = ralloc_context(NULL);
222
223 int ip = block->start_ip;
224 foreach_inst_in_block(fs_inst, inst, block) {
225 /* Skip some cases. */
226 if (is_expression(this, inst) && !inst->is_partial_write() &&
227 (inst->dst.file != HW_REG || inst->dst.is_null()))
228 {
229 bool found = false;
230 bool negate = false;
231
232 foreach_in_list_use_after(aeb_entry, entry, &aeb) {
233 /* Match current instruction's expression against those in AEB. */
234 if (!(entry->generator->dst.is_null() && !inst->dst.is_null()) &&
235 instructions_match(inst, entry->generator, &negate)) {
236 found = true;
237 progress = true;
238 break;
239 }
240 }
241
242 if (!found) {
243 if (inst->opcode != BRW_OPCODE_MOV ||
244 (inst->opcode == BRW_OPCODE_MOV &&
245 inst->src[0].file == IMM &&
246 inst->src[0].type == BRW_REGISTER_TYPE_VF)) {
247 /* Our first sighting of this expression. Create an entry. */
248 aeb_entry *entry = ralloc(cse_ctx, aeb_entry);
249 entry->tmp = reg_undef;
250 entry->generator = inst;
251 aeb.push_tail(entry);
252 }
253 } else {
254 /* This is at least our second sighting of this expression.
255 * If we don't have a temporary already, make one.
256 */
257 bool no_existing_temp = entry->tmp.file == BAD_FILE;
258 if (no_existing_temp && !entry->generator->dst.is_null()) {
259 const fs_builder ibld = fs_builder(this, block, entry->generator)
260 .at(block, entry->generator->next);
261 int written = entry->generator->regs_written;
262
263 entry->tmp = fs_reg(GRF, alloc.allocate(written),
264 entry->generator->dst.type);
265
266 create_copy_instr(ibld, entry->generator, entry->tmp, false);
267
268 entry->generator->dst = entry->tmp;
269 }
270
271 /* dest <- temp */
272 if (!inst->dst.is_null()) {
273 assert(inst->regs_written == entry->generator->regs_written);
274 assert(inst->dst.type == entry->tmp.type);
275 const fs_builder ibld(this, block, inst);
276
277 create_copy_instr(ibld, inst, entry->tmp, negate);
278 }
279
280 /* Set our iterator so that next time through the loop inst->next
281 * will get the instruction in the basic block after the one we've
282 * removed.
283 */
284 fs_inst *prev = (fs_inst *)inst->prev;
285
286 inst->remove(block);
287 inst = prev;
288 }
289 }
290
291 foreach_in_list_safe(aeb_entry, entry, &aeb) {
292 /* Kill all AEB entries that write a different value to or read from
293 * the flag register if we just wrote it.
294 */
295 if (inst->writes_flag()) {
296 bool negate; /* dummy */
297 if (entry->generator->reads_flag() ||
298 (entry->generator->writes_flag() &&
299 !instructions_match(inst, entry->generator, &negate))) {
300 entry->remove();
301 ralloc_free(entry);
302 continue;
303 }
304 }
305
306 for (int i = 0; i < entry->generator->sources; i++) {
307 fs_reg *src_reg = &entry->generator->src[i];
308
309 /* Kill all AEB entries that use the destination we just
310 * overwrote.
311 */
312 if (inst->overwrites_reg(entry->generator->src[i])) {
313 entry->remove();
314 ralloc_free(entry);
315 break;
316 }
317
318 /* Kill any AEB entries using registers that don't get reused any
319 * more -- a sure sign they'll fail operands_match().
320 */
321 if (src_reg->file == GRF && virtual_grf_end[src_reg->reg] < ip) {
322 entry->remove();
323 ralloc_free(entry);
324 break;
325 }
326 }
327 }
328
329 ip++;
330 }
331
332 ralloc_free(cse_ctx);
333
334 return progress;
335 }
336
337 bool
338 fs_visitor::opt_cse()
339 {
340 bool progress = false;
341
342 calculate_live_intervals();
343
344 foreach_block (block, cfg) {
345 progress = opt_cse_local(block) || progress;
346 }
347
348 if (progress)
349 invalidate_live_intervals();
350
351 return progress;
352 }