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i965: Add basic block generator.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_emit.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_emit.cpp
25 *
26 * This file supports emitting code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_fs_cfg.h"
38 #include "glsl/ir_print_visitor.h"
39
40 void
41 fs_visitor::patch_discard_jumps_to_fb_writes()
42 {
43 if (intel->gen < 6 || this->discard_halt_patches.is_empty())
44 return;
45
46 /* There is a somewhat strange undocumented requirement of using
47 * HALT, according to the simulator. If some channel has HALTed to
48 * a particular UIP, then by the end of the program, every channel
49 * must have HALTed to that UIP. Furthermore, the tracking is a
50 * stack, so you can't do the final halt of a UIP after starting
51 * halting to a new UIP.
52 *
53 * Symptoms of not emitting this instruction on actual hardware
54 * included GPU hangs and sparkly rendering on the piglit discard
55 * tests.
56 */
57 struct brw_instruction *last_halt = gen6_HALT(p);
58 last_halt->bits3.break_cont.uip = 2;
59 last_halt->bits3.break_cont.jip = 2;
60
61 int ip = p->nr_insn;
62
63 foreach_list(node, &this->discard_halt_patches) {
64 ip_record *patch_ip = (ip_record *)node;
65 struct brw_instruction *patch = &p->store[patch_ip->ip];
66 int br = (intel->gen >= 5) ? 2 : 1;
67
68 /* HALT takes a distance from the pre-incremented IP, so '1'
69 * would be the next instruction after jmpi.
70 */
71 assert(patch->header.opcode == BRW_OPCODE_HALT);
72 patch->bits3.break_cont.uip = (ip - patch_ip->ip) * br;
73 }
74
75 this->discard_halt_patches.make_empty();
76 }
77
78 void
79 fs_visitor::generate_fb_write(fs_inst *inst)
80 {
81 bool eot = inst->eot;
82 struct brw_reg implied_header;
83
84 /* Note that the jumps emitted to this point mean that the g0 ->
85 * base_mrf setup must be inside of this function, so that we jump
86 * to a point containing it.
87 */
88 patch_discard_jumps_to_fb_writes();
89
90 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
91 * move, here's g1.
92 */
93 brw_push_insn_state(p);
94 brw_set_mask_control(p, BRW_MASK_DISABLE);
95 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
96
97 if (inst->header_present) {
98 if (intel->gen >= 6) {
99 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
100 brw_MOV(p,
101 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
102 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
103 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
104
105 if (inst->target > 0) {
106 /* Set the render target index for choosing BLEND_STATE. */
107 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
108 inst->base_mrf, 2),
109 BRW_REGISTER_TYPE_UD),
110 brw_imm_ud(inst->target));
111 }
112
113 implied_header = brw_null_reg();
114 } else {
115 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
116
117 brw_MOV(p,
118 brw_message_reg(inst->base_mrf + 1),
119 brw_vec8_grf(1, 0));
120 }
121 } else {
122 implied_header = brw_null_reg();
123 }
124
125 brw_pop_insn_state(p);
126
127 brw_fb_WRITE(p,
128 c->dispatch_width,
129 inst->base_mrf,
130 implied_header,
131 inst->target,
132 inst->mlen,
133 0,
134 eot,
135 inst->header_present);
136 }
137
138 /* Computes the integer pixel x,y values from the origin.
139 *
140 * This is the basis of gl_FragCoord computation, but is also used
141 * pre-gen6 for computing the deltas from v0 for computing
142 * interpolation.
143 */
144 void
145 fs_visitor::generate_pixel_xy(struct brw_reg dst, bool is_x)
146 {
147 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
148 struct brw_reg src;
149 struct brw_reg deltas;
150
151 if (is_x) {
152 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
153 deltas = brw_imm_v(0x10101010);
154 } else {
155 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
156 deltas = brw_imm_v(0x11001100);
157 }
158
159 if (c->dispatch_width == 16) {
160 dst = vec16(dst);
161 }
162
163 /* We do this 8 or 16-wide, but since the destination is UW we
164 * don't do compression in the 16-wide case.
165 */
166 brw_push_insn_state(p);
167 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
168 brw_ADD(p, dst, src, deltas);
169 brw_pop_insn_state(p);
170 }
171
172 void
173 fs_visitor::generate_linterp(fs_inst *inst,
174 struct brw_reg dst, struct brw_reg *src)
175 {
176 struct brw_reg delta_x = src[0];
177 struct brw_reg delta_y = src[1];
178 struct brw_reg interp = src[2];
179
180 if (brw->has_pln &&
181 delta_y.nr == delta_x.nr + 1 &&
182 (intel->gen >= 6 || (delta_x.nr & 1) == 0)) {
183 brw_PLN(p, dst, interp, delta_x);
184 } else {
185 brw_LINE(p, brw_null_reg(), interp, delta_x);
186 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
187 }
188 }
189
190 void
191 fs_visitor::generate_math1_gen7(fs_inst *inst,
192 struct brw_reg dst,
193 struct brw_reg src0)
194 {
195 assert(inst->mlen == 0);
196 brw_math(p, dst,
197 brw_math_function(inst->opcode),
198 inst->saturate ? BRW_MATH_SATURATE_SATURATE
199 : BRW_MATH_SATURATE_NONE,
200 0, src0,
201 BRW_MATH_DATA_VECTOR,
202 BRW_MATH_PRECISION_FULL);
203 }
204
205 void
206 fs_visitor::generate_math2_gen7(fs_inst *inst,
207 struct brw_reg dst,
208 struct brw_reg src0,
209 struct brw_reg src1)
210 {
211 assert(inst->mlen == 0);
212 brw_math2(p, dst, brw_math_function(inst->opcode), src0, src1);
213 }
214
215 void
216 fs_visitor::generate_math1_gen6(fs_inst *inst,
217 struct brw_reg dst,
218 struct brw_reg src0)
219 {
220 int op = brw_math_function(inst->opcode);
221
222 assert(inst->mlen == 0);
223
224 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
225 brw_math(p, dst,
226 op,
227 inst->saturate ? BRW_MATH_SATURATE_SATURATE :
228 BRW_MATH_SATURATE_NONE,
229 0, src0,
230 BRW_MATH_DATA_VECTOR,
231 BRW_MATH_PRECISION_FULL);
232
233 if (c->dispatch_width == 16) {
234 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
235 brw_math(p, sechalf(dst),
236 op,
237 inst->saturate ? BRW_MATH_SATURATE_SATURATE :
238 BRW_MATH_SATURATE_NONE,
239 0, sechalf(src0),
240 BRW_MATH_DATA_VECTOR,
241 BRW_MATH_PRECISION_FULL);
242 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
243 }
244 }
245
246 void
247 fs_visitor::generate_math2_gen6(fs_inst *inst,
248 struct brw_reg dst,
249 struct brw_reg src0,
250 struct brw_reg src1)
251 {
252 int op = brw_math_function(inst->opcode);
253
254 assert(inst->mlen == 0);
255
256 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
257 brw_math2(p, dst, op, src0, src1);
258
259 if (c->dispatch_width == 16) {
260 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
261 brw_math2(p, sechalf(dst), op, sechalf(src0), sechalf(src1));
262 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
263 }
264 }
265
266 void
267 fs_visitor::generate_math_gen4(fs_inst *inst,
268 struct brw_reg dst,
269 struct brw_reg src)
270 {
271 int op = brw_math_function(inst->opcode);
272
273 assert(inst->mlen >= 1);
274
275 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
276 brw_math(p, dst,
277 op,
278 inst->saturate ? BRW_MATH_SATURATE_SATURATE :
279 BRW_MATH_SATURATE_NONE,
280 inst->base_mrf, src,
281 BRW_MATH_DATA_VECTOR,
282 BRW_MATH_PRECISION_FULL);
283
284 if (c->dispatch_width == 16) {
285 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
286 brw_math(p, sechalf(dst),
287 op,
288 inst->saturate ? BRW_MATH_SATURATE_SATURATE :
289 BRW_MATH_SATURATE_NONE,
290 inst->base_mrf + 1, sechalf(src),
291 BRW_MATH_DATA_VECTOR,
292 BRW_MATH_PRECISION_FULL);
293
294 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
295 }
296 }
297
298 void
299 fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
300 {
301 int msg_type = -1;
302 int rlen = 4;
303 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
304 uint32_t return_format;
305
306 switch (dst.type) {
307 case BRW_REGISTER_TYPE_D:
308 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
309 break;
310 case BRW_REGISTER_TYPE_UD:
311 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
312 break;
313 default:
314 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
315 break;
316 }
317
318 if (c->dispatch_width == 16)
319 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
320
321 if (intel->gen >= 5) {
322 switch (inst->opcode) {
323 case SHADER_OPCODE_TEX:
324 if (inst->shadow_compare) {
325 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
326 } else {
327 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
328 }
329 break;
330 case FS_OPCODE_TXB:
331 if (inst->shadow_compare) {
332 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
333 } else {
334 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
335 }
336 break;
337 case SHADER_OPCODE_TXL:
338 if (inst->shadow_compare) {
339 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
340 } else {
341 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
342 }
343 break;
344 case SHADER_OPCODE_TXS:
345 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
346 break;
347 case SHADER_OPCODE_TXD:
348 /* There is no sample_d_c message; comparisons are done manually */
349 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
350 break;
351 case SHADER_OPCODE_TXF:
352 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
353 break;
354 default:
355 assert(!"not reached");
356 break;
357 }
358 } else {
359 switch (inst->opcode) {
360 case SHADER_OPCODE_TEX:
361 /* Note that G45 and older determines shadow compare and dispatch width
362 * from message length for most messages.
363 */
364 assert(c->dispatch_width == 8);
365 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
366 if (inst->shadow_compare) {
367 assert(inst->mlen == 6);
368 } else {
369 assert(inst->mlen <= 4);
370 }
371 break;
372 case FS_OPCODE_TXB:
373 if (inst->shadow_compare) {
374 assert(inst->mlen == 6);
375 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
376 } else {
377 assert(inst->mlen == 9);
378 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
379 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
380 }
381 break;
382 case SHADER_OPCODE_TXL:
383 if (inst->shadow_compare) {
384 assert(inst->mlen == 6);
385 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
386 } else {
387 assert(inst->mlen == 9);
388 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
389 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
390 }
391 break;
392 case SHADER_OPCODE_TXD:
393 /* There is no sample_d_c message; comparisons are done manually */
394 assert(inst->mlen == 7 || inst->mlen == 10);
395 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
396 break;
397 case SHADER_OPCODE_TXF:
398 assert(inst->mlen == 9);
399 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
400 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
401 break;
402 case SHADER_OPCODE_TXS:
403 assert(inst->mlen == 3);
404 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
405 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
406 break;
407 default:
408 assert(!"not reached");
409 break;
410 }
411 }
412 assert(msg_type != -1);
413
414 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
415 rlen = 8;
416 dst = vec16(dst);
417 }
418
419 brw_SAMPLE(p,
420 retype(dst, BRW_REGISTER_TYPE_UW),
421 inst->base_mrf,
422 src,
423 SURF_INDEX_TEXTURE(inst->sampler),
424 inst->sampler,
425 WRITEMASK_XYZW,
426 msg_type,
427 rlen,
428 inst->mlen,
429 inst->header_present,
430 simd_mode,
431 return_format);
432 }
433
434
435 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
436 * looking like:
437 *
438 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
439 *
440 * and we're trying to produce:
441 *
442 * DDX DDY
443 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
444 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
445 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
446 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
447 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
448 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
449 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
450 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
451 *
452 * and add another set of two more subspans if in 16-pixel dispatch mode.
453 *
454 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
455 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
456 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
457 * between each other. We could probably do it like ddx and swizzle the right
458 * order later, but bail for now and just produce
459 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
460 */
461 void
462 fs_visitor::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
463 {
464 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
465 BRW_REGISTER_TYPE_F,
466 BRW_VERTICAL_STRIDE_2,
467 BRW_WIDTH_2,
468 BRW_HORIZONTAL_STRIDE_0,
469 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
470 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
471 BRW_REGISTER_TYPE_F,
472 BRW_VERTICAL_STRIDE_2,
473 BRW_WIDTH_2,
474 BRW_HORIZONTAL_STRIDE_0,
475 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
476 brw_ADD(p, dst, src0, negate(src1));
477 }
478
479 void
480 fs_visitor::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
481 {
482 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
483 BRW_REGISTER_TYPE_F,
484 BRW_VERTICAL_STRIDE_4,
485 BRW_WIDTH_4,
486 BRW_HORIZONTAL_STRIDE_0,
487 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
488 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
489 BRW_REGISTER_TYPE_F,
490 BRW_VERTICAL_STRIDE_4,
491 BRW_WIDTH_4,
492 BRW_HORIZONTAL_STRIDE_0,
493 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
494 brw_ADD(p, dst, src0, negate(src1));
495 }
496
497 void
498 fs_visitor::generate_discard(fs_inst *inst)
499 {
500 struct brw_reg f0 = brw_flag_reg();
501
502 if (intel->gen >= 6) {
503 struct brw_reg g1 = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
504 struct brw_reg some_register;
505
506 /* As of gen6, we no longer have the mask register to look at,
507 * so life gets a bit more complicated.
508 */
509
510 /* Load the flag register with all ones. */
511 brw_push_insn_state(p);
512 brw_set_mask_control(p, BRW_MASK_DISABLE);
513 brw_MOV(p, f0, brw_imm_uw(0xffff));
514 brw_pop_insn_state(p);
515
516 /* Do a comparison that should always fail, to produce 0s in the flag
517 * reg where we have active channels.
518 */
519 some_register = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
520 brw_CMP(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
521 BRW_CONDITIONAL_NZ, some_register, some_register);
522
523 /* Undo CMP's whacking of predication*/
524 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
525
526 brw_push_insn_state(p);
527 brw_set_mask_control(p, BRW_MASK_DISABLE);
528 brw_AND(p, g1, f0, g1);
529 brw_pop_insn_state(p);
530
531 /* GLSL 1.30+ say that discarded channels should stop executing
532 * (so, for example, an infinite loop that would otherwise in
533 * just that channel does not occur.
534 *
535 * This HALT will be patched up at FB write time to point UIP at
536 * the end of the program, and at brw_uip_jip() JIP will be set
537 * to the end of the current block (or the program).
538 */
539 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
540 gen6_HALT(p);
541 } else {
542 struct brw_reg g0 = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
543
544 brw_push_insn_state(p);
545 brw_set_mask_control(p, BRW_MASK_DISABLE);
546 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
547
548 /* Unlike the 965, we have the mask reg, so we just need
549 * somewhere to invert that (containing channels to be disabled)
550 * so it can be ANDed with the mask of pixels still to be
551 * written. Use the flag reg for consistency with gen6+.
552 */
553 brw_NOT(p, f0, brw_mask_reg(1)); /* IMASK */
554 brw_AND(p, g0, f0, g0);
555
556 brw_pop_insn_state(p);
557 }
558 }
559
560 void
561 fs_visitor::generate_spill(fs_inst *inst, struct brw_reg src)
562 {
563 assert(inst->mlen != 0);
564
565 brw_MOV(p,
566 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
567 retype(src, BRW_REGISTER_TYPE_UD));
568 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf), 1,
569 inst->offset);
570 }
571
572 void
573 fs_visitor::generate_unspill(fs_inst *inst, struct brw_reg dst)
574 {
575 assert(inst->mlen != 0);
576
577 /* Clear any post destination dependencies that would be ignored by
578 * the block read. See the B-Spec for pre-gen5 send instruction.
579 *
580 * This could use a better solution, since texture sampling and
581 * math reads could potentially run into it as well -- anywhere
582 * that we have a SEND with a destination that is a register that
583 * was written but not read within the last N instructions (what's
584 * N? unsure). This is rare because of dead code elimination, but
585 * not impossible.
586 */
587 if (intel->gen == 4 && !intel->is_g4x)
588 brw_MOV(p, brw_null_reg(), dst);
589
590 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf), 1,
591 inst->offset);
592
593 if (intel->gen == 4 && !intel->is_g4x) {
594 /* gen4 errata: destination from a send can't be used as a
595 * destination until it's been read. Just read it so we don't
596 * have to worry.
597 */
598 brw_MOV(p, brw_null_reg(), dst);
599 }
600 }
601
602 void
603 fs_visitor::generate_pull_constant_load(fs_inst *inst, struct brw_reg dst)
604 {
605 assert(inst->mlen != 0);
606
607 /* Clear any post destination dependencies that would be ignored by
608 * the block read. See the B-Spec for pre-gen5 send instruction.
609 *
610 * This could use a better solution, since texture sampling and
611 * math reads could potentially run into it as well -- anywhere
612 * that we have a SEND with a destination that is a register that
613 * was written but not read within the last N instructions (what's
614 * N? unsure). This is rare because of dead code elimination, but
615 * not impossible.
616 */
617 if (intel->gen == 4 && !intel->is_g4x)
618 brw_MOV(p, brw_null_reg(), dst);
619
620 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
621 inst->offset, SURF_INDEX_FRAG_CONST_BUFFER);
622
623 if (intel->gen == 4 && !intel->is_g4x) {
624 /* gen4 errata: destination from a send can't be used as a
625 * destination until it's been read. Just read it so we don't
626 * have to worry.
627 */
628 brw_MOV(p, brw_null_reg(), dst);
629 }
630 }
631
632 static uint32_t brw_file_from_reg(fs_reg *reg)
633 {
634 switch (reg->file) {
635 case ARF:
636 return BRW_ARCHITECTURE_REGISTER_FILE;
637 case GRF:
638 return BRW_GENERAL_REGISTER_FILE;
639 case MRF:
640 return BRW_MESSAGE_REGISTER_FILE;
641 case IMM:
642 return BRW_IMMEDIATE_VALUE;
643 default:
644 assert(!"not reached");
645 return BRW_GENERAL_REGISTER_FILE;
646 }
647 }
648
649 static struct brw_reg
650 brw_reg_from_fs_reg(fs_reg *reg)
651 {
652 struct brw_reg brw_reg;
653
654 switch (reg->file) {
655 case GRF:
656 case ARF:
657 case MRF:
658 if (reg->smear == -1) {
659 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
660 } else {
661 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, reg->smear);
662 }
663 brw_reg = retype(brw_reg, reg->type);
664 if (reg->sechalf)
665 brw_reg = sechalf(brw_reg);
666 break;
667 case IMM:
668 switch (reg->type) {
669 case BRW_REGISTER_TYPE_F:
670 brw_reg = brw_imm_f(reg->imm.f);
671 break;
672 case BRW_REGISTER_TYPE_D:
673 brw_reg = brw_imm_d(reg->imm.i);
674 break;
675 case BRW_REGISTER_TYPE_UD:
676 brw_reg = brw_imm_ud(reg->imm.u);
677 break;
678 default:
679 assert(!"not reached");
680 brw_reg = brw_null_reg();
681 break;
682 }
683 break;
684 case FIXED_HW_REG:
685 brw_reg = reg->fixed_hw_reg;
686 break;
687 case BAD_FILE:
688 /* Probably unused. */
689 brw_reg = brw_null_reg();
690 break;
691 case UNIFORM:
692 assert(!"not reached");
693 brw_reg = brw_null_reg();
694 break;
695 default:
696 assert(!"not reached");
697 brw_reg = brw_null_reg();
698 break;
699 }
700 if (reg->abs)
701 brw_reg = brw_abs(brw_reg);
702 if (reg->negate)
703 brw_reg = negate(brw_reg);
704
705 return brw_reg;
706 }
707
708 void
709 fs_visitor::generate_code()
710 {
711 int last_native_inst = p->nr_insn;
712 const char *last_annotation_string = NULL;
713 ir_instruction *last_annotation_ir = NULL;
714
715 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
716 printf("Native code for fragment shader %d (%d-wide dispatch):\n",
717 prog->Name, c->dispatch_width);
718 }
719
720 fs_cfg *cfg = NULL;
721 if (unlikely(INTEL_DEBUG & DEBUG_WM))
722 cfg = new(mem_ctx) fs_cfg(this);
723
724 foreach_list(node, &this->instructions) {
725 fs_inst *inst = (fs_inst *)node;
726 struct brw_reg src[3], dst;
727
728 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
729 foreach_list(node, &cfg->block_list) {
730 fs_bblock_link *link = (fs_bblock_link *)node;
731 fs_bblock *block = link->block;
732
733 if (block->start == inst) {
734 printf(" START B%d", block->block_num);
735 foreach_list(predecessor_node, &block->parents) {
736 fs_bblock_link *predecessor_link =
737 (fs_bblock_link *)predecessor_node;
738 fs_bblock *predecessor_block = predecessor_link->block;
739 printf(" <-B%d", predecessor_block->block_num);
740 }
741 printf("\n");
742 }
743 }
744
745 if (last_annotation_ir != inst->ir) {
746 last_annotation_ir = inst->ir;
747 if (last_annotation_ir) {
748 printf(" ");
749 last_annotation_ir->print();
750 printf("\n");
751 }
752 }
753 if (last_annotation_string != inst->annotation) {
754 last_annotation_string = inst->annotation;
755 if (last_annotation_string)
756 printf(" %s\n", last_annotation_string);
757 }
758 }
759
760 for (unsigned int i = 0; i < 3; i++) {
761 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
762
763 /* The accumulator result appears to get used for the
764 * conditional modifier generation. When negating a UD
765 * value, there is a 33rd bit generated for the sign in the
766 * accumulator value, so now you can't check, for example,
767 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
768 */
769 assert(!inst->conditional_mod ||
770 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
771 !inst->src[i].negate);
772 }
773 dst = brw_reg_from_fs_reg(&inst->dst);
774
775 brw_set_conditionalmod(p, inst->conditional_mod);
776 brw_set_predicate_control(p, inst->predicated);
777 brw_set_predicate_inverse(p, inst->predicate_inverse);
778 brw_set_saturate(p, inst->saturate);
779
780 if (inst->force_uncompressed || c->dispatch_width == 8) {
781 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
782 } else if (inst->force_sechalf) {
783 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
784 } else {
785 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
786 }
787
788 switch (inst->opcode) {
789 case BRW_OPCODE_MOV:
790 brw_MOV(p, dst, src[0]);
791 break;
792 case BRW_OPCODE_ADD:
793 brw_ADD(p, dst, src[0], src[1]);
794 break;
795 case BRW_OPCODE_MUL:
796 brw_MUL(p, dst, src[0], src[1]);
797 break;
798 case BRW_OPCODE_MACH:
799 brw_set_acc_write_control(p, 1);
800 brw_MACH(p, dst, src[0], src[1]);
801 brw_set_acc_write_control(p, 0);
802 break;
803
804 case BRW_OPCODE_MAD:
805 brw_set_access_mode(p, BRW_ALIGN_16);
806 if (c->dispatch_width == 16) {
807 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
808 brw_MAD(p, dst, src[0], src[1], src[2]);
809 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
810 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
811 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
812 } else {
813 brw_MAD(p, dst, src[0], src[1], src[2]);
814 }
815 brw_set_access_mode(p, BRW_ALIGN_1);
816 break;
817
818 case BRW_OPCODE_FRC:
819 brw_FRC(p, dst, src[0]);
820 break;
821 case BRW_OPCODE_RNDD:
822 brw_RNDD(p, dst, src[0]);
823 break;
824 case BRW_OPCODE_RNDE:
825 brw_RNDE(p, dst, src[0]);
826 break;
827 case BRW_OPCODE_RNDZ:
828 brw_RNDZ(p, dst, src[0]);
829 break;
830
831 case BRW_OPCODE_AND:
832 brw_AND(p, dst, src[0], src[1]);
833 break;
834 case BRW_OPCODE_OR:
835 brw_OR(p, dst, src[0], src[1]);
836 break;
837 case BRW_OPCODE_XOR:
838 brw_XOR(p, dst, src[0], src[1]);
839 break;
840 case BRW_OPCODE_NOT:
841 brw_NOT(p, dst, src[0]);
842 break;
843 case BRW_OPCODE_ASR:
844 brw_ASR(p, dst, src[0], src[1]);
845 break;
846 case BRW_OPCODE_SHR:
847 brw_SHR(p, dst, src[0], src[1]);
848 break;
849 case BRW_OPCODE_SHL:
850 brw_SHL(p, dst, src[0], src[1]);
851 break;
852
853 case BRW_OPCODE_CMP:
854 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
855 break;
856 case BRW_OPCODE_SEL:
857 brw_SEL(p, dst, src[0], src[1]);
858 break;
859
860 case BRW_OPCODE_IF:
861 if (inst->src[0].file != BAD_FILE) {
862 /* The instruction has an embedded compare (only allowed on gen6) */
863 assert(intel->gen == 6);
864 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
865 } else {
866 brw_IF(p, c->dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
867 }
868 break;
869
870 case BRW_OPCODE_ELSE:
871 brw_ELSE(p);
872 break;
873 case BRW_OPCODE_ENDIF:
874 brw_ENDIF(p);
875 break;
876
877 case BRW_OPCODE_DO:
878 brw_DO(p, BRW_EXECUTE_8);
879 break;
880
881 case BRW_OPCODE_BREAK:
882 brw_BREAK(p);
883 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
884 break;
885 case BRW_OPCODE_CONTINUE:
886 /* FINISHME: We need to write the loop instruction support still. */
887 if (intel->gen >= 6)
888 gen6_CONT(p);
889 else
890 brw_CONT(p);
891 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
892 break;
893
894 case BRW_OPCODE_WHILE:
895 brw_WHILE(p);
896 break;
897
898 case SHADER_OPCODE_RCP:
899 case SHADER_OPCODE_RSQ:
900 case SHADER_OPCODE_SQRT:
901 case SHADER_OPCODE_EXP2:
902 case SHADER_OPCODE_LOG2:
903 case SHADER_OPCODE_SIN:
904 case SHADER_OPCODE_COS:
905 if (intel->gen >= 7) {
906 generate_math1_gen7(inst, dst, src[0]);
907 } else if (intel->gen == 6) {
908 generate_math1_gen6(inst, dst, src[0]);
909 } else {
910 generate_math_gen4(inst, dst, src[0]);
911 }
912 break;
913 case SHADER_OPCODE_INT_QUOTIENT:
914 case SHADER_OPCODE_INT_REMAINDER:
915 case SHADER_OPCODE_POW:
916 if (intel->gen >= 7) {
917 generate_math2_gen7(inst, dst, src[0], src[1]);
918 } else if (intel->gen == 6) {
919 generate_math2_gen6(inst, dst, src[0], src[1]);
920 } else {
921 generate_math_gen4(inst, dst, src[0]);
922 }
923 break;
924 case FS_OPCODE_PIXEL_X:
925 generate_pixel_xy(dst, true);
926 break;
927 case FS_OPCODE_PIXEL_Y:
928 generate_pixel_xy(dst, false);
929 break;
930 case FS_OPCODE_CINTERP:
931 brw_MOV(p, dst, src[0]);
932 break;
933 case FS_OPCODE_LINTERP:
934 generate_linterp(inst, dst, src);
935 break;
936 case SHADER_OPCODE_TEX:
937 case FS_OPCODE_TXB:
938 case SHADER_OPCODE_TXD:
939 case SHADER_OPCODE_TXF:
940 case SHADER_OPCODE_TXL:
941 case SHADER_OPCODE_TXS:
942 generate_tex(inst, dst, src[0]);
943 break;
944 case FS_OPCODE_DISCARD:
945 generate_discard(inst);
946 break;
947 case FS_OPCODE_DDX:
948 generate_ddx(inst, dst, src[0]);
949 break;
950 case FS_OPCODE_DDY:
951 generate_ddy(inst, dst, src[0]);
952 break;
953
954 case FS_OPCODE_SPILL:
955 generate_spill(inst, src[0]);
956 break;
957
958 case FS_OPCODE_UNSPILL:
959 generate_unspill(inst, dst);
960 break;
961
962 case FS_OPCODE_PULL_CONSTANT_LOAD:
963 generate_pull_constant_load(inst, dst);
964 break;
965
966 case FS_OPCODE_FB_WRITE:
967 generate_fb_write(inst);
968 break;
969 default:
970 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
971 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
972 brw_opcodes[inst->opcode].name);
973 } else {
974 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
975 }
976 fail("unsupported opcode in FS\n");
977 }
978
979 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
980 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) {
981 if (0) {
982 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
983 ((uint32_t *)&p->store[i])[3],
984 ((uint32_t *)&p->store[i])[2],
985 ((uint32_t *)&p->store[i])[1],
986 ((uint32_t *)&p->store[i])[0]);
987 }
988 brw_disasm(stdout, &p->store[i], intel->gen);
989 }
990
991 foreach_list(node, &cfg->block_list) {
992 fs_bblock_link *link = (fs_bblock_link *)node;
993 fs_bblock *block = link->block;
994
995 if (block->end == inst) {
996 printf(" END B%d", block->block_num);
997 foreach_list(successor_node, &block->children) {
998 fs_bblock_link *successor_link =
999 (fs_bblock_link *)successor_node;
1000 fs_bblock *successor_block = successor_link->block;
1001 printf(" ->B%d", successor_block->block_num);
1002 }
1003 printf("\n");
1004 }
1005 }
1006 }
1007
1008 last_native_inst = p->nr_insn;
1009 }
1010
1011 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1012 printf("\n");
1013 }
1014
1015 brw_set_uip_jip(p);
1016
1017 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
1018 * emit issues, it doesn't get the jump distances into the output,
1019 * which is often something we want to debug. So this is here in
1020 * case you're doing that.
1021 */
1022 if (0) {
1023 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1024 for (unsigned int i = 0; i < p->nr_insn; i++) {
1025 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
1026 ((uint32_t *)&p->store[i])[3],
1027 ((uint32_t *)&p->store[i])[2],
1028 ((uint32_t *)&p->store[i])[1],
1029 ((uint32_t *)&p->store[i])[0]);
1030 brw_disasm(stdout, &p->store[i], intel->gen);
1031 }
1032 }
1033 }
1034 }