2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_emit.cpp
26 * This file supports emitting code from the FS LIR to the actual
27 * native instructions.
31 #include "main/macros.h"
32 #include "brw_context.h"
38 #include "glsl/ir_print_visitor.h"
40 fs_generator::fs_generator(struct brw_context
*brw
,
41 struct brw_wm_compile
*c
,
42 struct gl_shader_program
*prog
,
43 struct gl_fragment_program
*fp
,
44 bool dual_source_output
)
46 : brw(brw
), c(c
), prog(prog
), fp(fp
), dual_source_output(dual_source_output
)
51 shader
= prog
? prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
] : NULL
;
55 p
= rzalloc(mem_ctx
, struct brw_compile
);
56 brw_init_compile(brw
, p
, mem_ctx
);
59 fs_generator::~fs_generator()
64 fs_generator::patch_discard_jumps_to_fb_writes()
66 if (intel
->gen
< 6 || this->discard_halt_patches
.is_empty())
69 /* There is a somewhat strange undocumented requirement of using
70 * HALT, according to the simulator. If some channel has HALTed to
71 * a particular UIP, then by the end of the program, every channel
72 * must have HALTed to that UIP. Furthermore, the tracking is a
73 * stack, so you can't do the final halt of a UIP after starting
74 * halting to a new UIP.
76 * Symptoms of not emitting this instruction on actual hardware
77 * included GPU hangs and sparkly rendering on the piglit discard
80 struct brw_instruction
*last_halt
= gen6_HALT(p
);
81 last_halt
->bits3
.break_cont
.uip
= 2;
82 last_halt
->bits3
.break_cont
.jip
= 2;
86 foreach_list(node
, &this->discard_halt_patches
) {
87 ip_record
*patch_ip
= (ip_record
*)node
;
88 struct brw_instruction
*patch
= &p
->store
[patch_ip
->ip
];
90 assert(patch
->header
.opcode
== BRW_OPCODE_HALT
);
91 /* HALT takes a half-instruction distance from the pre-incremented IP. */
92 patch
->bits3
.break_cont
.uip
= (ip
- patch_ip
->ip
) * 2;
95 this->discard_halt_patches
.make_empty();
99 fs_generator::generate_fb_write(fs_inst
*inst
)
101 bool eot
= inst
->eot
;
102 struct brw_reg implied_header
;
103 uint32_t msg_control
;
105 /* Note that the jumps emitted to this point mean that the g0 ->
106 * base_mrf setup must be inside of this function, so that we jump
107 * to a point containing it.
109 patch_discard_jumps_to_fb_writes();
111 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
114 brw_push_insn_state(p
);
115 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
116 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
119 struct brw_reg pixel_mask
;
122 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
124 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
126 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
129 if (inst
->header_present
) {
130 if (intel
->gen
>= 6) {
131 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
133 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
),
134 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
135 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
137 if (inst
->target
> 0 &&
138 c
->key
.nr_color_regions
> 1 &&
139 c
->key
.sample_alpha_to_coverage
) {
140 /* Set "Source0 Alpha Present to RenderTarget" bit in message
144 vec1(retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
)),
145 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
146 brw_imm_ud(0x1 << 11));
149 if (inst
->target
> 0) {
150 /* Set the render target index for choosing BLEND_STATE. */
151 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
,
153 BRW_REGISTER_TYPE_UD
),
154 brw_imm_ud(inst
->target
));
157 implied_header
= brw_null_reg();
159 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
162 brw_message_reg(inst
->base_mrf
+ 1),
166 implied_header
= brw_null_reg();
169 if (this->dual_source_output
)
170 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
171 else if (dispatch_width
== 16)
172 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
174 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
176 brw_pop_insn_state(p
);
187 inst
->header_present
);
190 /* Computes the integer pixel x,y values from the origin.
192 * This is the basis of gl_FragCoord computation, but is also used
193 * pre-gen6 for computing the deltas from v0 for computing
197 fs_generator::generate_pixel_xy(struct brw_reg dst
, bool is_x
)
199 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
201 struct brw_reg deltas
;
204 src
= stride(suboffset(g1_uw
, 4), 2, 4, 0);
205 deltas
= brw_imm_v(0x10101010);
207 src
= stride(suboffset(g1_uw
, 5), 2, 4, 0);
208 deltas
= brw_imm_v(0x11001100);
211 if (dispatch_width
== 16) {
215 /* We do this 8 or 16-wide, but since the destination is UW we
216 * don't do compression in the 16-wide case.
218 brw_push_insn_state(p
);
219 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
220 brw_ADD(p
, dst
, src
, deltas
);
221 brw_pop_insn_state(p
);
225 fs_generator::generate_linterp(fs_inst
*inst
,
226 struct brw_reg dst
, struct brw_reg
*src
)
228 struct brw_reg delta_x
= src
[0];
229 struct brw_reg delta_y
= src
[1];
230 struct brw_reg interp
= src
[2];
233 delta_y
.nr
== delta_x
.nr
+ 1 &&
234 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
235 brw_PLN(p
, dst
, interp
, delta_x
);
237 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
238 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
243 fs_generator::generate_math1_gen7(fs_inst
*inst
,
247 assert(inst
->mlen
== 0);
249 brw_math_function(inst
->opcode
),
251 BRW_MATH_DATA_VECTOR
,
252 BRW_MATH_PRECISION_FULL
);
256 fs_generator::generate_math2_gen7(fs_inst
*inst
,
261 assert(inst
->mlen
== 0);
262 brw_math2(p
, dst
, brw_math_function(inst
->opcode
), src0
, src1
);
266 fs_generator::generate_math1_gen6(fs_inst
*inst
,
270 int op
= brw_math_function(inst
->opcode
);
272 assert(inst
->mlen
== 0);
274 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
278 BRW_MATH_DATA_VECTOR
,
279 BRW_MATH_PRECISION_FULL
);
281 if (dispatch_width
== 16) {
282 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
283 brw_math(p
, sechalf(dst
),
286 BRW_MATH_DATA_VECTOR
,
287 BRW_MATH_PRECISION_FULL
);
288 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
293 fs_generator::generate_math2_gen6(fs_inst
*inst
,
298 int op
= brw_math_function(inst
->opcode
);
300 assert(inst
->mlen
== 0);
302 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
303 brw_math2(p
, dst
, op
, src0
, src1
);
305 if (dispatch_width
== 16) {
306 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
307 brw_math2(p
, sechalf(dst
), op
, sechalf(src0
), sechalf(src1
));
308 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
313 fs_generator::generate_math_gen4(fs_inst
*inst
,
317 int op
= brw_math_function(inst
->opcode
);
319 assert(inst
->mlen
>= 1);
321 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
325 BRW_MATH_DATA_VECTOR
,
326 BRW_MATH_PRECISION_FULL
);
328 if (dispatch_width
== 16) {
329 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
330 brw_math(p
, sechalf(dst
),
332 inst
->base_mrf
+ 1, sechalf(src
),
333 BRW_MATH_DATA_VECTOR
,
334 BRW_MATH_PRECISION_FULL
);
336 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
341 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
345 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
346 uint32_t return_format
;
349 case BRW_REGISTER_TYPE_D
:
350 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
352 case BRW_REGISTER_TYPE_UD
:
353 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
356 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
360 if (dispatch_width
== 16)
361 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
363 if (intel
->gen
>= 5) {
364 switch (inst
->opcode
) {
365 case SHADER_OPCODE_TEX
:
366 if (inst
->shadow_compare
) {
367 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
369 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
373 if (inst
->shadow_compare
) {
374 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
376 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
379 case SHADER_OPCODE_TXL
:
380 if (inst
->shadow_compare
) {
381 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
383 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
386 case SHADER_OPCODE_TXS
:
387 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
389 case SHADER_OPCODE_TXD
:
390 if (inst
->shadow_compare
) {
391 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
392 assert(intel
->is_haswell
);
393 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
395 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
398 case SHADER_OPCODE_TXF
:
399 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
402 assert(!"not reached");
406 switch (inst
->opcode
) {
407 case SHADER_OPCODE_TEX
:
408 /* Note that G45 and older determines shadow compare and dispatch width
409 * from message length for most messages.
411 assert(dispatch_width
== 8);
412 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
413 if (inst
->shadow_compare
) {
414 assert(inst
->mlen
== 6);
416 assert(inst
->mlen
<= 4);
420 if (inst
->shadow_compare
) {
421 assert(inst
->mlen
== 6);
422 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
424 assert(inst
->mlen
== 9);
425 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
426 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
429 case SHADER_OPCODE_TXL
:
430 if (inst
->shadow_compare
) {
431 assert(inst
->mlen
== 6);
432 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
434 assert(inst
->mlen
== 9);
435 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
436 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
439 case SHADER_OPCODE_TXD
:
440 /* There is no sample_d_c message; comparisons are done manually */
441 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
442 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
444 case SHADER_OPCODE_TXF
:
445 assert(inst
->mlen
== 9);
446 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
447 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
449 case SHADER_OPCODE_TXS
:
450 assert(inst
->mlen
== 3);
451 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
452 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
455 assert(!"not reached");
459 assert(msg_type
!= -1);
461 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
466 /* Load the message header if present. If there's a texture offset,
467 * we need to set it up explicitly and load the offset bitfield.
468 * Otherwise, we can use an implied move from g0 to the first message reg.
470 if (inst
->texture_offset
) {
471 brw_push_insn_state(p
);
472 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
473 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
474 /* Explicitly set up the message header by copying g0 to the MRF. */
475 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
),
476 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
478 /* Then set the offset bits in DWord 2. */
479 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
,
480 inst
->base_mrf
, 2), BRW_REGISTER_TYPE_UD
),
481 brw_imm_ud(inst
->texture_offset
));
482 brw_pop_insn_state(p
);
483 } else if (inst
->header_present
) {
484 /* Set up an implied move from g0 to the MRF. */
485 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
489 retype(dst
, BRW_REGISTER_TYPE_UW
),
492 SURF_INDEX_TEXTURE(inst
->sampler
),
497 inst
->header_present
,
503 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
506 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
508 * and we're trying to produce:
511 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
512 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
513 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
514 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
515 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
516 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
517 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
518 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
520 * and add another set of two more subspans if in 16-pixel dispatch mode.
522 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
523 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
524 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
525 * between each other. We could probably do it like ddx and swizzle the right
526 * order later, but bail for now and just produce
527 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
530 fs_generator::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
532 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
534 BRW_VERTICAL_STRIDE_2
,
536 BRW_HORIZONTAL_STRIDE_0
,
537 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
538 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
540 BRW_VERTICAL_STRIDE_2
,
542 BRW_HORIZONTAL_STRIDE_0
,
543 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
544 brw_ADD(p
, dst
, src0
, negate(src1
));
547 /* The negate_value boolean is used to negate the derivative computation for
548 * FBOs, since they place the origin at the upper left instead of the lower
552 fs_generator::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
555 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
557 BRW_VERTICAL_STRIDE_4
,
559 BRW_HORIZONTAL_STRIDE_0
,
560 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
561 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
563 BRW_VERTICAL_STRIDE_4
,
565 BRW_HORIZONTAL_STRIDE_0
,
566 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
568 brw_ADD(p
, dst
, src1
, negate(src0
));
570 brw_ADD(p
, dst
, src0
, negate(src1
));
574 fs_generator::generate_discard_jump(fs_inst
*inst
)
576 assert(intel
->gen
>= 6);
578 /* This HALT will be patched up at FB write time to point UIP at the end of
579 * the program, and at brw_uip_jip() JIP will be set to the end of the
580 * current block (or the program).
582 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
584 brw_push_insn_state(p
);
585 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
587 brw_pop_insn_state(p
);
591 fs_generator::generate_spill(fs_inst
*inst
, struct brw_reg src
)
593 assert(inst
->mlen
!= 0);
596 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
597 retype(src
, BRW_REGISTER_TYPE_UD
));
598 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
), 1,
603 fs_generator::generate_unspill(fs_inst
*inst
, struct brw_reg dst
)
605 assert(inst
->mlen
!= 0);
607 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
), 1,
612 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
614 struct brw_reg index
,
615 struct brw_reg offset
)
617 assert(inst
->mlen
!= 0);
619 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
620 index
.type
== BRW_REGISTER_TYPE_UD
);
621 uint32_t surf_index
= index
.dw1
.ud
;
623 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
624 offset
.type
== BRW_REGISTER_TYPE_UD
);
625 uint32_t read_offset
= offset
.dw1
.ud
;
627 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
628 read_offset
, surf_index
);
632 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
634 struct brw_reg index
,
635 struct brw_reg offset
)
637 assert(inst
->mlen
== 0);
639 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
640 index
.type
== BRW_REGISTER_TYPE_UD
);
641 uint32_t surf_index
= index
.dw1
.ud
;
643 assert(offset
.file
== BRW_GENERAL_REGISTER_FILE
);
645 brw_push_insn_state(p
);
646 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
647 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
648 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
649 brw_pop_insn_state(p
);
651 brw_set_dest(p
, send
, dst
);
652 brw_set_src0(p
, send
, offset
);
654 uint32_t msg_control
= BRW_DATAPORT_OWORD_BLOCK_2_OWORDS
;
655 uint32_t msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ
;
656 bool header_present
= true;
657 brw_set_dp_read_message(p
, send
,
661 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
668 fs_generator::generate_varying_pull_constant_load(fs_inst
*inst
,
670 struct brw_reg index
)
672 assert(intel
->gen
< 7); /* Should use the gen7 variant. */
673 assert(inst
->header_present
);
675 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
676 index
.type
== BRW_REGISTER_TYPE_UD
);
677 uint32_t surf_index
= index
.dw1
.ud
;
679 uint32_t msg_type
, msg_control
, rlen
;
681 msg_type
= GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ
;
682 else if (intel
->gen
== 5 || intel
->is_g4x
)
683 msg_type
= G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ
;
685 msg_type
= BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ
;
687 if (dispatch_width
== 16) {
688 msg_control
= BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS
;
691 msg_control
= BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS
;
695 struct brw_reg header
= brw_vec8_grf(0, 0);
696 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
698 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
699 brw_set_dest(p
, send
, dst
);
700 brw_set_src0(p
, send
, header
);
702 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
703 brw_set_dp_read_message(p
, send
,
707 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
709 inst
->header_present
,
714 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
716 struct brw_reg index
,
717 struct brw_reg offset
)
719 assert(intel
->gen
>= 7);
720 /* Varying-offset pull constant loads are treated as a normal expression on
721 * gen7, so the fact that it's a send message is hidden at the IR level.
723 assert(!inst
->header_present
);
726 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
727 index
.type
== BRW_REGISTER_TYPE_UD
);
728 uint32_t surf_index
= index
.dw1
.ud
;
730 uint32_t msg_control
, rlen
, mlen
;
731 if (dispatch_width
== 16) {
732 msg_control
= BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS
;
735 msg_control
= BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS
;
739 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
740 brw_set_dest(p
, send
, dst
);
741 brw_set_src0(p
, send
, offset
);
743 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
744 brw_set_dp_read_message(p
, send
,
747 GEN7_DATAPORT_DC_DWORD_SCATTERED_READ
,
748 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
750 inst
->header_present
,
755 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
756 * into the flags register (f0.0).
758 * Used only on Gen6 and above.
761 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
763 struct brw_reg flags
= brw_flag_reg(0, inst
->flag_subreg
);
764 struct brw_reg dispatch_mask
;
767 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
769 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
771 brw_push_insn_state(p
);
772 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
773 brw_MOV(p
, flags
, dispatch_mask
);
774 brw_pop_insn_state(p
);
778 static uint32_t brw_file_from_reg(fs_reg
*reg
)
782 return BRW_ARCHITECTURE_REGISTER_FILE
;
784 return BRW_GENERAL_REGISTER_FILE
;
786 return BRW_MESSAGE_REGISTER_FILE
;
788 return BRW_IMMEDIATE_VALUE
;
790 assert(!"not reached");
791 return BRW_GENERAL_REGISTER_FILE
;
795 static struct brw_reg
796 brw_reg_from_fs_reg(fs_reg
*reg
)
798 struct brw_reg brw_reg
;
804 if (reg
->smear
== -1) {
805 brw_reg
= brw_vec8_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
807 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->reg
, reg
->smear
);
809 brw_reg
= retype(brw_reg
, reg
->type
);
811 brw_reg
= sechalf(brw_reg
);
815 case BRW_REGISTER_TYPE_F
:
816 brw_reg
= brw_imm_f(reg
->imm
.f
);
818 case BRW_REGISTER_TYPE_D
:
819 brw_reg
= brw_imm_d(reg
->imm
.i
);
821 case BRW_REGISTER_TYPE_UD
:
822 brw_reg
= brw_imm_ud(reg
->imm
.u
);
825 assert(!"not reached");
826 brw_reg
= brw_null_reg();
831 brw_reg
= reg
->fixed_hw_reg
;
834 /* Probably unused. */
835 brw_reg
= brw_null_reg();
838 assert(!"not reached");
839 brw_reg
= brw_null_reg();
842 assert(!"not reached");
843 brw_reg
= brw_null_reg();
847 brw_reg
= brw_abs(brw_reg
);
849 brw_reg
= negate(brw_reg
);
855 * Sets the second dword of a vgrf for gen7+ message setup.
857 * For setting up gen7 messages in VGRFs, we need to be able to set the second
858 * dword for some payloads where in the MRF world we'd have just used
859 * brw_message_reg(). We don't want to bake it into the send message's code
860 * generation because that means we don't get a chance to schedule the
864 fs_generator::generate_set_global_offset(fs_inst
*inst
,
867 struct brw_reg value
)
869 /* We use a matching src and dst to get the information on how this
870 * instruction works exposed to various optimization passes that would
871 * otherwise treat it as completely overwriting the dst.
873 assert(src
.file
== dst
.file
&& src
.nr
== dst
.nr
);
874 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
876 brw_push_insn_state(p
);
877 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
878 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
879 brw_MOV(p
, retype(brw_vec1_reg(dst
.file
, dst
.nr
, 2), value
.type
), value
);
880 brw_pop_insn_state(p
);
884 * Change the register's data type from UD to W, doubling the strides in order
885 * to compensate for halving the data type width.
887 static struct brw_reg
888 ud_reg_to_w(struct brw_reg r
)
890 assert(r
.type
== BRW_REGISTER_TYPE_UD
);
891 r
.type
= BRW_REGISTER_TYPE_W
;
893 /* The BRW_*_STRIDE enums are defined so that incrementing the field
894 * doubles the real stride.
905 fs_generator::generate_pack_half_2x16_split(fs_inst
*inst
,
910 assert(intel
->gen
>= 7);
911 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
912 assert(x
.type
== BRW_REGISTER_TYPE_F
);
913 assert(y
.type
== BRW_REGISTER_TYPE_F
);
915 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
917 * Because this instruction does not have a 16-bit floating-point type,
918 * the destination data type must be Word (W).
920 * The destination must be DWord-aligned and specify a horizontal stride
921 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
922 * each destination channel and the upper word is not modified.
924 struct brw_reg dst_w
= ud_reg_to_w(dst
);
926 /* Give each 32-bit channel of dst the form below , where "." means
930 brw_F32TO16(p
, dst_w
, y
);
935 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
937 /* And, finally the form of packHalf2x16's output:
940 brw_F32TO16(p
, dst_w
, x
);
944 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
948 assert(intel
->gen
>= 7);
949 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
950 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
952 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
954 * Because this instruction does not have a 16-bit floating-point type,
955 * the source data type must be Word (W). The destination type must be
958 struct brw_reg src_w
= ud_reg_to_w(src
);
960 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
961 * For the Y case, we wish to access only the upper word; therefore
962 * a 16-bit subregister offset is needed.
964 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
965 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
966 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
969 brw_F16TO32(p
, dst
, src_w
);
973 fs_generator::generate_code(exec_list
*instructions
)
975 int last_native_insn_offset
= p
->next_insn_offset
;
976 const char *last_annotation_string
= NULL
;
977 const void *last_annotation_ir
= NULL
;
979 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
981 printf("Native code for fragment shader %d (%d-wide dispatch):\n",
982 prog
->Name
, dispatch_width
);
984 printf("Native code for fragment program %d (%d-wide dispatch):\n",
985 fp
->Base
.Id
, dispatch_width
);
990 if (unlikely(INTEL_DEBUG
& DEBUG_WM
))
991 cfg
= new(mem_ctx
) cfg_t(mem_ctx
, instructions
);
993 foreach_list(node
, instructions
) {
994 fs_inst
*inst
= (fs_inst
*)node
;
995 struct brw_reg src
[3], dst
;
997 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
998 foreach_list(node
, &cfg
->block_list
) {
999 bblock_link
*link
= (bblock_link
*)node
;
1000 bblock_t
*block
= link
->block
;
1002 if (block
->start
== inst
) {
1003 printf(" START B%d", block
->block_num
);
1004 foreach_list(predecessor_node
, &block
->parents
) {
1005 bblock_link
*predecessor_link
=
1006 (bblock_link
*)predecessor_node
;
1007 bblock_t
*predecessor_block
= predecessor_link
->block
;
1008 printf(" <-B%d", predecessor_block
->block_num
);
1014 if (last_annotation_ir
!= inst
->ir
) {
1015 last_annotation_ir
= inst
->ir
;
1016 if (last_annotation_ir
) {
1019 ((ir_instruction
*)inst
->ir
)->print();
1021 const prog_instruction
*fpi
;
1022 fpi
= (const prog_instruction
*)inst
->ir
;
1023 printf("%d: ", (int)(fpi
- fp
->Base
.Instructions
));
1024 _mesa_fprint_instruction_opt(stdout
,
1026 0, PROG_PRINT_DEBUG
, NULL
);
1031 if (last_annotation_string
!= inst
->annotation
) {
1032 last_annotation_string
= inst
->annotation
;
1033 if (last_annotation_string
)
1034 printf(" %s\n", last_annotation_string
);
1038 for (unsigned int i
= 0; i
< 3; i
++) {
1039 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
1041 /* The accumulator result appears to get used for the
1042 * conditional modifier generation. When negating a UD
1043 * value, there is a 33rd bit generated for the sign in the
1044 * accumulator value, so now you can't check, for example,
1045 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1047 assert(!inst
->conditional_mod
||
1048 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1049 !inst
->src
[i
].negate
);
1051 dst
= brw_reg_from_fs_reg(&inst
->dst
);
1053 brw_set_conditionalmod(p
, inst
->conditional_mod
);
1054 brw_set_predicate_control(p
, inst
->predicate
);
1055 brw_set_predicate_inverse(p
, inst
->predicate_inverse
);
1056 brw_set_flag_reg(p
, 0, inst
->flag_subreg
);
1057 brw_set_saturate(p
, inst
->saturate
);
1058 brw_set_mask_control(p
, inst
->force_writemask_all
);
1060 if (inst
->force_uncompressed
|| dispatch_width
== 8) {
1061 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1062 } else if (inst
->force_sechalf
) {
1063 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1065 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1068 switch (inst
->opcode
) {
1069 case BRW_OPCODE_MOV
:
1070 brw_MOV(p
, dst
, src
[0]);
1072 case BRW_OPCODE_ADD
:
1073 brw_ADD(p
, dst
, src
[0], src
[1]);
1075 case BRW_OPCODE_MUL
:
1076 brw_MUL(p
, dst
, src
[0], src
[1]);
1078 case BRW_OPCODE_MACH
:
1079 brw_set_acc_write_control(p
, 1);
1080 brw_MACH(p
, dst
, src
[0], src
[1]);
1081 brw_set_acc_write_control(p
, 0);
1084 case BRW_OPCODE_MAD
:
1085 brw_set_access_mode(p
, BRW_ALIGN_16
);
1086 if (dispatch_width
== 16) {
1087 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1088 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1089 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1090 brw_MAD(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1091 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1093 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1095 brw_set_access_mode(p
, BRW_ALIGN_1
);
1098 case BRW_OPCODE_LRP
:
1099 brw_set_access_mode(p
, BRW_ALIGN_16
);
1100 if (dispatch_width
== 16) {
1101 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1102 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1103 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1104 brw_LRP(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1105 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1107 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1109 brw_set_access_mode(p
, BRW_ALIGN_1
);
1112 case BRW_OPCODE_FRC
:
1113 brw_FRC(p
, dst
, src
[0]);
1115 case BRW_OPCODE_RNDD
:
1116 brw_RNDD(p
, dst
, src
[0]);
1118 case BRW_OPCODE_RNDE
:
1119 brw_RNDE(p
, dst
, src
[0]);
1121 case BRW_OPCODE_RNDZ
:
1122 brw_RNDZ(p
, dst
, src
[0]);
1125 case BRW_OPCODE_AND
:
1126 brw_AND(p
, dst
, src
[0], src
[1]);
1129 brw_OR(p
, dst
, src
[0], src
[1]);
1131 case BRW_OPCODE_XOR
:
1132 brw_XOR(p
, dst
, src
[0], src
[1]);
1134 case BRW_OPCODE_NOT
:
1135 brw_NOT(p
, dst
, src
[0]);
1137 case BRW_OPCODE_ASR
:
1138 brw_ASR(p
, dst
, src
[0], src
[1]);
1140 case BRW_OPCODE_SHR
:
1141 brw_SHR(p
, dst
, src
[0], src
[1]);
1143 case BRW_OPCODE_SHL
:
1144 brw_SHL(p
, dst
, src
[0], src
[1]);
1146 case BRW_OPCODE_F32TO16
:
1147 brw_F32TO16(p
, dst
, src
[0]);
1149 case BRW_OPCODE_F16TO32
:
1150 brw_F16TO32(p
, dst
, src
[0]);
1152 case BRW_OPCODE_CMP
:
1153 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1155 case BRW_OPCODE_SEL
:
1156 brw_SEL(p
, dst
, src
[0], src
[1]);
1160 if (inst
->src
[0].file
!= BAD_FILE
) {
1161 /* The instruction has an embedded compare (only allowed on gen6) */
1162 assert(intel
->gen
== 6);
1163 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1165 brw_IF(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
1169 case BRW_OPCODE_ELSE
:
1172 case BRW_OPCODE_ENDIF
:
1177 brw_DO(p
, BRW_EXECUTE_8
);
1180 case BRW_OPCODE_BREAK
:
1182 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1184 case BRW_OPCODE_CONTINUE
:
1185 /* FINISHME: We need to write the loop instruction support still. */
1186 if (intel
->gen
>= 6)
1190 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1193 case BRW_OPCODE_WHILE
:
1197 case SHADER_OPCODE_RCP
:
1198 case SHADER_OPCODE_RSQ
:
1199 case SHADER_OPCODE_SQRT
:
1200 case SHADER_OPCODE_EXP2
:
1201 case SHADER_OPCODE_LOG2
:
1202 case SHADER_OPCODE_SIN
:
1203 case SHADER_OPCODE_COS
:
1204 if (intel
->gen
>= 7) {
1205 generate_math1_gen7(inst
, dst
, src
[0]);
1206 } else if (intel
->gen
== 6) {
1207 generate_math1_gen6(inst
, dst
, src
[0]);
1209 generate_math_gen4(inst
, dst
, src
[0]);
1212 case SHADER_OPCODE_INT_QUOTIENT
:
1213 case SHADER_OPCODE_INT_REMAINDER
:
1214 case SHADER_OPCODE_POW
:
1215 if (intel
->gen
>= 7) {
1216 generate_math2_gen7(inst
, dst
, src
[0], src
[1]);
1217 } else if (intel
->gen
== 6) {
1218 generate_math2_gen6(inst
, dst
, src
[0], src
[1]);
1220 generate_math_gen4(inst
, dst
, src
[0]);
1223 case FS_OPCODE_PIXEL_X
:
1224 generate_pixel_xy(dst
, true);
1226 case FS_OPCODE_PIXEL_Y
:
1227 generate_pixel_xy(dst
, false);
1229 case FS_OPCODE_CINTERP
:
1230 brw_MOV(p
, dst
, src
[0]);
1232 case FS_OPCODE_LINTERP
:
1233 generate_linterp(inst
, dst
, src
);
1235 case SHADER_OPCODE_TEX
:
1237 case SHADER_OPCODE_TXD
:
1238 case SHADER_OPCODE_TXF
:
1239 case SHADER_OPCODE_TXL
:
1240 case SHADER_OPCODE_TXS
:
1241 generate_tex(inst
, dst
, src
[0]);
1244 generate_ddx(inst
, dst
, src
[0]);
1247 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1248 * guarantee that c->key.render_to_fbo is set).
1250 assert(fp
->UsesDFdy
);
1251 generate_ddy(inst
, dst
, src
[0], c
->key
.render_to_fbo
);
1254 case FS_OPCODE_SPILL
:
1255 generate_spill(inst
, src
[0]);
1258 case FS_OPCODE_UNSPILL
:
1259 generate_unspill(inst
, dst
);
1262 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1263 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1266 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
1267 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1270 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
1271 generate_varying_pull_constant_load(inst
, dst
, src
[0]);
1274 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
1275 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1278 case FS_OPCODE_FB_WRITE
:
1279 generate_fb_write(inst
);
1282 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
1283 generate_mov_dispatch_to_flags(inst
);
1286 case FS_OPCODE_DISCARD_JUMP
:
1287 generate_discard_jump(inst
);
1290 case SHADER_OPCODE_SHADER_TIME_ADD
:
1291 brw_shader_time_add(p
, inst
->base_mrf
, SURF_INDEX_WM_SHADER_TIME
);
1294 case FS_OPCODE_SET_GLOBAL_OFFSET
:
1295 generate_set_global_offset(inst
, dst
, src
[0], src
[1]);
1298 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
1299 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
1302 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
1303 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
1304 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
1308 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
1309 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
1310 opcode_descs
[inst
->opcode
].name
);
1312 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
1317 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1318 brw_dump_compile(p
, stdout
,
1319 last_native_insn_offset
, p
->next_insn_offset
);
1321 foreach_list(node
, &cfg
->block_list
) {
1322 bblock_link
*link
= (bblock_link
*)node
;
1323 bblock_t
*block
= link
->block
;
1325 if (block
->end
== inst
) {
1326 printf(" END B%d", block
->block_num
);
1327 foreach_list(successor_node
, &block
->children
) {
1328 bblock_link
*successor_link
=
1329 (bblock_link
*)successor_node
;
1330 bblock_t
*successor_block
= successor_link
->block
;
1331 printf(" ->B%d", successor_block
->block_num
);
1338 last_native_insn_offset
= p
->next_insn_offset
;
1341 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1347 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
1348 * emit issues, it doesn't get the jump distances into the output,
1349 * which is often something we want to debug. So this is here in
1350 * case you're doing that.
1353 brw_dump_compile(p
, stdout
, 0, p
->next_insn_offset
);
1358 fs_generator::generate_assembly(exec_list
*simd8_instructions
,
1359 exec_list
*simd16_instructions
,
1360 unsigned *assembly_size
)
1363 generate_code(simd8_instructions
);
1365 if (simd16_instructions
) {
1366 /* We have to do a compaction pass now, or the one at the end of
1367 * execution will squash down where our prog_offset start needs
1370 brw_compact_instructions(p
);
1372 /* align to 64 byte boundary. */
1373 while ((p
->nr_insn
* sizeof(struct brw_instruction
)) % 64) {
1377 /* Save off the start of this 16-wide program */
1378 c
->prog_data
.prog_offset_16
= p
->nr_insn
* sizeof(struct brw_instruction
);
1380 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1382 dispatch_width
= 16;
1383 generate_code(simd16_instructions
);
1386 return brw_get_program(p
, assembly_size
);