2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_emit.cpp
26 * This file supports emitting code from the FS LIR to the actual
27 * native instructions.
31 #include "main/macros.h"
32 #include "brw_context.h"
39 fs_generator::fs_generator(struct brw_context
*brw
,
40 struct brw_wm_compile
*c
,
41 struct gl_shader_program
*prog
,
42 struct gl_fragment_program
*fp
,
43 bool dual_source_output
)
45 : brw(brw
), c(c
), prog(prog
), fp(fp
), dual_source_output(dual_source_output
)
50 shader
= prog
? prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
] : NULL
;
54 p
= rzalloc(mem_ctx
, struct brw_compile
);
55 brw_init_compile(brw
, p
, mem_ctx
);
58 fs_generator::~fs_generator()
63 fs_generator::patch_discard_jumps_to_fb_writes()
65 if (intel
->gen
< 6 || this->discard_halt_patches
.is_empty())
68 /* There is a somewhat strange undocumented requirement of using
69 * HALT, according to the simulator. If some channel has HALTed to
70 * a particular UIP, then by the end of the program, every channel
71 * must have HALTed to that UIP. Furthermore, the tracking is a
72 * stack, so you can't do the final halt of a UIP after starting
73 * halting to a new UIP.
75 * Symptoms of not emitting this instruction on actual hardware
76 * included GPU hangs and sparkly rendering on the piglit discard
79 struct brw_instruction
*last_halt
= gen6_HALT(p
);
80 last_halt
->bits3
.break_cont
.uip
= 2;
81 last_halt
->bits3
.break_cont
.jip
= 2;
85 foreach_list(node
, &this->discard_halt_patches
) {
86 ip_record
*patch_ip
= (ip_record
*)node
;
87 struct brw_instruction
*patch
= &p
->store
[patch_ip
->ip
];
89 assert(patch
->header
.opcode
== BRW_OPCODE_HALT
);
90 /* HALT takes a half-instruction distance from the pre-incremented IP. */
91 patch
->bits3
.break_cont
.uip
= (ip
- patch_ip
->ip
) * 2;
94 this->discard_halt_patches
.make_empty();
98 fs_generator::generate_fb_write(fs_inst
*inst
)
100 bool eot
= inst
->eot
;
101 struct brw_reg implied_header
;
102 uint32_t msg_control
;
104 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
107 brw_push_insn_state(p
);
108 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
109 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
112 struct brw_reg pixel_mask
;
115 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
117 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
119 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
122 if (inst
->header_present
) {
123 if (intel
->gen
>= 6) {
124 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
126 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
),
127 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
128 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
130 if (inst
->target
> 0 && c
->key
.replicate_alpha
) {
131 /* Set "Source0 Alpha Present to RenderTarget" bit in message
135 vec1(retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
)),
136 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
137 brw_imm_ud(0x1 << 11));
140 if (inst
->target
> 0) {
141 /* Set the render target index for choosing BLEND_STATE. */
142 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
,
144 BRW_REGISTER_TYPE_UD
),
145 brw_imm_ud(inst
->target
));
148 implied_header
= brw_null_reg();
150 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
153 brw_message_reg(inst
->base_mrf
+ 1),
157 implied_header
= brw_null_reg();
160 if (this->dual_source_output
)
161 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
162 else if (dispatch_width
== 16)
163 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
165 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
167 brw_pop_insn_state(p
);
178 inst
->header_present
);
181 /* Computes the integer pixel x,y values from the origin.
183 * This is the basis of gl_FragCoord computation, but is also used
184 * pre-gen6 for computing the deltas from v0 for computing
188 fs_generator::generate_pixel_xy(struct brw_reg dst
, bool is_x
)
190 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
192 struct brw_reg deltas
;
195 src
= stride(suboffset(g1_uw
, 4), 2, 4, 0);
196 deltas
= brw_imm_v(0x10101010);
198 src
= stride(suboffset(g1_uw
, 5), 2, 4, 0);
199 deltas
= brw_imm_v(0x11001100);
202 if (dispatch_width
== 16) {
206 /* We do this 8 or 16-wide, but since the destination is UW we
207 * don't do compression in the 16-wide case.
209 brw_push_insn_state(p
);
210 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
211 brw_ADD(p
, dst
, src
, deltas
);
212 brw_pop_insn_state(p
);
216 fs_generator::generate_linterp(fs_inst
*inst
,
217 struct brw_reg dst
, struct brw_reg
*src
)
219 struct brw_reg delta_x
= src
[0];
220 struct brw_reg delta_y
= src
[1];
221 struct brw_reg interp
= src
[2];
224 delta_y
.nr
== delta_x
.nr
+ 1 &&
225 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
226 brw_PLN(p
, dst
, interp
, delta_x
);
228 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
229 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
234 fs_generator::generate_math1_gen7(fs_inst
*inst
,
238 assert(inst
->mlen
== 0);
240 brw_math_function(inst
->opcode
),
242 BRW_MATH_DATA_VECTOR
,
243 BRW_MATH_PRECISION_FULL
);
247 fs_generator::generate_math2_gen7(fs_inst
*inst
,
252 assert(inst
->mlen
== 0);
253 brw_math2(p
, dst
, brw_math_function(inst
->opcode
), src0
, src1
);
257 fs_generator::generate_math1_gen6(fs_inst
*inst
,
261 int op
= brw_math_function(inst
->opcode
);
263 assert(inst
->mlen
== 0);
265 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
269 BRW_MATH_DATA_VECTOR
,
270 BRW_MATH_PRECISION_FULL
);
272 if (dispatch_width
== 16) {
273 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
274 brw_math(p
, sechalf(dst
),
277 BRW_MATH_DATA_VECTOR
,
278 BRW_MATH_PRECISION_FULL
);
279 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
284 fs_generator::generate_math2_gen6(fs_inst
*inst
,
289 int op
= brw_math_function(inst
->opcode
);
291 assert(inst
->mlen
== 0);
293 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
294 brw_math2(p
, dst
, op
, src0
, src1
);
296 if (dispatch_width
== 16) {
297 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
298 brw_math2(p
, sechalf(dst
), op
, sechalf(src0
), sechalf(src1
));
299 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
304 fs_generator::generate_math_gen4(fs_inst
*inst
,
308 int op
= brw_math_function(inst
->opcode
);
310 assert(inst
->mlen
>= 1);
312 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
316 BRW_MATH_DATA_VECTOR
,
317 BRW_MATH_PRECISION_FULL
);
319 if (dispatch_width
== 16) {
320 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
321 brw_math(p
, sechalf(dst
),
323 inst
->base_mrf
+ 1, sechalf(src
),
324 BRW_MATH_DATA_VECTOR
,
325 BRW_MATH_PRECISION_FULL
);
327 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
332 fs_generator::generate_math_g45(fs_inst
*inst
,
336 if (inst
->opcode
== SHADER_OPCODE_POW
||
337 inst
->opcode
== SHADER_OPCODE_INT_QUOTIENT
||
338 inst
->opcode
== SHADER_OPCODE_INT_REMAINDER
) {
339 generate_math_gen4(inst
, dst
, src
);
343 int op
= brw_math_function(inst
->opcode
);
345 assert(inst
->mlen
>= 1);
350 BRW_MATH_DATA_VECTOR
,
351 BRW_MATH_PRECISION_FULL
);
355 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
359 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
360 uint32_t return_format
;
363 case BRW_REGISTER_TYPE_D
:
364 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
366 case BRW_REGISTER_TYPE_UD
:
367 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
370 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
374 if (dispatch_width
== 16)
375 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
377 if (intel
->gen
>= 5) {
378 switch (inst
->opcode
) {
379 case SHADER_OPCODE_TEX
:
380 if (inst
->shadow_compare
) {
381 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
383 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
387 if (inst
->shadow_compare
) {
388 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
390 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
393 case SHADER_OPCODE_TXL
:
394 if (inst
->shadow_compare
) {
395 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
397 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
400 case SHADER_OPCODE_TXS
:
401 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
403 case SHADER_OPCODE_TXD
:
404 if (inst
->shadow_compare
) {
405 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
406 assert(intel
->is_haswell
);
407 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
409 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
412 case SHADER_OPCODE_TXF
:
413 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
415 case SHADER_OPCODE_TXF_MS
:
417 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
419 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
421 case SHADER_OPCODE_LOD
:
422 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
425 assert(!"not reached");
429 switch (inst
->opcode
) {
430 case SHADER_OPCODE_TEX
:
431 /* Note that G45 and older determines shadow compare and dispatch width
432 * from message length for most messages.
434 assert(dispatch_width
== 8);
435 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
436 if (inst
->shadow_compare
) {
437 assert(inst
->mlen
== 6);
439 assert(inst
->mlen
<= 4);
443 if (inst
->shadow_compare
) {
444 assert(inst
->mlen
== 6);
445 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
447 assert(inst
->mlen
== 9);
448 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
449 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
452 case SHADER_OPCODE_TXL
:
453 if (inst
->shadow_compare
) {
454 assert(inst
->mlen
== 6);
455 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
457 assert(inst
->mlen
== 9);
458 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
459 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
462 case SHADER_OPCODE_TXD
:
463 /* There is no sample_d_c message; comparisons are done manually */
464 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
465 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
467 case SHADER_OPCODE_TXF
:
468 assert(inst
->mlen
== 9);
469 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
470 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
472 case SHADER_OPCODE_TXS
:
473 assert(inst
->mlen
== 3);
474 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
475 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
478 assert(!"not reached");
482 assert(msg_type
!= -1);
484 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
489 /* Load the message header if present. If there's a texture offset,
490 * we need to set it up explicitly and load the offset bitfield.
491 * Otherwise, we can use an implied move from g0 to the first message reg.
493 if (inst
->texture_offset
) {
494 brw_push_insn_state(p
);
495 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
496 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
497 /* Explicitly set up the message header by copying g0 to the MRF. */
498 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
),
499 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
501 /* Then set the offset bits in DWord 2. */
502 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
,
503 inst
->base_mrf
, 2), BRW_REGISTER_TYPE_UD
),
504 brw_imm_ud(inst
->texture_offset
));
505 brw_pop_insn_state(p
);
506 } else if (inst
->header_present
) {
507 /* Set up an implied move from g0 to the MRF. */
508 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
512 retype(dst
, BRW_REGISTER_TYPE_UW
),
515 SURF_INDEX_TEXTURE(inst
->sampler
),
520 inst
->header_present
,
526 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
529 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
531 * and we're trying to produce:
534 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
535 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
536 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
537 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
538 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
539 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
540 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
541 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
543 * and add another set of two more subspans if in 16-pixel dispatch mode.
545 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
546 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
547 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
548 * between each other. We could probably do it like ddx and swizzle the right
549 * order later, but bail for now and just produce
550 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
553 fs_generator::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
555 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
557 BRW_VERTICAL_STRIDE_2
,
559 BRW_HORIZONTAL_STRIDE_0
,
560 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
561 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
563 BRW_VERTICAL_STRIDE_2
,
565 BRW_HORIZONTAL_STRIDE_0
,
566 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
567 brw_ADD(p
, dst
, src0
, negate(src1
));
570 /* The negate_value boolean is used to negate the derivative computation for
571 * FBOs, since they place the origin at the upper left instead of the lower
575 fs_generator::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
578 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
580 BRW_VERTICAL_STRIDE_4
,
582 BRW_HORIZONTAL_STRIDE_0
,
583 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
584 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
586 BRW_VERTICAL_STRIDE_4
,
588 BRW_HORIZONTAL_STRIDE_0
,
589 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
591 brw_ADD(p
, dst
, src1
, negate(src0
));
593 brw_ADD(p
, dst
, src0
, negate(src1
));
597 fs_generator::generate_discard_jump(fs_inst
*inst
)
599 assert(intel
->gen
>= 6);
601 /* This HALT will be patched up at FB write time to point UIP at the end of
602 * the program, and at brw_uip_jip() JIP will be set to the end of the
603 * current block (or the program).
605 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
607 brw_push_insn_state(p
);
608 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
610 brw_pop_insn_state(p
);
614 fs_generator::generate_spill(fs_inst
*inst
, struct brw_reg src
)
616 assert(inst
->mlen
!= 0);
619 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
620 retype(src
, BRW_REGISTER_TYPE_UD
));
621 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
), 1,
626 fs_generator::generate_unspill(fs_inst
*inst
, struct brw_reg dst
)
628 assert(inst
->mlen
!= 0);
630 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
), 1,
635 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
637 struct brw_reg index
,
638 struct brw_reg offset
)
640 assert(inst
->mlen
!= 0);
642 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
643 index
.type
== BRW_REGISTER_TYPE_UD
);
644 uint32_t surf_index
= index
.dw1
.ud
;
646 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
647 offset
.type
== BRW_REGISTER_TYPE_UD
);
648 uint32_t read_offset
= offset
.dw1
.ud
;
650 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
651 read_offset
, surf_index
);
655 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
657 struct brw_reg index
,
658 struct brw_reg offset
)
660 assert(inst
->mlen
== 0);
662 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
663 index
.type
== BRW_REGISTER_TYPE_UD
);
664 uint32_t surf_index
= index
.dw1
.ud
;
666 assert(offset
.file
== BRW_GENERAL_REGISTER_FILE
);
667 /* Reference just the dword we need, to avoid angering validate_reg(). */
668 offset
= brw_vec1_grf(offset
.nr
, 0);
670 brw_push_insn_state(p
);
671 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
672 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
673 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
674 brw_pop_insn_state(p
);
676 /* We use the SIMD4x2 mode because we want to end up with 4 components in
677 * the destination loaded consecutively from the same offset (which appears
678 * in the first component, and the rest are ignored).
680 dst
.width
= BRW_WIDTH_4
;
681 brw_set_dest(p
, send
, dst
);
682 brw_set_src0(p
, send
, offset
);
683 brw_set_sampler_message(p
, send
,
685 0, /* LD message ignores sampler unit */
686 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
689 false, /* no header */
690 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
695 fs_generator::generate_varying_pull_constant_load(fs_inst
*inst
,
697 struct brw_reg index
,
698 struct brw_reg offset
)
700 assert(intel
->gen
< 7); /* Should use the gen7 variant. */
701 assert(inst
->header_present
);
704 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
705 index
.type
== BRW_REGISTER_TYPE_UD
);
706 uint32_t surf_index
= index
.dw1
.ud
;
708 uint32_t simd_mode
, rlen
, msg_type
;
709 if (dispatch_width
== 16) {
710 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
713 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
718 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
720 /* We always use the SIMD16 message so that we only have to load U, and
723 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
724 assert(inst
->mlen
== 3);
725 assert(inst
->regs_written
== 8);
727 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
730 struct brw_reg offset_mrf
= retype(brw_message_reg(inst
->base_mrf
+ 1),
731 BRW_REGISTER_TYPE_D
);
732 brw_MOV(p
, offset_mrf
, offset
);
734 struct brw_reg header
= brw_vec8_grf(0, 0);
735 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
737 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
738 send
->header
.compression_control
= BRW_COMPRESSION_NONE
;
739 brw_set_dest(p
, send
, dst
);
740 brw_set_src0(p
, send
, header
);
742 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
744 /* Our surface is set up as floats, regardless of what actual data is
747 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
748 brw_set_sampler_message(p
, send
,
750 0, /* sampler (unused) */
754 inst
->header_present
,
760 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
762 struct brw_reg index
,
763 struct brw_reg offset
)
765 assert(intel
->gen
>= 7);
766 /* Varying-offset pull constant loads are treated as a normal expression on
767 * gen7, so the fact that it's a send message is hidden at the IR level.
769 assert(!inst
->header_present
);
772 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
773 index
.type
== BRW_REGISTER_TYPE_UD
);
774 uint32_t surf_index
= index
.dw1
.ud
;
776 uint32_t simd_mode
, rlen
, mlen
;
777 if (dispatch_width
== 16) {
780 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
784 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
787 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
788 brw_set_dest(p
, send
, dst
);
789 brw_set_src0(p
, send
, offset
);
790 brw_set_sampler_message(p
, send
,
792 0, /* LD message ignores sampler unit */
793 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
796 false, /* no header */
802 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
803 * into the flags register (f0.0).
805 * Used only on Gen6 and above.
808 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
810 struct brw_reg flags
= brw_flag_reg(0, inst
->flag_subreg
);
811 struct brw_reg dispatch_mask
;
814 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
816 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
818 brw_push_insn_state(p
);
819 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
820 brw_MOV(p
, flags
, dispatch_mask
);
821 brw_pop_insn_state(p
);
825 static uint32_t brw_file_from_reg(fs_reg
*reg
)
829 return BRW_ARCHITECTURE_REGISTER_FILE
;
831 return BRW_GENERAL_REGISTER_FILE
;
833 return BRW_MESSAGE_REGISTER_FILE
;
835 return BRW_IMMEDIATE_VALUE
;
837 assert(!"not reached");
838 return BRW_GENERAL_REGISTER_FILE
;
842 static struct brw_reg
843 brw_reg_from_fs_reg(fs_reg
*reg
)
845 struct brw_reg brw_reg
;
851 if (reg
->smear
== -1) {
852 brw_reg
= brw_vec8_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
854 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->reg
, reg
->smear
);
856 brw_reg
= retype(brw_reg
, reg
->type
);
858 brw_reg
= sechalf(brw_reg
);
862 case BRW_REGISTER_TYPE_F
:
863 brw_reg
= brw_imm_f(reg
->imm
.f
);
865 case BRW_REGISTER_TYPE_D
:
866 brw_reg
= brw_imm_d(reg
->imm
.i
);
868 case BRW_REGISTER_TYPE_UD
:
869 brw_reg
= brw_imm_ud(reg
->imm
.u
);
872 assert(!"not reached");
873 brw_reg
= brw_null_reg();
878 brw_reg
= reg
->fixed_hw_reg
;
881 /* Probably unused. */
882 brw_reg
= brw_null_reg();
885 assert(!"not reached");
886 brw_reg
= brw_null_reg();
889 assert(!"not reached");
890 brw_reg
= brw_null_reg();
894 brw_reg
= brw_abs(brw_reg
);
896 brw_reg
= negate(brw_reg
);
902 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
903 * sampler LD messages.
905 * We don't want to bake it into the send message's code generation because
906 * that means we don't get a chance to schedule the instructions.
909 fs_generator::generate_set_simd4x2_offset(fs_inst
*inst
,
911 struct brw_reg value
)
913 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
915 brw_push_insn_state(p
);
916 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
917 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
918 brw_MOV(p
, retype(brw_vec1_reg(dst
.file
, dst
.nr
, 0), value
.type
), value
);
919 brw_pop_insn_state(p
);
923 * Change the register's data type from UD to W, doubling the strides in order
924 * to compensate for halving the data type width.
926 static struct brw_reg
927 ud_reg_to_w(struct brw_reg r
)
929 assert(r
.type
== BRW_REGISTER_TYPE_UD
);
930 r
.type
= BRW_REGISTER_TYPE_W
;
932 /* The BRW_*_STRIDE enums are defined so that incrementing the field
933 * doubles the real stride.
944 fs_generator::generate_pack_half_2x16_split(fs_inst
*inst
,
949 assert(intel
->gen
>= 7);
950 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
951 assert(x
.type
== BRW_REGISTER_TYPE_F
);
952 assert(y
.type
== BRW_REGISTER_TYPE_F
);
954 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
956 * Because this instruction does not have a 16-bit floating-point type,
957 * the destination data type must be Word (W).
959 * The destination must be DWord-aligned and specify a horizontal stride
960 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
961 * each destination channel and the upper word is not modified.
963 struct brw_reg dst_w
= ud_reg_to_w(dst
);
965 /* Give each 32-bit channel of dst the form below , where "." means
969 brw_F32TO16(p
, dst_w
, y
);
974 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
976 /* And, finally the form of packHalf2x16's output:
979 brw_F32TO16(p
, dst_w
, x
);
983 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
987 assert(intel
->gen
>= 7);
988 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
989 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
991 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
993 * Because this instruction does not have a 16-bit floating-point type,
994 * the source data type must be Word (W). The destination type must be
997 struct brw_reg src_w
= ud_reg_to_w(src
);
999 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1000 * For the Y case, we wish to access only the upper word; therefore
1001 * a 16-bit subregister offset is needed.
1003 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1004 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1005 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1008 brw_F16TO32(p
, dst
, src_w
);
1012 fs_generator::generate_shader_time_add(fs_inst
*inst
,
1013 struct brw_reg payload
,
1014 struct brw_reg offset
,
1015 struct brw_reg value
)
1017 assert(intel
->gen
>= 7);
1018 brw_push_insn_state(p
);
1019 brw_set_mask_control(p
, true);
1021 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1022 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1024 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1027 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1028 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1029 value
.width
= BRW_WIDTH_1
;
1030 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1031 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1033 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1036 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1037 * case, and we don't really care about squeezing every bit of performance
1038 * out of this path, so we just emit the MOVs from here.
1040 brw_MOV(p
, payload_offset
, offset
);
1041 brw_MOV(p
, payload_value
, value
);
1042 brw_shader_time_add(p
, payload
, SURF_INDEX_WM_SHADER_TIME
);
1043 brw_pop_insn_state(p
);
1047 fs_generator::generate_code(exec_list
*instructions
)
1049 int last_native_insn_offset
= p
->next_insn_offset
;
1050 const char *last_annotation_string
= NULL
;
1051 const void *last_annotation_ir
= NULL
;
1053 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1055 printf("Native code for fragment shader %d (%d-wide dispatch):\n",
1056 prog
->Name
, dispatch_width
);
1058 printf("Native code for fragment program %d (%d-wide dispatch):\n",
1059 fp
->Base
.Id
, dispatch_width
);
1064 if (unlikely(INTEL_DEBUG
& DEBUG_WM
))
1065 cfg
= new(mem_ctx
) cfg_t(mem_ctx
, instructions
);
1067 foreach_list(node
, instructions
) {
1068 fs_inst
*inst
= (fs_inst
*)node
;
1069 struct brw_reg src
[3], dst
;
1071 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1072 foreach_list(node
, &cfg
->block_list
) {
1073 bblock_link
*link
= (bblock_link
*)node
;
1074 bblock_t
*block
= link
->block
;
1076 if (block
->start
== inst
) {
1077 printf(" START B%d", block
->block_num
);
1078 foreach_list(predecessor_node
, &block
->parents
) {
1079 bblock_link
*predecessor_link
=
1080 (bblock_link
*)predecessor_node
;
1081 bblock_t
*predecessor_block
= predecessor_link
->block
;
1082 printf(" <-B%d", predecessor_block
->block_num
);
1088 if (last_annotation_ir
!= inst
->ir
) {
1089 last_annotation_ir
= inst
->ir
;
1090 if (last_annotation_ir
) {
1093 ((ir_instruction
*)inst
->ir
)->print();
1095 const prog_instruction
*fpi
;
1096 fpi
= (const prog_instruction
*)inst
->ir
;
1097 printf("%d: ", (int)(fpi
- fp
->Base
.Instructions
));
1098 _mesa_fprint_instruction_opt(stdout
,
1100 0, PROG_PRINT_DEBUG
, NULL
);
1105 if (last_annotation_string
!= inst
->annotation
) {
1106 last_annotation_string
= inst
->annotation
;
1107 if (last_annotation_string
)
1108 printf(" %s\n", last_annotation_string
);
1112 for (unsigned int i
= 0; i
< 3; i
++) {
1113 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
1115 /* The accumulator result appears to get used for the
1116 * conditional modifier generation. When negating a UD
1117 * value, there is a 33rd bit generated for the sign in the
1118 * accumulator value, so now you can't check, for example,
1119 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1121 assert(!inst
->conditional_mod
||
1122 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1123 !inst
->src
[i
].negate
);
1125 dst
= brw_reg_from_fs_reg(&inst
->dst
);
1127 brw_set_conditionalmod(p
, inst
->conditional_mod
);
1128 brw_set_predicate_control(p
, inst
->predicate
);
1129 brw_set_predicate_inverse(p
, inst
->predicate_inverse
);
1130 brw_set_flag_reg(p
, 0, inst
->flag_subreg
);
1131 brw_set_saturate(p
, inst
->saturate
);
1132 brw_set_mask_control(p
, inst
->force_writemask_all
);
1134 if (inst
->force_uncompressed
|| dispatch_width
== 8) {
1135 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1136 } else if (inst
->force_sechalf
) {
1137 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1139 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1142 switch (inst
->opcode
) {
1143 case BRW_OPCODE_MOV
:
1144 brw_MOV(p
, dst
, src
[0]);
1146 case BRW_OPCODE_ADD
:
1147 brw_ADD(p
, dst
, src
[0], src
[1]);
1149 case BRW_OPCODE_MUL
:
1150 brw_MUL(p
, dst
, src
[0], src
[1]);
1152 case BRW_OPCODE_MACH
:
1153 brw_set_acc_write_control(p
, 1);
1154 brw_MACH(p
, dst
, src
[0], src
[1]);
1155 brw_set_acc_write_control(p
, 0);
1158 case BRW_OPCODE_MAD
:
1159 brw_set_access_mode(p
, BRW_ALIGN_16
);
1160 if (dispatch_width
== 16) {
1161 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1162 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1163 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1164 brw_MAD(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1165 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1167 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1169 brw_set_access_mode(p
, BRW_ALIGN_1
);
1172 case BRW_OPCODE_LRP
:
1173 brw_set_access_mode(p
, BRW_ALIGN_16
);
1174 if (dispatch_width
== 16) {
1175 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1176 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1177 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1178 brw_LRP(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1179 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1181 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1183 brw_set_access_mode(p
, BRW_ALIGN_1
);
1186 case BRW_OPCODE_FRC
:
1187 brw_FRC(p
, dst
, src
[0]);
1189 case BRW_OPCODE_RNDD
:
1190 brw_RNDD(p
, dst
, src
[0]);
1192 case BRW_OPCODE_RNDE
:
1193 brw_RNDE(p
, dst
, src
[0]);
1195 case BRW_OPCODE_RNDZ
:
1196 brw_RNDZ(p
, dst
, src
[0]);
1199 case BRW_OPCODE_AND
:
1200 brw_AND(p
, dst
, src
[0], src
[1]);
1203 brw_OR(p
, dst
, src
[0], src
[1]);
1205 case BRW_OPCODE_XOR
:
1206 brw_XOR(p
, dst
, src
[0], src
[1]);
1208 case BRW_OPCODE_NOT
:
1209 brw_NOT(p
, dst
, src
[0]);
1211 case BRW_OPCODE_ASR
:
1212 brw_ASR(p
, dst
, src
[0], src
[1]);
1214 case BRW_OPCODE_SHR
:
1215 brw_SHR(p
, dst
, src
[0], src
[1]);
1217 case BRW_OPCODE_SHL
:
1218 brw_SHL(p
, dst
, src
[0], src
[1]);
1220 case BRW_OPCODE_F32TO16
:
1221 brw_F32TO16(p
, dst
, src
[0]);
1223 case BRW_OPCODE_F16TO32
:
1224 brw_F16TO32(p
, dst
, src
[0]);
1226 case BRW_OPCODE_CMP
:
1227 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1229 case BRW_OPCODE_SEL
:
1230 brw_SEL(p
, dst
, src
[0], src
[1]);
1232 case BRW_OPCODE_BFREV
:
1233 /* BFREV only supports UD type for src and dst. */
1234 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1235 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1237 case BRW_OPCODE_FBH
:
1238 /* FBH only supports UD type for dst. */
1239 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1241 case BRW_OPCODE_FBL
:
1242 /* FBL only supports UD type for dst. */
1243 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1245 case BRW_OPCODE_CBIT
:
1246 /* CBIT only supports UD type for dst. */
1247 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1250 case BRW_OPCODE_BFE
:
1251 brw_set_access_mode(p
, BRW_ALIGN_16
);
1252 if (dispatch_width
== 16) {
1253 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1254 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1255 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1256 brw_BFE(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1257 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1259 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1261 brw_set_access_mode(p
, BRW_ALIGN_1
);
1264 case BRW_OPCODE_BFI1
:
1265 brw_BFI1(p
, dst
, src
[0], src
[1]);
1267 case BRW_OPCODE_BFI2
:
1268 brw_set_access_mode(p
, BRW_ALIGN_16
);
1269 if (dispatch_width
== 16) {
1270 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1271 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1272 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1273 brw_BFI2(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1274 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1276 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1278 brw_set_access_mode(p
, BRW_ALIGN_1
);
1282 if (inst
->src
[0].file
!= BAD_FILE
) {
1283 /* The instruction has an embedded compare (only allowed on gen6) */
1284 assert(intel
->gen
== 6);
1285 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1287 brw_IF(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
1291 case BRW_OPCODE_ELSE
:
1294 case BRW_OPCODE_ENDIF
:
1299 brw_DO(p
, BRW_EXECUTE_8
);
1302 case BRW_OPCODE_BREAK
:
1304 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1306 case BRW_OPCODE_CONTINUE
:
1307 /* FINISHME: We need to write the loop instruction support still. */
1308 if (intel
->gen
>= 6)
1312 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1315 case BRW_OPCODE_WHILE
:
1319 case SHADER_OPCODE_RCP
:
1320 case SHADER_OPCODE_RSQ
:
1321 case SHADER_OPCODE_SQRT
:
1322 case SHADER_OPCODE_EXP2
:
1323 case SHADER_OPCODE_LOG2
:
1324 case SHADER_OPCODE_SIN
:
1325 case SHADER_OPCODE_COS
:
1326 if (intel
->gen
>= 7) {
1327 generate_math1_gen7(inst
, dst
, src
[0]);
1328 } else if (intel
->gen
== 6) {
1329 generate_math1_gen6(inst
, dst
, src
[0]);
1330 } else if (intel
->gen
== 5 || intel
->is_g4x
) {
1331 generate_math_g45(inst
, dst
, src
[0]);
1333 generate_math_gen4(inst
, dst
, src
[0]);
1336 case SHADER_OPCODE_INT_QUOTIENT
:
1337 case SHADER_OPCODE_INT_REMAINDER
:
1338 case SHADER_OPCODE_POW
:
1339 if (intel
->gen
>= 7) {
1340 generate_math2_gen7(inst
, dst
, src
[0], src
[1]);
1341 } else if (intel
->gen
== 6) {
1342 generate_math2_gen6(inst
, dst
, src
[0], src
[1]);
1344 generate_math_gen4(inst
, dst
, src
[0]);
1347 case FS_OPCODE_PIXEL_X
:
1348 generate_pixel_xy(dst
, true);
1350 case FS_OPCODE_PIXEL_Y
:
1351 generate_pixel_xy(dst
, false);
1353 case FS_OPCODE_CINTERP
:
1354 brw_MOV(p
, dst
, src
[0]);
1356 case FS_OPCODE_LINTERP
:
1357 generate_linterp(inst
, dst
, src
);
1359 case SHADER_OPCODE_TEX
:
1361 case SHADER_OPCODE_TXD
:
1362 case SHADER_OPCODE_TXF
:
1363 case SHADER_OPCODE_TXF_MS
:
1364 case SHADER_OPCODE_TXL
:
1365 case SHADER_OPCODE_TXS
:
1366 case SHADER_OPCODE_LOD
:
1367 generate_tex(inst
, dst
, src
[0]);
1370 generate_ddx(inst
, dst
, src
[0]);
1373 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1374 * guarantee that c->key.render_to_fbo is set).
1376 assert(fp
->UsesDFdy
);
1377 generate_ddy(inst
, dst
, src
[0], c
->key
.render_to_fbo
);
1380 case FS_OPCODE_SPILL
:
1381 generate_spill(inst
, src
[0]);
1384 case FS_OPCODE_UNSPILL
:
1385 generate_unspill(inst
, dst
);
1388 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1389 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1392 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
1393 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1396 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
1397 generate_varying_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1400 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
1401 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1404 case FS_OPCODE_FB_WRITE
:
1405 generate_fb_write(inst
);
1408 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
1409 generate_mov_dispatch_to_flags(inst
);
1412 case FS_OPCODE_DISCARD_JUMP
:
1413 generate_discard_jump(inst
);
1416 case SHADER_OPCODE_SHADER_TIME_ADD
:
1417 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
1420 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
1421 generate_set_simd4x2_offset(inst
, dst
, src
[0]);
1424 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
1425 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
1428 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
1429 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
1430 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
1433 case FS_OPCODE_PLACEHOLDER_HALT
:
1434 /* This is the place where the final HALT needs to be inserted if
1435 * we've emitted any discards. If not, this will emit no code.
1437 patch_discard_jumps_to_fb_writes();
1441 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
1442 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
1443 opcode_descs
[inst
->opcode
].name
);
1445 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
1450 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1451 brw_dump_compile(p
, stdout
,
1452 last_native_insn_offset
, p
->next_insn_offset
);
1454 foreach_list(node
, &cfg
->block_list
) {
1455 bblock_link
*link
= (bblock_link
*)node
;
1456 bblock_t
*block
= link
->block
;
1458 if (block
->end
== inst
) {
1459 printf(" END B%d", block
->block_num
);
1460 foreach_list(successor_node
, &block
->children
) {
1461 bblock_link
*successor_link
=
1462 (bblock_link
*)successor_node
;
1463 bblock_t
*successor_block
= successor_link
->block
;
1464 printf(" ->B%d", successor_block
->block_num
);
1471 last_native_insn_offset
= p
->next_insn_offset
;
1474 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1480 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
1481 * emit issues, it doesn't get the jump distances into the output,
1482 * which is often something we want to debug. So this is here in
1483 * case you're doing that.
1486 brw_dump_compile(p
, stdout
, 0, p
->next_insn_offset
);
1491 fs_generator::generate_assembly(exec_list
*simd8_instructions
,
1492 exec_list
*simd16_instructions
,
1493 unsigned *assembly_size
)
1496 generate_code(simd8_instructions
);
1498 if (simd16_instructions
) {
1499 /* We have to do a compaction pass now, or the one at the end of
1500 * execution will squash down where our prog_offset start needs
1503 brw_compact_instructions(p
);
1505 /* align to 64 byte boundary. */
1506 while ((p
->nr_insn
* sizeof(struct brw_instruction
)) % 64) {
1510 /* Save off the start of this 16-wide program */
1511 c
->prog_data
.prog_offset_16
= p
->nr_insn
* sizeof(struct brw_instruction
);
1513 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1515 dispatch_width
= 16;
1516 generate_code(simd16_instructions
);
1519 return brw_get_program(p
, assembly_size
);