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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_emit.cpp
26 * This file supports emitting code from the FS LIR to the actual
27 * native instructions.
31 #include "main/macros.h"
32 #include "brw_context.h"
39 fs_generator::fs_generator(struct brw_context
*brw
,
40 struct brw_wm_compile
*c
,
41 struct gl_shader_program
*prog
,
42 struct gl_fragment_program
*fp
,
43 bool dual_source_output
)
45 : brw(brw
), c(c
), prog(prog
), fp(fp
), dual_source_output(dual_source_output
)
49 shader
= prog
? prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
] : NULL
;
53 p
= rzalloc(mem_ctx
, struct brw_compile
);
54 brw_init_compile(brw
, p
, mem_ctx
);
57 fs_generator::~fs_generator()
62 fs_generator::mark_surface_used(unsigned surf_index
)
64 assert(surf_index
< BRW_MAX_WM_SURFACES
);
66 c
->prog_data
.binding_table_size
=
67 MAX2(c
->prog_data
.binding_table_size
, surf_index
+ 1);
71 fs_generator::patch_discard_jumps_to_fb_writes()
73 if (brw
->gen
< 6 || this->discard_halt_patches
.is_empty())
76 /* There is a somewhat strange undocumented requirement of using
77 * HALT, according to the simulator. If some channel has HALTed to
78 * a particular UIP, then by the end of the program, every channel
79 * must have HALTed to that UIP. Furthermore, the tracking is a
80 * stack, so you can't do the final halt of a UIP after starting
81 * halting to a new UIP.
83 * Symptoms of not emitting this instruction on actual hardware
84 * included GPU hangs and sparkly rendering on the piglit discard
87 struct brw_instruction
*last_halt
= gen6_HALT(p
);
88 last_halt
->bits3
.break_cont
.uip
= 2;
89 last_halt
->bits3
.break_cont
.jip
= 2;
93 foreach_list(node
, &this->discard_halt_patches
) {
94 ip_record
*patch_ip
= (ip_record
*)node
;
95 struct brw_instruction
*patch
= &p
->store
[patch_ip
->ip
];
97 assert(patch
->header
.opcode
== BRW_OPCODE_HALT
);
98 /* HALT takes a half-instruction distance from the pre-incremented IP. */
99 patch
->bits3
.break_cont
.uip
= (ip
- patch_ip
->ip
) * 2;
102 this->discard_halt_patches
.make_empty();
106 fs_generator::generate_fb_write(fs_inst
*inst
)
108 bool eot
= inst
->eot
;
109 struct brw_reg implied_header
;
110 uint32_t msg_control
;
112 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
115 brw_push_insn_state(p
);
116 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
117 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
120 struct brw_reg pixel_mask
;
123 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
125 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
127 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
130 if (inst
->header_present
) {
132 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
134 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
),
135 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
136 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
138 if (inst
->target
> 0 && c
->key
.replicate_alpha
) {
139 /* Set "Source0 Alpha Present to RenderTarget" bit in message
143 vec1(retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
)),
144 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
145 brw_imm_ud(0x1 << 11));
148 if (inst
->target
> 0) {
149 /* Set the render target index for choosing BLEND_STATE. */
150 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
,
152 BRW_REGISTER_TYPE_UD
),
153 brw_imm_ud(inst
->target
));
156 implied_header
= brw_null_reg();
158 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
161 brw_message_reg(inst
->base_mrf
+ 1),
165 implied_header
= brw_null_reg();
168 if (this->dual_source_output
)
169 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
170 else if (dispatch_width
== 16)
171 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
173 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
175 brw_pop_insn_state(p
);
182 SURF_INDEX_DRAW(inst
->target
),
186 inst
->header_present
);
188 mark_surface_used(SURF_INDEX_DRAW(inst
->target
));
191 /* Computes the integer pixel x,y values from the origin.
193 * This is the basis of gl_FragCoord computation, but is also used
194 * pre-gen6 for computing the deltas from v0 for computing
198 fs_generator::generate_pixel_xy(struct brw_reg dst
, bool is_x
)
200 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
202 struct brw_reg deltas
;
205 src
= stride(suboffset(g1_uw
, 4), 2, 4, 0);
206 deltas
= brw_imm_v(0x10101010);
208 src
= stride(suboffset(g1_uw
, 5), 2, 4, 0);
209 deltas
= brw_imm_v(0x11001100);
212 if (dispatch_width
== 16) {
216 /* We do this 8 or 16-wide, but since the destination is UW we
217 * don't do compression in the 16-wide case.
219 brw_push_insn_state(p
);
220 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
221 brw_ADD(p
, dst
, src
, deltas
);
222 brw_pop_insn_state(p
);
226 fs_generator::generate_linterp(fs_inst
*inst
,
227 struct brw_reg dst
, struct brw_reg
*src
)
229 struct brw_reg delta_x
= src
[0];
230 struct brw_reg delta_y
= src
[1];
231 struct brw_reg interp
= src
[2];
234 delta_y
.nr
== delta_x
.nr
+ 1 &&
235 (brw
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
236 brw_PLN(p
, dst
, interp
, delta_x
);
238 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
239 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
244 fs_generator::generate_math1_gen7(fs_inst
*inst
,
248 assert(inst
->mlen
== 0);
250 brw_math_function(inst
->opcode
),
252 BRW_MATH_DATA_VECTOR
,
253 BRW_MATH_PRECISION_FULL
);
257 fs_generator::generate_math2_gen7(fs_inst
*inst
,
262 assert(inst
->mlen
== 0);
263 brw_math2(p
, dst
, brw_math_function(inst
->opcode
), src0
, src1
);
267 fs_generator::generate_math1_gen6(fs_inst
*inst
,
271 int op
= brw_math_function(inst
->opcode
);
273 assert(inst
->mlen
== 0);
275 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
279 BRW_MATH_DATA_VECTOR
,
280 BRW_MATH_PRECISION_FULL
);
282 if (dispatch_width
== 16) {
283 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
284 brw_math(p
, sechalf(dst
),
287 BRW_MATH_DATA_VECTOR
,
288 BRW_MATH_PRECISION_FULL
);
289 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
294 fs_generator::generate_math2_gen6(fs_inst
*inst
,
299 int op
= brw_math_function(inst
->opcode
);
301 assert(inst
->mlen
== 0);
303 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
304 brw_math2(p
, dst
, op
, src0
, src1
);
306 if (dispatch_width
== 16) {
307 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
308 brw_math2(p
, sechalf(dst
), op
, sechalf(src0
), sechalf(src1
));
309 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
314 fs_generator::generate_math_gen4(fs_inst
*inst
,
318 int op
= brw_math_function(inst
->opcode
);
320 assert(inst
->mlen
>= 1);
322 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
326 BRW_MATH_DATA_VECTOR
,
327 BRW_MATH_PRECISION_FULL
);
329 if (dispatch_width
== 16) {
330 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
331 brw_math(p
, sechalf(dst
),
333 inst
->base_mrf
+ 1, sechalf(src
),
334 BRW_MATH_DATA_VECTOR
,
335 BRW_MATH_PRECISION_FULL
);
337 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
342 fs_generator::generate_math_g45(fs_inst
*inst
,
346 if (inst
->opcode
== SHADER_OPCODE_POW
||
347 inst
->opcode
== SHADER_OPCODE_INT_QUOTIENT
||
348 inst
->opcode
== SHADER_OPCODE_INT_REMAINDER
) {
349 generate_math_gen4(inst
, dst
, src
);
353 int op
= brw_math_function(inst
->opcode
);
355 assert(inst
->mlen
>= 1);
360 BRW_MATH_DATA_VECTOR
,
361 BRW_MATH_PRECISION_FULL
);
365 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
369 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
370 uint32_t return_format
;
373 case BRW_REGISTER_TYPE_D
:
374 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
376 case BRW_REGISTER_TYPE_UD
:
377 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
380 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
384 if (dispatch_width
== 16)
385 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
388 switch (inst
->opcode
) {
389 case SHADER_OPCODE_TEX
:
390 if (inst
->shadow_compare
) {
391 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
393 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
397 if (inst
->shadow_compare
) {
398 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
400 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
403 case SHADER_OPCODE_TXL
:
404 if (inst
->shadow_compare
) {
405 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
407 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
410 case SHADER_OPCODE_TXS
:
411 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
413 case SHADER_OPCODE_TXD
:
414 if (inst
->shadow_compare
) {
415 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
416 assert(brw
->is_haswell
);
417 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
419 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
422 case SHADER_OPCODE_TXF
:
423 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
425 case SHADER_OPCODE_TXF_MS
:
427 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
429 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
431 case SHADER_OPCODE_LOD
:
432 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
435 assert(!"not reached");
439 switch (inst
->opcode
) {
440 case SHADER_OPCODE_TEX
:
441 /* Note that G45 and older determines shadow compare and dispatch width
442 * from message length for most messages.
444 assert(dispatch_width
== 8);
445 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
446 if (inst
->shadow_compare
) {
447 assert(inst
->mlen
== 6);
449 assert(inst
->mlen
<= 4);
453 if (inst
->shadow_compare
) {
454 assert(inst
->mlen
== 6);
455 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
457 assert(inst
->mlen
== 9);
458 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
459 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
462 case SHADER_OPCODE_TXL
:
463 if (inst
->shadow_compare
) {
464 assert(inst
->mlen
== 6);
465 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
467 assert(inst
->mlen
== 9);
468 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
469 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
472 case SHADER_OPCODE_TXD
:
473 /* There is no sample_d_c message; comparisons are done manually */
474 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
475 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
477 case SHADER_OPCODE_TXF
:
478 assert(inst
->mlen
== 9);
479 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
480 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
482 case SHADER_OPCODE_TXS
:
483 assert(inst
->mlen
== 3);
484 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
485 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
488 assert(!"not reached");
492 assert(msg_type
!= -1);
494 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
499 /* Load the message header if present. If there's a texture offset,
500 * we need to set it up explicitly and load the offset bitfield.
501 * Otherwise, we can use an implied move from g0 to the first message reg.
503 if (inst
->texture_offset
) {
504 brw_push_insn_state(p
);
505 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
506 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
507 /* Explicitly set up the message header by copying g0 to the MRF. */
508 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
),
509 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
511 /* Then set the offset bits in DWord 2. */
512 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
,
513 inst
->base_mrf
, 2), BRW_REGISTER_TYPE_UD
),
514 brw_imm_ud(inst
->texture_offset
));
515 brw_pop_insn_state(p
);
516 } else if (inst
->header_present
) {
517 /* Set up an implied move from g0 to the MRF. */
518 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
522 retype(dst
, BRW_REGISTER_TYPE_UW
),
525 SURF_INDEX_TEXTURE(inst
->sampler
),
530 inst
->header_present
,
534 mark_surface_used(SURF_INDEX_TEXTURE(inst
->sampler
));
538 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
541 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
543 * and we're trying to produce:
546 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
547 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
548 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
549 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
550 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
551 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
552 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
553 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
555 * and add another set of two more subspans if in 16-pixel dispatch mode.
557 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
558 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
559 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
560 * between each other. We could probably do it like ddx and swizzle the right
561 * order later, but bail for now and just produce
562 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
565 fs_generator::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
567 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
569 BRW_VERTICAL_STRIDE_2
,
571 BRW_HORIZONTAL_STRIDE_0
,
572 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
573 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
575 BRW_VERTICAL_STRIDE_2
,
577 BRW_HORIZONTAL_STRIDE_0
,
578 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
579 brw_ADD(p
, dst
, src0
, negate(src1
));
582 /* The negate_value boolean is used to negate the derivative computation for
583 * FBOs, since they place the origin at the upper left instead of the lower
587 fs_generator::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
590 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
592 BRW_VERTICAL_STRIDE_4
,
594 BRW_HORIZONTAL_STRIDE_0
,
595 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
596 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
598 BRW_VERTICAL_STRIDE_4
,
600 BRW_HORIZONTAL_STRIDE_0
,
601 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
603 brw_ADD(p
, dst
, src1
, negate(src0
));
605 brw_ADD(p
, dst
, src0
, negate(src1
));
609 fs_generator::generate_discard_jump(fs_inst
*inst
)
611 assert(brw
->gen
>= 6);
613 /* This HALT will be patched up at FB write time to point UIP at the end of
614 * the program, and at brw_uip_jip() JIP will be set to the end of the
615 * current block (or the program).
617 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
619 brw_push_insn_state(p
);
620 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
622 brw_pop_insn_state(p
);
626 fs_generator::generate_spill(fs_inst
*inst
, struct brw_reg src
)
628 assert(inst
->mlen
!= 0);
631 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
632 retype(src
, BRW_REGISTER_TYPE_UD
));
633 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
), 1,
638 fs_generator::generate_unspill(fs_inst
*inst
, struct brw_reg dst
)
640 assert(inst
->mlen
!= 0);
642 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
), 1,
647 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
649 struct brw_reg index
,
650 struct brw_reg offset
)
652 assert(inst
->mlen
!= 0);
654 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
655 index
.type
== BRW_REGISTER_TYPE_UD
);
656 uint32_t surf_index
= index
.dw1
.ud
;
658 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
659 offset
.type
== BRW_REGISTER_TYPE_UD
);
660 uint32_t read_offset
= offset
.dw1
.ud
;
662 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
663 read_offset
, surf_index
);
665 mark_surface_used(surf_index
);
669 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
671 struct brw_reg index
,
672 struct brw_reg offset
)
674 assert(inst
->mlen
== 0);
676 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
677 index
.type
== BRW_REGISTER_TYPE_UD
);
678 uint32_t surf_index
= index
.dw1
.ud
;
680 assert(offset
.file
== BRW_GENERAL_REGISTER_FILE
);
681 /* Reference just the dword we need, to avoid angering validate_reg(). */
682 offset
= brw_vec1_grf(offset
.nr
, 0);
684 brw_push_insn_state(p
);
685 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
686 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
687 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
688 brw_pop_insn_state(p
);
690 /* We use the SIMD4x2 mode because we want to end up with 4 components in
691 * the destination loaded consecutively from the same offset (which appears
692 * in the first component, and the rest are ignored).
694 dst
.width
= BRW_WIDTH_4
;
695 brw_set_dest(p
, send
, dst
);
696 brw_set_src0(p
, send
, offset
);
697 brw_set_sampler_message(p
, send
,
699 0, /* LD message ignores sampler unit */
700 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
703 false, /* no header */
704 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
707 mark_surface_used(surf_index
);
711 fs_generator::generate_varying_pull_constant_load(fs_inst
*inst
,
713 struct brw_reg index
,
714 struct brw_reg offset
)
716 assert(brw
->gen
< 7); /* Should use the gen7 variant. */
717 assert(inst
->header_present
);
720 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
721 index
.type
== BRW_REGISTER_TYPE_UD
);
722 uint32_t surf_index
= index
.dw1
.ud
;
724 uint32_t simd_mode
, rlen
, msg_type
;
725 if (dispatch_width
== 16) {
726 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
729 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
734 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
736 /* We always use the SIMD16 message so that we only have to load U, and
739 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
740 assert(inst
->mlen
== 3);
741 assert(inst
->regs_written
== 8);
743 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
746 struct brw_reg offset_mrf
= retype(brw_message_reg(inst
->base_mrf
+ 1),
747 BRW_REGISTER_TYPE_D
);
748 brw_MOV(p
, offset_mrf
, offset
);
750 struct brw_reg header
= brw_vec8_grf(0, 0);
751 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
753 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
754 send
->header
.compression_control
= BRW_COMPRESSION_NONE
;
755 brw_set_dest(p
, send
, dst
);
756 brw_set_src0(p
, send
, header
);
758 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
760 /* Our surface is set up as floats, regardless of what actual data is
763 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
764 brw_set_sampler_message(p
, send
,
766 0, /* sampler (unused) */
770 inst
->header_present
,
774 mark_surface_used(surf_index
);
778 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
780 struct brw_reg index
,
781 struct brw_reg offset
)
783 assert(brw
->gen
>= 7);
784 /* Varying-offset pull constant loads are treated as a normal expression on
785 * gen7, so the fact that it's a send message is hidden at the IR level.
787 assert(!inst
->header_present
);
790 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
791 index
.type
== BRW_REGISTER_TYPE_UD
);
792 uint32_t surf_index
= index
.dw1
.ud
;
794 uint32_t simd_mode
, rlen
, mlen
;
795 if (dispatch_width
== 16) {
798 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
802 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
805 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
806 brw_set_dest(p
, send
, dst
);
807 brw_set_src0(p
, send
, offset
);
808 brw_set_sampler_message(p
, send
,
810 0, /* LD message ignores sampler unit */
811 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
814 false, /* no header */
818 mark_surface_used(surf_index
);
822 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
823 * into the flags register (f0.0).
825 * Used only on Gen6 and above.
828 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
830 struct brw_reg flags
= brw_flag_reg(0, inst
->flag_subreg
);
831 struct brw_reg dispatch_mask
;
834 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
836 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
838 brw_push_insn_state(p
);
839 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
840 brw_MOV(p
, flags
, dispatch_mask
);
841 brw_pop_insn_state(p
);
845 static uint32_t brw_file_from_reg(fs_reg
*reg
)
849 return BRW_ARCHITECTURE_REGISTER_FILE
;
851 return BRW_GENERAL_REGISTER_FILE
;
853 return BRW_MESSAGE_REGISTER_FILE
;
855 return BRW_IMMEDIATE_VALUE
;
857 assert(!"not reached");
858 return BRW_GENERAL_REGISTER_FILE
;
862 static struct brw_reg
863 brw_reg_from_fs_reg(fs_reg
*reg
)
865 struct brw_reg brw_reg
;
871 if (reg
->smear
== -1) {
872 brw_reg
= brw_vec8_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
874 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->reg
, reg
->smear
);
876 brw_reg
= retype(brw_reg
, reg
->type
);
878 brw_reg
= sechalf(brw_reg
);
882 case BRW_REGISTER_TYPE_F
:
883 brw_reg
= brw_imm_f(reg
->imm
.f
);
885 case BRW_REGISTER_TYPE_D
:
886 brw_reg
= brw_imm_d(reg
->imm
.i
);
888 case BRW_REGISTER_TYPE_UD
:
889 brw_reg
= brw_imm_ud(reg
->imm
.u
);
892 assert(!"not reached");
893 brw_reg
= brw_null_reg();
898 brw_reg
= reg
->fixed_hw_reg
;
901 /* Probably unused. */
902 brw_reg
= brw_null_reg();
905 assert(!"not reached");
906 brw_reg
= brw_null_reg();
909 assert(!"not reached");
910 brw_reg
= brw_null_reg();
914 brw_reg
= brw_abs(brw_reg
);
916 brw_reg
= negate(brw_reg
);
922 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
923 * sampler LD messages.
925 * We don't want to bake it into the send message's code generation because
926 * that means we don't get a chance to schedule the instructions.
929 fs_generator::generate_set_simd4x2_offset(fs_inst
*inst
,
931 struct brw_reg value
)
933 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
935 brw_push_insn_state(p
);
936 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
937 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
938 brw_MOV(p
, retype(brw_vec1_reg(dst
.file
, dst
.nr
, 0), value
.type
), value
);
939 brw_pop_insn_state(p
);
943 * Change the register's data type from UD to W, doubling the strides in order
944 * to compensate for halving the data type width.
946 static struct brw_reg
947 ud_reg_to_w(struct brw_reg r
)
949 assert(r
.type
== BRW_REGISTER_TYPE_UD
);
950 r
.type
= BRW_REGISTER_TYPE_W
;
952 /* The BRW_*_STRIDE enums are defined so that incrementing the field
953 * doubles the real stride.
964 fs_generator::generate_pack_half_2x16_split(fs_inst
*inst
,
969 assert(brw
->gen
>= 7);
970 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
971 assert(x
.type
== BRW_REGISTER_TYPE_F
);
972 assert(y
.type
== BRW_REGISTER_TYPE_F
);
974 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
976 * Because this instruction does not have a 16-bit floating-point type,
977 * the destination data type must be Word (W).
979 * The destination must be DWord-aligned and specify a horizontal stride
980 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
981 * each destination channel and the upper word is not modified.
983 struct brw_reg dst_w
= ud_reg_to_w(dst
);
985 /* Give each 32-bit channel of dst the form below , where "." means
989 brw_F32TO16(p
, dst_w
, y
);
994 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
996 /* And, finally the form of packHalf2x16's output:
999 brw_F32TO16(p
, dst_w
, x
);
1003 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
1007 assert(brw
->gen
>= 7);
1008 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1009 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1011 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1013 * Because this instruction does not have a 16-bit floating-point type,
1014 * the source data type must be Word (W). The destination type must be
1017 struct brw_reg src_w
= ud_reg_to_w(src
);
1019 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1020 * For the Y case, we wish to access only the upper word; therefore
1021 * a 16-bit subregister offset is needed.
1023 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1024 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1025 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1028 brw_F16TO32(p
, dst
, src_w
);
1032 fs_generator::generate_shader_time_add(fs_inst
*inst
,
1033 struct brw_reg payload
,
1034 struct brw_reg offset
,
1035 struct brw_reg value
)
1037 assert(brw
->gen
>= 7);
1038 brw_push_insn_state(p
);
1039 brw_set_mask_control(p
, true);
1041 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1042 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1044 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1047 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1048 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1049 value
.width
= BRW_WIDTH_1
;
1050 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1051 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1053 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1056 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1057 * case, and we don't really care about squeezing every bit of performance
1058 * out of this path, so we just emit the MOVs from here.
1060 brw_MOV(p
, payload_offset
, offset
);
1061 brw_MOV(p
, payload_value
, value
);
1062 brw_shader_time_add(p
, payload
, SURF_INDEX_WM_SHADER_TIME
);
1063 brw_pop_insn_state(p
);
1065 mark_surface_used(SURF_INDEX_WM_SHADER_TIME
);
1069 fs_generator::generate_code(exec_list
*instructions
)
1071 int last_native_insn_offset
= p
->next_insn_offset
;
1072 const char *last_annotation_string
= NULL
;
1073 const void *last_annotation_ir
= NULL
;
1075 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1077 printf("Native code for fragment shader %d (%d-wide dispatch):\n",
1078 prog
->Name
, dispatch_width
);
1080 printf("Native code for fragment program %d (%d-wide dispatch):\n",
1081 fp
->Base
.Id
, dispatch_width
);
1086 if (unlikely(INTEL_DEBUG
& DEBUG_WM
))
1087 cfg
= new(mem_ctx
) cfg_t(mem_ctx
, instructions
);
1089 foreach_list(node
, instructions
) {
1090 fs_inst
*inst
= (fs_inst
*)node
;
1091 struct brw_reg src
[3], dst
;
1093 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1094 foreach_list(node
, &cfg
->block_list
) {
1095 bblock_link
*link
= (bblock_link
*)node
;
1096 bblock_t
*block
= link
->block
;
1098 if (block
->start
== inst
) {
1099 printf(" START B%d", block
->block_num
);
1100 foreach_list(predecessor_node
, &block
->parents
) {
1101 bblock_link
*predecessor_link
=
1102 (bblock_link
*)predecessor_node
;
1103 bblock_t
*predecessor_block
= predecessor_link
->block
;
1104 printf(" <-B%d", predecessor_block
->block_num
);
1110 if (last_annotation_ir
!= inst
->ir
) {
1111 last_annotation_ir
= inst
->ir
;
1112 if (last_annotation_ir
) {
1115 ((ir_instruction
*)inst
->ir
)->print();
1117 const prog_instruction
*fpi
;
1118 fpi
= (const prog_instruction
*)inst
->ir
;
1119 printf("%d: ", (int)(fpi
- fp
->Base
.Instructions
));
1120 _mesa_fprint_instruction_opt(stdout
,
1122 0, PROG_PRINT_DEBUG
, NULL
);
1127 if (last_annotation_string
!= inst
->annotation
) {
1128 last_annotation_string
= inst
->annotation
;
1129 if (last_annotation_string
)
1130 printf(" %s\n", last_annotation_string
);
1134 for (unsigned int i
= 0; i
< 3; i
++) {
1135 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
1137 /* The accumulator result appears to get used for the
1138 * conditional modifier generation. When negating a UD
1139 * value, there is a 33rd bit generated for the sign in the
1140 * accumulator value, so now you can't check, for example,
1141 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1143 assert(!inst
->conditional_mod
||
1144 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1145 !inst
->src
[i
].negate
);
1147 dst
= brw_reg_from_fs_reg(&inst
->dst
);
1149 brw_set_conditionalmod(p
, inst
->conditional_mod
);
1150 brw_set_predicate_control(p
, inst
->predicate
);
1151 brw_set_predicate_inverse(p
, inst
->predicate_inverse
);
1152 brw_set_flag_reg(p
, 0, inst
->flag_subreg
);
1153 brw_set_saturate(p
, inst
->saturate
);
1154 brw_set_mask_control(p
, inst
->force_writemask_all
);
1156 if (inst
->force_uncompressed
|| dispatch_width
== 8) {
1157 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1158 } else if (inst
->force_sechalf
) {
1159 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1161 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1164 switch (inst
->opcode
) {
1165 case BRW_OPCODE_MOV
:
1166 brw_MOV(p
, dst
, src
[0]);
1168 case BRW_OPCODE_ADD
:
1169 brw_ADD(p
, dst
, src
[0], src
[1]);
1171 case BRW_OPCODE_MUL
:
1172 brw_MUL(p
, dst
, src
[0], src
[1]);
1174 case BRW_OPCODE_MACH
:
1175 brw_set_acc_write_control(p
, 1);
1176 brw_MACH(p
, dst
, src
[0], src
[1]);
1177 brw_set_acc_write_control(p
, 0);
1180 case BRW_OPCODE_MAD
:
1181 brw_set_access_mode(p
, BRW_ALIGN_16
);
1182 if (dispatch_width
== 16) {
1183 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1184 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1185 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1186 brw_MAD(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1187 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1189 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1191 brw_set_access_mode(p
, BRW_ALIGN_1
);
1194 case BRW_OPCODE_LRP
:
1195 brw_set_access_mode(p
, BRW_ALIGN_16
);
1196 if (dispatch_width
== 16) {
1197 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1198 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1199 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1200 brw_LRP(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1201 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1203 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1205 brw_set_access_mode(p
, BRW_ALIGN_1
);
1208 case BRW_OPCODE_FRC
:
1209 brw_FRC(p
, dst
, src
[0]);
1211 case BRW_OPCODE_RNDD
:
1212 brw_RNDD(p
, dst
, src
[0]);
1214 case BRW_OPCODE_RNDE
:
1215 brw_RNDE(p
, dst
, src
[0]);
1217 case BRW_OPCODE_RNDZ
:
1218 brw_RNDZ(p
, dst
, src
[0]);
1221 case BRW_OPCODE_AND
:
1222 brw_AND(p
, dst
, src
[0], src
[1]);
1225 brw_OR(p
, dst
, src
[0], src
[1]);
1227 case BRW_OPCODE_XOR
:
1228 brw_XOR(p
, dst
, src
[0], src
[1]);
1230 case BRW_OPCODE_NOT
:
1231 brw_NOT(p
, dst
, src
[0]);
1233 case BRW_OPCODE_ASR
:
1234 brw_ASR(p
, dst
, src
[0], src
[1]);
1236 case BRW_OPCODE_SHR
:
1237 brw_SHR(p
, dst
, src
[0], src
[1]);
1239 case BRW_OPCODE_SHL
:
1240 brw_SHL(p
, dst
, src
[0], src
[1]);
1242 case BRW_OPCODE_F32TO16
:
1243 brw_F32TO16(p
, dst
, src
[0]);
1245 case BRW_OPCODE_F16TO32
:
1246 brw_F16TO32(p
, dst
, src
[0]);
1248 case BRW_OPCODE_CMP
:
1249 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1251 case BRW_OPCODE_SEL
:
1252 brw_SEL(p
, dst
, src
[0], src
[1]);
1254 case BRW_OPCODE_BFREV
:
1255 /* BFREV only supports UD type for src and dst. */
1256 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1257 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1259 case BRW_OPCODE_FBH
:
1260 /* FBH only supports UD type for dst. */
1261 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1263 case BRW_OPCODE_FBL
:
1264 /* FBL only supports UD type for dst. */
1265 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1267 case BRW_OPCODE_CBIT
:
1268 /* CBIT only supports UD type for dst. */
1269 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1272 case BRW_OPCODE_BFE
:
1273 brw_set_access_mode(p
, BRW_ALIGN_16
);
1274 if (dispatch_width
== 16) {
1275 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1276 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1277 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1278 brw_BFE(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1279 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1281 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1283 brw_set_access_mode(p
, BRW_ALIGN_1
);
1286 case BRW_OPCODE_BFI1
:
1287 brw_BFI1(p
, dst
, src
[0], src
[1]);
1289 case BRW_OPCODE_BFI2
:
1290 brw_set_access_mode(p
, BRW_ALIGN_16
);
1291 if (dispatch_width
== 16) {
1292 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1293 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1294 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1295 brw_BFI2(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1296 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1298 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1300 brw_set_access_mode(p
, BRW_ALIGN_1
);
1304 if (inst
->src
[0].file
!= BAD_FILE
) {
1305 /* The instruction has an embedded compare (only allowed on gen6) */
1306 assert(brw
->gen
== 6);
1307 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1309 brw_IF(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
1313 case BRW_OPCODE_ELSE
:
1316 case BRW_OPCODE_ENDIF
:
1321 brw_DO(p
, BRW_EXECUTE_8
);
1324 case BRW_OPCODE_BREAK
:
1326 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1328 case BRW_OPCODE_CONTINUE
:
1329 /* FINISHME: We need to write the loop instruction support still. */
1334 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1337 case BRW_OPCODE_WHILE
:
1341 case SHADER_OPCODE_RCP
:
1342 case SHADER_OPCODE_RSQ
:
1343 case SHADER_OPCODE_SQRT
:
1344 case SHADER_OPCODE_EXP2
:
1345 case SHADER_OPCODE_LOG2
:
1346 case SHADER_OPCODE_SIN
:
1347 case SHADER_OPCODE_COS
:
1348 if (brw
->gen
>= 7) {
1349 generate_math1_gen7(inst
, dst
, src
[0]);
1350 } else if (brw
->gen
== 6) {
1351 generate_math1_gen6(inst
, dst
, src
[0]);
1352 } else if (brw
->gen
== 5 || brw
->is_g4x
) {
1353 generate_math_g45(inst
, dst
, src
[0]);
1355 generate_math_gen4(inst
, dst
, src
[0]);
1358 case SHADER_OPCODE_INT_QUOTIENT
:
1359 case SHADER_OPCODE_INT_REMAINDER
:
1360 case SHADER_OPCODE_POW
:
1361 if (brw
->gen
>= 7) {
1362 generate_math2_gen7(inst
, dst
, src
[0], src
[1]);
1363 } else if (brw
->gen
== 6) {
1364 generate_math2_gen6(inst
, dst
, src
[0], src
[1]);
1366 generate_math_gen4(inst
, dst
, src
[0]);
1369 case FS_OPCODE_PIXEL_X
:
1370 generate_pixel_xy(dst
, true);
1372 case FS_OPCODE_PIXEL_Y
:
1373 generate_pixel_xy(dst
, false);
1375 case FS_OPCODE_CINTERP
:
1376 brw_MOV(p
, dst
, src
[0]);
1378 case FS_OPCODE_LINTERP
:
1379 generate_linterp(inst
, dst
, src
);
1381 case SHADER_OPCODE_TEX
:
1383 case SHADER_OPCODE_TXD
:
1384 case SHADER_OPCODE_TXF
:
1385 case SHADER_OPCODE_TXF_MS
:
1386 case SHADER_OPCODE_TXL
:
1387 case SHADER_OPCODE_TXS
:
1388 case SHADER_OPCODE_LOD
:
1389 generate_tex(inst
, dst
, src
[0]);
1392 generate_ddx(inst
, dst
, src
[0]);
1395 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1396 * guarantee that c->key.render_to_fbo is set).
1398 assert(fp
->UsesDFdy
);
1399 generate_ddy(inst
, dst
, src
[0], c
->key
.render_to_fbo
);
1402 case FS_OPCODE_SPILL
:
1403 generate_spill(inst
, src
[0]);
1406 case FS_OPCODE_UNSPILL
:
1407 generate_unspill(inst
, dst
);
1410 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1411 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1414 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
1415 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1418 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
1419 generate_varying_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1422 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
1423 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1426 case FS_OPCODE_FB_WRITE
:
1427 generate_fb_write(inst
);
1430 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
1431 generate_mov_dispatch_to_flags(inst
);
1434 case FS_OPCODE_DISCARD_JUMP
:
1435 generate_discard_jump(inst
);
1438 case SHADER_OPCODE_SHADER_TIME_ADD
:
1439 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
1442 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
1443 generate_set_simd4x2_offset(inst
, dst
, src
[0]);
1446 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
1447 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
1450 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
1451 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
1452 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
1455 case FS_OPCODE_PLACEHOLDER_HALT
:
1456 /* This is the place where the final HALT needs to be inserted if
1457 * we've emitted any discards. If not, this will emit no code.
1459 patch_discard_jumps_to_fb_writes();
1463 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
1464 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
1465 opcode_descs
[inst
->opcode
].name
);
1467 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
1472 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1473 brw_dump_compile(p
, stdout
,
1474 last_native_insn_offset
, p
->next_insn_offset
);
1476 foreach_list(node
, &cfg
->block_list
) {
1477 bblock_link
*link
= (bblock_link
*)node
;
1478 bblock_t
*block
= link
->block
;
1480 if (block
->end
== inst
) {
1481 printf(" END B%d", block
->block_num
);
1482 foreach_list(successor_node
, &block
->children
) {
1483 bblock_link
*successor_link
=
1484 (bblock_link
*)successor_node
;
1485 bblock_t
*successor_block
= successor_link
->block
;
1486 printf(" ->B%d", successor_block
->block_num
);
1493 last_native_insn_offset
= p
->next_insn_offset
;
1496 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1502 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
1503 * emit issues, it doesn't get the jump distances into the output,
1504 * which is often something we want to debug. So this is here in
1505 * case you're doing that.
1508 brw_dump_compile(p
, stdout
, 0, p
->next_insn_offset
);
1513 fs_generator::generate_assembly(exec_list
*simd8_instructions
,
1514 exec_list
*simd16_instructions
,
1515 unsigned *assembly_size
)
1518 generate_code(simd8_instructions
);
1520 if (simd16_instructions
) {
1521 /* We have to do a compaction pass now, or the one at the end of
1522 * execution will squash down where our prog_offset start needs
1525 brw_compact_instructions(p
);
1527 /* align to 64 byte boundary. */
1528 while ((p
->nr_insn
* sizeof(struct brw_instruction
)) % 64) {
1532 /* Save off the start of this 16-wide program */
1533 c
->prog_data
.prog_offset_16
= p
->nr_insn
* sizeof(struct brw_instruction
);
1535 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1537 dispatch_width
= 16;
1538 generate_code(simd16_instructions
);
1541 return brw_get_program(p
, assembly_size
);