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i965/fs: Move message header and texture offset setup to generate_tex().
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_emit.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_emit.cpp
25 *
26 * This file supports emitting code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_fs_cfg.h"
38 #include "glsl/ir_print_visitor.h"
39
40 void
41 fs_visitor::generate_fb_write(fs_inst *inst)
42 {
43 bool eot = inst->eot;
44 struct brw_reg implied_header;
45 uint32_t msg_control;
46
47 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
48 * move, here's g1.
49 */
50 brw_push_insn_state(p);
51 brw_set_mask_control(p, BRW_MASK_DISABLE);
52 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
53
54 if (inst->header_present) {
55 if (intel->gen >= 6) {
56 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
57 brw_MOV(p,
58 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
59 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
60 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
61
62 if (inst->target > 0) {
63 /* Set the render target index for choosing BLEND_STATE. */
64 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
65 inst->base_mrf, 2),
66 BRW_REGISTER_TYPE_UD),
67 brw_imm_ud(inst->target));
68 }
69
70 implied_header = brw_null_reg();
71 } else {
72 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
73
74 brw_MOV(p,
75 brw_message_reg(inst->base_mrf + 1),
76 brw_vec8_grf(1, 0));
77 }
78 } else {
79 implied_header = brw_null_reg();
80 }
81
82 if (this->dual_src_output.file != BAD_FILE)
83 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
84 else if (c->dispatch_width == 16)
85 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
86 else
87 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
88
89 brw_pop_insn_state(p);
90
91 brw_fb_WRITE(p,
92 c->dispatch_width,
93 inst->base_mrf,
94 implied_header,
95 msg_control,
96 inst->target,
97 inst->mlen,
98 0,
99 eot,
100 inst->header_present);
101 }
102
103 /* Computes the integer pixel x,y values from the origin.
104 *
105 * This is the basis of gl_FragCoord computation, but is also used
106 * pre-gen6 for computing the deltas from v0 for computing
107 * interpolation.
108 */
109 void
110 fs_visitor::generate_pixel_xy(struct brw_reg dst, bool is_x)
111 {
112 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
113 struct brw_reg src;
114 struct brw_reg deltas;
115
116 if (is_x) {
117 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
118 deltas = brw_imm_v(0x10101010);
119 } else {
120 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
121 deltas = brw_imm_v(0x11001100);
122 }
123
124 if (c->dispatch_width == 16) {
125 dst = vec16(dst);
126 }
127
128 /* We do this 8 or 16-wide, but since the destination is UW we
129 * don't do compression in the 16-wide case.
130 */
131 brw_push_insn_state(p);
132 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
133 brw_ADD(p, dst, src, deltas);
134 brw_pop_insn_state(p);
135 }
136
137 void
138 fs_visitor::generate_linterp(fs_inst *inst,
139 struct brw_reg dst, struct brw_reg *src)
140 {
141 struct brw_reg delta_x = src[0];
142 struct brw_reg delta_y = src[1];
143 struct brw_reg interp = src[2];
144
145 if (brw->has_pln &&
146 delta_y.nr == delta_x.nr + 1 &&
147 (intel->gen >= 6 || (delta_x.nr & 1) == 0)) {
148 brw_PLN(p, dst, interp, delta_x);
149 } else {
150 brw_LINE(p, brw_null_reg(), interp, delta_x);
151 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
152 }
153 }
154
155 void
156 fs_visitor::generate_math1_gen7(fs_inst *inst,
157 struct brw_reg dst,
158 struct brw_reg src0)
159 {
160 assert(inst->mlen == 0);
161 brw_math(p, dst,
162 brw_math_function(inst->opcode),
163 inst->saturate ? BRW_MATH_SATURATE_SATURATE
164 : BRW_MATH_SATURATE_NONE,
165 0, src0,
166 BRW_MATH_DATA_VECTOR,
167 BRW_MATH_PRECISION_FULL);
168 }
169
170 void
171 fs_visitor::generate_math2_gen7(fs_inst *inst,
172 struct brw_reg dst,
173 struct brw_reg src0,
174 struct brw_reg src1)
175 {
176 assert(inst->mlen == 0);
177 brw_math2(p, dst, brw_math_function(inst->opcode), src0, src1);
178 }
179
180 void
181 fs_visitor::generate_math1_gen6(fs_inst *inst,
182 struct brw_reg dst,
183 struct brw_reg src0)
184 {
185 int op = brw_math_function(inst->opcode);
186
187 assert(inst->mlen == 0);
188
189 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
190 brw_math(p, dst,
191 op,
192 inst->saturate ? BRW_MATH_SATURATE_SATURATE :
193 BRW_MATH_SATURATE_NONE,
194 0, src0,
195 BRW_MATH_DATA_VECTOR,
196 BRW_MATH_PRECISION_FULL);
197
198 if (c->dispatch_width == 16) {
199 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
200 brw_math(p, sechalf(dst),
201 op,
202 inst->saturate ? BRW_MATH_SATURATE_SATURATE :
203 BRW_MATH_SATURATE_NONE,
204 0, sechalf(src0),
205 BRW_MATH_DATA_VECTOR,
206 BRW_MATH_PRECISION_FULL);
207 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
208 }
209 }
210
211 void
212 fs_visitor::generate_math2_gen6(fs_inst *inst,
213 struct brw_reg dst,
214 struct brw_reg src0,
215 struct brw_reg src1)
216 {
217 int op = brw_math_function(inst->opcode);
218
219 assert(inst->mlen == 0);
220
221 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
222 brw_math2(p, dst, op, src0, src1);
223
224 if (c->dispatch_width == 16) {
225 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
226 brw_math2(p, sechalf(dst), op, sechalf(src0), sechalf(src1));
227 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
228 }
229 }
230
231 void
232 fs_visitor::generate_math_gen4(fs_inst *inst,
233 struct brw_reg dst,
234 struct brw_reg src)
235 {
236 int op = brw_math_function(inst->opcode);
237
238 assert(inst->mlen >= 1);
239
240 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
241 brw_math(p, dst,
242 op,
243 inst->saturate ? BRW_MATH_SATURATE_SATURATE :
244 BRW_MATH_SATURATE_NONE,
245 inst->base_mrf, src,
246 BRW_MATH_DATA_VECTOR,
247 BRW_MATH_PRECISION_FULL);
248
249 if (c->dispatch_width == 16) {
250 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
251 brw_math(p, sechalf(dst),
252 op,
253 inst->saturate ? BRW_MATH_SATURATE_SATURATE :
254 BRW_MATH_SATURATE_NONE,
255 inst->base_mrf + 1, sechalf(src),
256 BRW_MATH_DATA_VECTOR,
257 BRW_MATH_PRECISION_FULL);
258
259 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
260 }
261 }
262
263 void
264 fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
265 {
266 int msg_type = -1;
267 int rlen = 4;
268 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
269 uint32_t return_format;
270
271 switch (dst.type) {
272 case BRW_REGISTER_TYPE_D:
273 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
274 break;
275 case BRW_REGISTER_TYPE_UD:
276 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
277 break;
278 default:
279 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
280 break;
281 }
282
283 if (c->dispatch_width == 16)
284 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
285
286 if (intel->gen >= 5) {
287 switch (inst->opcode) {
288 case SHADER_OPCODE_TEX:
289 if (inst->shadow_compare) {
290 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
291 } else {
292 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
293 }
294 break;
295 case FS_OPCODE_TXB:
296 if (inst->shadow_compare) {
297 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
298 } else {
299 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
300 }
301 break;
302 case SHADER_OPCODE_TXL:
303 if (inst->shadow_compare) {
304 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
305 } else {
306 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
307 }
308 break;
309 case SHADER_OPCODE_TXS:
310 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
311 break;
312 case SHADER_OPCODE_TXD:
313 /* There is no sample_d_c message; comparisons are done manually */
314 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
315 break;
316 case SHADER_OPCODE_TXF:
317 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
318 break;
319 default:
320 assert(!"not reached");
321 break;
322 }
323 } else {
324 switch (inst->opcode) {
325 case SHADER_OPCODE_TEX:
326 /* Note that G45 and older determines shadow compare and dispatch width
327 * from message length for most messages.
328 */
329 assert(c->dispatch_width == 8);
330 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
331 if (inst->shadow_compare) {
332 assert(inst->mlen == 6);
333 } else {
334 assert(inst->mlen <= 4);
335 }
336 break;
337 case FS_OPCODE_TXB:
338 if (inst->shadow_compare) {
339 assert(inst->mlen == 6);
340 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
341 } else {
342 assert(inst->mlen == 9);
343 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
344 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
345 }
346 break;
347 case SHADER_OPCODE_TXL:
348 if (inst->shadow_compare) {
349 assert(inst->mlen == 6);
350 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
351 } else {
352 assert(inst->mlen == 9);
353 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
354 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
355 }
356 break;
357 case SHADER_OPCODE_TXD:
358 /* There is no sample_d_c message; comparisons are done manually */
359 assert(inst->mlen == 7 || inst->mlen == 10);
360 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
361 break;
362 case SHADER_OPCODE_TXF:
363 assert(inst->mlen == 9);
364 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
365 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
366 break;
367 case SHADER_OPCODE_TXS:
368 assert(inst->mlen == 3);
369 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
370 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
371 break;
372 default:
373 assert(!"not reached");
374 break;
375 }
376 }
377 assert(msg_type != -1);
378
379 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
380 rlen = 8;
381 dst = vec16(dst);
382 }
383
384 /* Load the message header if present. If there's a texture offset,
385 * we need to set it up explicitly and load the offset bitfield.
386 * Otherwise, we can use an implied move from g0 to the first message reg.
387 */
388 if (inst->texture_offset) {
389 brw_push_insn_state(p);
390 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
391 /* Explicitly set up the message header by copying g0 to the MRF. */
392 brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
393 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
394
395 /* Then set the offset bits in DWord 2. */
396 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
397 inst->base_mrf, 2), BRW_REGISTER_TYPE_UD),
398 brw_imm_ud(inst->texture_offset));
399 brw_pop_insn_state(p);
400 } else if (inst->header_present) {
401 /* Set up an implied move from g0 to the MRF. */
402 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
403 }
404
405 brw_SAMPLE(p,
406 retype(dst, BRW_REGISTER_TYPE_UW),
407 inst->base_mrf,
408 src,
409 SURF_INDEX_TEXTURE(inst->sampler),
410 inst->sampler,
411 WRITEMASK_XYZW,
412 msg_type,
413 rlen,
414 inst->mlen,
415 inst->header_present,
416 simd_mode,
417 return_format);
418 }
419
420
421 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
422 * looking like:
423 *
424 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
425 *
426 * and we're trying to produce:
427 *
428 * DDX DDY
429 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
430 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
431 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
432 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
433 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
434 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
435 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
436 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
437 *
438 * and add another set of two more subspans if in 16-pixel dispatch mode.
439 *
440 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
441 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
442 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
443 * between each other. We could probably do it like ddx and swizzle the right
444 * order later, but bail for now and just produce
445 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
446 */
447 void
448 fs_visitor::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
449 {
450 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
451 BRW_REGISTER_TYPE_F,
452 BRW_VERTICAL_STRIDE_2,
453 BRW_WIDTH_2,
454 BRW_HORIZONTAL_STRIDE_0,
455 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
456 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
457 BRW_REGISTER_TYPE_F,
458 BRW_VERTICAL_STRIDE_2,
459 BRW_WIDTH_2,
460 BRW_HORIZONTAL_STRIDE_0,
461 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
462 brw_ADD(p, dst, src0, negate(src1));
463 }
464
465 /* The negate_value boolean is used to negate the derivative computation for
466 * FBOs, since they place the origin at the upper left instead of the lower
467 * left.
468 */
469 void
470 fs_visitor::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
471 bool negate_value)
472 {
473 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
474 BRW_REGISTER_TYPE_F,
475 BRW_VERTICAL_STRIDE_4,
476 BRW_WIDTH_4,
477 BRW_HORIZONTAL_STRIDE_0,
478 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
479 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
480 BRW_REGISTER_TYPE_F,
481 BRW_VERTICAL_STRIDE_4,
482 BRW_WIDTH_4,
483 BRW_HORIZONTAL_STRIDE_0,
484 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
485 if (negate_value)
486 brw_ADD(p, dst, src1, negate(src0));
487 else
488 brw_ADD(p, dst, src0, negate(src1));
489 }
490
491 void
492 fs_visitor::generate_discard(fs_inst *inst)
493 {
494 struct brw_reg f0 = brw_flag_reg();
495
496 if (intel->gen >= 6) {
497 struct brw_reg g1 = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
498 struct brw_reg some_register;
499
500 /* As of gen6, we no longer have the mask register to look at,
501 * so life gets a bit more complicated.
502 */
503
504 /* Load the flag register with all ones. */
505 brw_push_insn_state(p);
506 brw_set_mask_control(p, BRW_MASK_DISABLE);
507 brw_MOV(p, f0, brw_imm_uw(0xffff));
508 brw_pop_insn_state(p);
509
510 /* Do a comparison that should always fail, to produce 0s in the flag
511 * reg where we have active channels.
512 */
513 some_register = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
514 brw_CMP(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
515 BRW_CONDITIONAL_NZ, some_register, some_register);
516
517 /* Undo CMP's whacking of predication*/
518 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
519
520 brw_push_insn_state(p);
521 brw_set_mask_control(p, BRW_MASK_DISABLE);
522 brw_AND(p, g1, f0, g1);
523 brw_pop_insn_state(p);
524 } else {
525 struct brw_reg g0 = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
526
527 brw_push_insn_state(p);
528 brw_set_mask_control(p, BRW_MASK_DISABLE);
529 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
530
531 /* Unlike the 965, we have the mask reg, so we just need
532 * somewhere to invert that (containing channels to be disabled)
533 * so it can be ANDed with the mask of pixels still to be
534 * written. Use the flag reg for consistency with gen6+.
535 */
536 brw_NOT(p, f0, brw_mask_reg(1)); /* IMASK */
537 brw_AND(p, g0, f0, g0);
538
539 brw_pop_insn_state(p);
540 }
541 }
542
543 void
544 fs_visitor::generate_spill(fs_inst *inst, struct brw_reg src)
545 {
546 assert(inst->mlen != 0);
547
548 brw_MOV(p,
549 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
550 retype(src, BRW_REGISTER_TYPE_UD));
551 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf), 1,
552 inst->offset);
553 }
554
555 void
556 fs_visitor::generate_unspill(fs_inst *inst, struct brw_reg dst)
557 {
558 assert(inst->mlen != 0);
559
560 /* Clear any post destination dependencies that would be ignored by
561 * the block read. See the B-Spec for pre-gen5 send instruction.
562 *
563 * This could use a better solution, since texture sampling and
564 * math reads could potentially run into it as well -- anywhere
565 * that we have a SEND with a destination that is a register that
566 * was written but not read within the last N instructions (what's
567 * N? unsure). This is rare because of dead code elimination, but
568 * not impossible.
569 */
570 if (intel->gen == 4 && !intel->is_g4x)
571 brw_MOV(p, brw_null_reg(), dst);
572
573 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf), 1,
574 inst->offset);
575
576 if (intel->gen == 4 && !intel->is_g4x) {
577 /* gen4 errata: destination from a send can't be used as a
578 * destination until it's been read. Just read it so we don't
579 * have to worry.
580 */
581 brw_MOV(p, brw_null_reg(), dst);
582 }
583 }
584
585 void
586 fs_visitor::generate_pull_constant_load(fs_inst *inst, struct brw_reg dst)
587 {
588 assert(inst->mlen != 0);
589
590 /* Clear any post destination dependencies that would be ignored by
591 * the block read. See the B-Spec for pre-gen5 send instruction.
592 *
593 * This could use a better solution, since texture sampling and
594 * math reads could potentially run into it as well -- anywhere
595 * that we have a SEND with a destination that is a register that
596 * was written but not read within the last N instructions (what's
597 * N? unsure). This is rare because of dead code elimination, but
598 * not impossible.
599 */
600 if (intel->gen == 4 && !intel->is_g4x)
601 brw_MOV(p, brw_null_reg(), dst);
602
603 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
604 inst->offset, SURF_INDEX_FRAG_CONST_BUFFER);
605
606 if (intel->gen == 4 && !intel->is_g4x) {
607 /* gen4 errata: destination from a send can't be used as a
608 * destination until it's been read. Just read it so we don't
609 * have to worry.
610 */
611 brw_MOV(p, brw_null_reg(), dst);
612 }
613 }
614
615
616 /**
617 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
618 * into the flags register (f0.0).
619 *
620 * Used only on Gen6 and above.
621 */
622 void
623 fs_visitor::generate_mov_dispatch_to_flags()
624 {
625 struct brw_reg f0 = brw_flag_reg();
626 struct brw_reg g1 = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
627
628 assert (intel->gen >= 6);
629 brw_push_insn_state(p);
630 brw_set_mask_control(p, BRW_MASK_DISABLE);
631 brw_MOV(p, f0, g1);
632 brw_pop_insn_state(p);
633 }
634
635
636 static uint32_t brw_file_from_reg(fs_reg *reg)
637 {
638 switch (reg->file) {
639 case ARF:
640 return BRW_ARCHITECTURE_REGISTER_FILE;
641 case GRF:
642 return BRW_GENERAL_REGISTER_FILE;
643 case MRF:
644 return BRW_MESSAGE_REGISTER_FILE;
645 case IMM:
646 return BRW_IMMEDIATE_VALUE;
647 default:
648 assert(!"not reached");
649 return BRW_GENERAL_REGISTER_FILE;
650 }
651 }
652
653 static struct brw_reg
654 brw_reg_from_fs_reg(fs_reg *reg)
655 {
656 struct brw_reg brw_reg;
657
658 switch (reg->file) {
659 case GRF:
660 case ARF:
661 case MRF:
662 if (reg->smear == -1) {
663 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
664 } else {
665 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, reg->smear);
666 }
667 brw_reg = retype(brw_reg, reg->type);
668 if (reg->sechalf)
669 brw_reg = sechalf(brw_reg);
670 break;
671 case IMM:
672 switch (reg->type) {
673 case BRW_REGISTER_TYPE_F:
674 brw_reg = brw_imm_f(reg->imm.f);
675 break;
676 case BRW_REGISTER_TYPE_D:
677 brw_reg = brw_imm_d(reg->imm.i);
678 break;
679 case BRW_REGISTER_TYPE_UD:
680 brw_reg = brw_imm_ud(reg->imm.u);
681 break;
682 default:
683 assert(!"not reached");
684 brw_reg = brw_null_reg();
685 break;
686 }
687 break;
688 case FIXED_HW_REG:
689 brw_reg = reg->fixed_hw_reg;
690 break;
691 case BAD_FILE:
692 /* Probably unused. */
693 brw_reg = brw_null_reg();
694 break;
695 case UNIFORM:
696 assert(!"not reached");
697 brw_reg = brw_null_reg();
698 break;
699 default:
700 assert(!"not reached");
701 brw_reg = brw_null_reg();
702 break;
703 }
704 if (reg->abs)
705 brw_reg = brw_abs(brw_reg);
706 if (reg->negate)
707 brw_reg = negate(brw_reg);
708
709 return brw_reg;
710 }
711
712 void
713 fs_visitor::generate_code()
714 {
715 int last_native_inst = p->nr_insn;
716 const char *last_annotation_string = NULL;
717 ir_instruction *last_annotation_ir = NULL;
718
719 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
720 printf("Native code for fragment shader %d (%d-wide dispatch):\n",
721 prog->Name, c->dispatch_width);
722 }
723
724 fs_cfg *cfg = NULL;
725 if (unlikely(INTEL_DEBUG & DEBUG_WM))
726 cfg = new(mem_ctx) fs_cfg(this);
727
728 foreach_list(node, &this->instructions) {
729 fs_inst *inst = (fs_inst *)node;
730 struct brw_reg src[3], dst;
731
732 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
733 foreach_list(node, &cfg->block_list) {
734 fs_bblock_link *link = (fs_bblock_link *)node;
735 fs_bblock *block = link->block;
736
737 if (block->start == inst) {
738 printf(" START B%d", block->block_num);
739 foreach_list(predecessor_node, &block->parents) {
740 fs_bblock_link *predecessor_link =
741 (fs_bblock_link *)predecessor_node;
742 fs_bblock *predecessor_block = predecessor_link->block;
743 printf(" <-B%d", predecessor_block->block_num);
744 }
745 printf("\n");
746 }
747 }
748
749 if (last_annotation_ir != inst->ir) {
750 last_annotation_ir = inst->ir;
751 if (last_annotation_ir) {
752 printf(" ");
753 last_annotation_ir->print();
754 printf("\n");
755 }
756 }
757 if (last_annotation_string != inst->annotation) {
758 last_annotation_string = inst->annotation;
759 if (last_annotation_string)
760 printf(" %s\n", last_annotation_string);
761 }
762 }
763
764 for (unsigned int i = 0; i < 3; i++) {
765 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
766
767 /* The accumulator result appears to get used for the
768 * conditional modifier generation. When negating a UD
769 * value, there is a 33rd bit generated for the sign in the
770 * accumulator value, so now you can't check, for example,
771 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
772 */
773 assert(!inst->conditional_mod ||
774 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
775 !inst->src[i].negate);
776 }
777 dst = brw_reg_from_fs_reg(&inst->dst);
778
779 brw_set_conditionalmod(p, inst->conditional_mod);
780 brw_set_predicate_control(p, inst->predicated);
781 brw_set_predicate_inverse(p, inst->predicate_inverse);
782 brw_set_saturate(p, inst->saturate);
783
784 if (inst->force_uncompressed || c->dispatch_width == 8) {
785 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
786 } else if (inst->force_sechalf) {
787 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
788 } else {
789 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
790 }
791
792 switch (inst->opcode) {
793 case BRW_OPCODE_MOV:
794 brw_MOV(p, dst, src[0]);
795 break;
796 case BRW_OPCODE_ADD:
797 brw_ADD(p, dst, src[0], src[1]);
798 break;
799 case BRW_OPCODE_MUL:
800 brw_MUL(p, dst, src[0], src[1]);
801 break;
802 case BRW_OPCODE_MACH:
803 brw_set_acc_write_control(p, 1);
804 brw_MACH(p, dst, src[0], src[1]);
805 brw_set_acc_write_control(p, 0);
806 break;
807
808 case BRW_OPCODE_MAD:
809 brw_set_access_mode(p, BRW_ALIGN_16);
810 if (c->dispatch_width == 16) {
811 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
812 brw_MAD(p, dst, src[0], src[1], src[2]);
813 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
814 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
815 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
816 } else {
817 brw_MAD(p, dst, src[0], src[1], src[2]);
818 }
819 brw_set_access_mode(p, BRW_ALIGN_1);
820 break;
821
822 case BRW_OPCODE_FRC:
823 brw_FRC(p, dst, src[0]);
824 break;
825 case BRW_OPCODE_RNDD:
826 brw_RNDD(p, dst, src[0]);
827 break;
828 case BRW_OPCODE_RNDE:
829 brw_RNDE(p, dst, src[0]);
830 break;
831 case BRW_OPCODE_RNDZ:
832 brw_RNDZ(p, dst, src[0]);
833 break;
834
835 case BRW_OPCODE_AND:
836 brw_AND(p, dst, src[0], src[1]);
837 break;
838 case BRW_OPCODE_OR:
839 brw_OR(p, dst, src[0], src[1]);
840 break;
841 case BRW_OPCODE_XOR:
842 brw_XOR(p, dst, src[0], src[1]);
843 break;
844 case BRW_OPCODE_NOT:
845 brw_NOT(p, dst, src[0]);
846 break;
847 case BRW_OPCODE_ASR:
848 brw_ASR(p, dst, src[0], src[1]);
849 break;
850 case BRW_OPCODE_SHR:
851 brw_SHR(p, dst, src[0], src[1]);
852 break;
853 case BRW_OPCODE_SHL:
854 brw_SHL(p, dst, src[0], src[1]);
855 break;
856
857 case BRW_OPCODE_CMP:
858 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
859 break;
860 case BRW_OPCODE_SEL:
861 brw_SEL(p, dst, src[0], src[1]);
862 break;
863
864 case BRW_OPCODE_IF:
865 if (inst->src[0].file != BAD_FILE) {
866 /* The instruction has an embedded compare (only allowed on gen6) */
867 assert(intel->gen == 6);
868 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
869 } else {
870 brw_IF(p, c->dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
871 }
872 break;
873
874 case BRW_OPCODE_ELSE:
875 brw_ELSE(p);
876 break;
877 case BRW_OPCODE_ENDIF:
878 brw_ENDIF(p);
879 break;
880
881 case BRW_OPCODE_DO:
882 brw_DO(p, BRW_EXECUTE_8);
883 break;
884
885 case BRW_OPCODE_BREAK:
886 brw_BREAK(p);
887 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
888 break;
889 case BRW_OPCODE_CONTINUE:
890 /* FINISHME: We need to write the loop instruction support still. */
891 if (intel->gen >= 6)
892 gen6_CONT(p);
893 else
894 brw_CONT(p);
895 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
896 break;
897
898 case BRW_OPCODE_WHILE:
899 brw_WHILE(p);
900 break;
901
902 case SHADER_OPCODE_RCP:
903 case SHADER_OPCODE_RSQ:
904 case SHADER_OPCODE_SQRT:
905 case SHADER_OPCODE_EXP2:
906 case SHADER_OPCODE_LOG2:
907 case SHADER_OPCODE_SIN:
908 case SHADER_OPCODE_COS:
909 if (intel->gen >= 7) {
910 generate_math1_gen7(inst, dst, src[0]);
911 } else if (intel->gen == 6) {
912 generate_math1_gen6(inst, dst, src[0]);
913 } else {
914 generate_math_gen4(inst, dst, src[0]);
915 }
916 break;
917 case SHADER_OPCODE_INT_QUOTIENT:
918 case SHADER_OPCODE_INT_REMAINDER:
919 case SHADER_OPCODE_POW:
920 if (intel->gen >= 7) {
921 generate_math2_gen7(inst, dst, src[0], src[1]);
922 } else if (intel->gen == 6) {
923 generate_math2_gen6(inst, dst, src[0], src[1]);
924 } else {
925 generate_math_gen4(inst, dst, src[0]);
926 }
927 break;
928 case FS_OPCODE_PIXEL_X:
929 generate_pixel_xy(dst, true);
930 break;
931 case FS_OPCODE_PIXEL_Y:
932 generate_pixel_xy(dst, false);
933 break;
934 case FS_OPCODE_CINTERP:
935 brw_MOV(p, dst, src[0]);
936 break;
937 case FS_OPCODE_LINTERP:
938 generate_linterp(inst, dst, src);
939 break;
940 case SHADER_OPCODE_TEX:
941 case FS_OPCODE_TXB:
942 case SHADER_OPCODE_TXD:
943 case SHADER_OPCODE_TXF:
944 case SHADER_OPCODE_TXL:
945 case SHADER_OPCODE_TXS:
946 generate_tex(inst, dst, src[0]);
947 break;
948 case FS_OPCODE_DISCARD:
949 generate_discard(inst);
950 break;
951 case FS_OPCODE_DDX:
952 generate_ddx(inst, dst, src[0]);
953 break;
954 case FS_OPCODE_DDY:
955 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
956 * guarantee that c->key.render_to_fbo is set).
957 */
958 assert(fp->UsesDFdy);
959 generate_ddy(inst, dst, src[0], c->key.render_to_fbo);
960 break;
961
962 case FS_OPCODE_SPILL:
963 generate_spill(inst, src[0]);
964 break;
965
966 case FS_OPCODE_UNSPILL:
967 generate_unspill(inst, dst);
968 break;
969
970 case FS_OPCODE_PULL_CONSTANT_LOAD:
971 generate_pull_constant_load(inst, dst);
972 break;
973
974 case FS_OPCODE_FB_WRITE:
975 generate_fb_write(inst);
976 break;
977
978 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
979 generate_mov_dispatch_to_flags();
980 break;
981
982 default:
983 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
984 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
985 brw_opcodes[inst->opcode].name);
986 } else {
987 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
988 }
989 fail("unsupported opcode in FS\n");
990 }
991
992 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
993 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) {
994 if (0) {
995 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
996 ((uint32_t *)&p->store[i])[3],
997 ((uint32_t *)&p->store[i])[2],
998 ((uint32_t *)&p->store[i])[1],
999 ((uint32_t *)&p->store[i])[0]);
1000 }
1001 brw_disasm(stdout, &p->store[i], intel->gen);
1002 }
1003
1004 foreach_list(node, &cfg->block_list) {
1005 fs_bblock_link *link = (fs_bblock_link *)node;
1006 fs_bblock *block = link->block;
1007
1008 if (block->end == inst) {
1009 printf(" END B%d", block->block_num);
1010 foreach_list(successor_node, &block->children) {
1011 fs_bblock_link *successor_link =
1012 (fs_bblock_link *)successor_node;
1013 fs_bblock *successor_block = successor_link->block;
1014 printf(" ->B%d", successor_block->block_num);
1015 }
1016 printf("\n");
1017 }
1018 }
1019 }
1020
1021 last_native_inst = p->nr_insn;
1022 }
1023
1024 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1025 printf("\n");
1026 }
1027
1028 brw_set_uip_jip(p);
1029
1030 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
1031 * emit issues, it doesn't get the jump distances into the output,
1032 * which is often something we want to debug. So this is here in
1033 * case you're doing that.
1034 */
1035 if (0) {
1036 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1037 for (unsigned int i = 0; i < p->nr_insn; i++) {
1038 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
1039 ((uint32_t *)&p->store[i])[3],
1040 ((uint32_t *)&p->store[i])[2],
1041 ((uint32_t *)&p->store[i])[1],
1042 ((uint32_t *)&p->store[i])[0]);
1043 brw_disasm(stdout, &p->store[i], intel->gen);
1044 }
1045 }
1046 }
1047 }