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i965: Share the register file enum between the two backends.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_emit.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_emit.cpp
25 *
26 * This file supports emitting code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38 #include "glsl/ir_print_visitor.h"
39
40 fs_generator::fs_generator(struct brw_context *brw,
41 struct brw_wm_compile *c,
42 struct gl_shader_program *prog,
43 struct gl_fragment_program *fp,
44 bool dual_source_output)
45
46 : brw(brw), c(c), prog(prog), fp(fp), dual_source_output(dual_source_output)
47 {
48 intel = &brw->intel;
49 ctx = &intel->ctx;
50
51 shader = prog ? prog->_LinkedShaders[MESA_SHADER_FRAGMENT] : NULL;
52
53 mem_ctx = c;
54
55 p = rzalloc(mem_ctx, struct brw_compile);
56 brw_init_compile(brw, p, mem_ctx);
57 }
58
59 fs_generator::~fs_generator()
60 {
61 }
62
63 void
64 fs_generator::patch_discard_jumps_to_fb_writes()
65 {
66 if (intel->gen < 6 || this->discard_halt_patches.is_empty())
67 return;
68
69 /* There is a somewhat strange undocumented requirement of using
70 * HALT, according to the simulator. If some channel has HALTed to
71 * a particular UIP, then by the end of the program, every channel
72 * must have HALTed to that UIP. Furthermore, the tracking is a
73 * stack, so you can't do the final halt of a UIP after starting
74 * halting to a new UIP.
75 *
76 * Symptoms of not emitting this instruction on actual hardware
77 * included GPU hangs and sparkly rendering on the piglit discard
78 * tests.
79 */
80 struct brw_instruction *last_halt = gen6_HALT(p);
81 last_halt->bits3.break_cont.uip = 2;
82 last_halt->bits3.break_cont.jip = 2;
83
84 int ip = p->nr_insn;
85
86 foreach_list(node, &this->discard_halt_patches) {
87 ip_record *patch_ip = (ip_record *)node;
88 struct brw_instruction *patch = &p->store[patch_ip->ip];
89
90 assert(patch->header.opcode == BRW_OPCODE_HALT);
91 /* HALT takes a half-instruction distance from the pre-incremented IP. */
92 patch->bits3.break_cont.uip = (ip - patch_ip->ip) * 2;
93 }
94
95 this->discard_halt_patches.make_empty();
96 }
97
98 void
99 fs_generator::generate_fb_write(fs_inst *inst)
100 {
101 bool eot = inst->eot;
102 struct brw_reg implied_header;
103 uint32_t msg_control;
104
105 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
106 * move, here's g1.
107 */
108 brw_push_insn_state(p);
109 brw_set_mask_control(p, BRW_MASK_DISABLE);
110 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
111
112 if (fp->UsesKill) {
113 struct brw_reg pixel_mask;
114
115 if (intel->gen >= 6)
116 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
117 else
118 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
119
120 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
121 }
122
123 if (inst->header_present) {
124 if (intel->gen >= 6) {
125 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
126 brw_MOV(p,
127 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
128 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
129 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
130
131 if (inst->target > 0 &&
132 c->key.nr_color_regions > 1 &&
133 c->key.sample_alpha_to_coverage) {
134 /* Set "Source0 Alpha Present to RenderTarget" bit in message
135 * header.
136 */
137 brw_OR(p,
138 vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)),
139 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
140 brw_imm_ud(0x1 << 11));
141 }
142
143 if (inst->target > 0) {
144 /* Set the render target index for choosing BLEND_STATE. */
145 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
146 inst->base_mrf, 2),
147 BRW_REGISTER_TYPE_UD),
148 brw_imm_ud(inst->target));
149 }
150
151 implied_header = brw_null_reg();
152 } else {
153 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
154
155 brw_MOV(p,
156 brw_message_reg(inst->base_mrf + 1),
157 brw_vec8_grf(1, 0));
158 }
159 } else {
160 implied_header = brw_null_reg();
161 }
162
163 if (this->dual_source_output)
164 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
165 else if (dispatch_width == 16)
166 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
167 else
168 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
169
170 brw_pop_insn_state(p);
171
172 brw_fb_WRITE(p,
173 dispatch_width,
174 inst->base_mrf,
175 implied_header,
176 msg_control,
177 inst->target,
178 inst->mlen,
179 0,
180 eot,
181 inst->header_present);
182 }
183
184 /* Computes the integer pixel x,y values from the origin.
185 *
186 * This is the basis of gl_FragCoord computation, but is also used
187 * pre-gen6 for computing the deltas from v0 for computing
188 * interpolation.
189 */
190 void
191 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
192 {
193 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
194 struct brw_reg src;
195 struct brw_reg deltas;
196
197 if (is_x) {
198 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
199 deltas = brw_imm_v(0x10101010);
200 } else {
201 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
202 deltas = brw_imm_v(0x11001100);
203 }
204
205 if (dispatch_width == 16) {
206 dst = vec16(dst);
207 }
208
209 /* We do this 8 or 16-wide, but since the destination is UW we
210 * don't do compression in the 16-wide case.
211 */
212 brw_push_insn_state(p);
213 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
214 brw_ADD(p, dst, src, deltas);
215 brw_pop_insn_state(p);
216 }
217
218 void
219 fs_generator::generate_linterp(fs_inst *inst,
220 struct brw_reg dst, struct brw_reg *src)
221 {
222 struct brw_reg delta_x = src[0];
223 struct brw_reg delta_y = src[1];
224 struct brw_reg interp = src[2];
225
226 if (brw->has_pln &&
227 delta_y.nr == delta_x.nr + 1 &&
228 (intel->gen >= 6 || (delta_x.nr & 1) == 0)) {
229 brw_PLN(p, dst, interp, delta_x);
230 } else {
231 brw_LINE(p, brw_null_reg(), interp, delta_x);
232 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
233 }
234 }
235
236 void
237 fs_generator::generate_math1_gen7(fs_inst *inst,
238 struct brw_reg dst,
239 struct brw_reg src0)
240 {
241 assert(inst->mlen == 0);
242 brw_math(p, dst,
243 brw_math_function(inst->opcode),
244 0, src0,
245 BRW_MATH_DATA_VECTOR,
246 BRW_MATH_PRECISION_FULL);
247 }
248
249 void
250 fs_generator::generate_math2_gen7(fs_inst *inst,
251 struct brw_reg dst,
252 struct brw_reg src0,
253 struct brw_reg src1)
254 {
255 assert(inst->mlen == 0);
256 brw_math2(p, dst, brw_math_function(inst->opcode), src0, src1);
257 }
258
259 void
260 fs_generator::generate_math1_gen6(fs_inst *inst,
261 struct brw_reg dst,
262 struct brw_reg src0)
263 {
264 int op = brw_math_function(inst->opcode);
265
266 assert(inst->mlen == 0);
267
268 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
269 brw_math(p, dst,
270 op,
271 0, src0,
272 BRW_MATH_DATA_VECTOR,
273 BRW_MATH_PRECISION_FULL);
274
275 if (dispatch_width == 16) {
276 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
277 brw_math(p, sechalf(dst),
278 op,
279 0, sechalf(src0),
280 BRW_MATH_DATA_VECTOR,
281 BRW_MATH_PRECISION_FULL);
282 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
283 }
284 }
285
286 void
287 fs_generator::generate_math2_gen6(fs_inst *inst,
288 struct brw_reg dst,
289 struct brw_reg src0,
290 struct brw_reg src1)
291 {
292 int op = brw_math_function(inst->opcode);
293
294 assert(inst->mlen == 0);
295
296 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
297 brw_math2(p, dst, op, src0, src1);
298
299 if (dispatch_width == 16) {
300 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
301 brw_math2(p, sechalf(dst), op, sechalf(src0), sechalf(src1));
302 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
303 }
304 }
305
306 void
307 fs_generator::generate_math_gen4(fs_inst *inst,
308 struct brw_reg dst,
309 struct brw_reg src)
310 {
311 int op = brw_math_function(inst->opcode);
312
313 assert(inst->mlen >= 1);
314
315 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
316 brw_math(p, dst,
317 op,
318 inst->base_mrf, src,
319 BRW_MATH_DATA_VECTOR,
320 BRW_MATH_PRECISION_FULL);
321
322 if (dispatch_width == 16) {
323 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
324 brw_math(p, sechalf(dst),
325 op,
326 inst->base_mrf + 1, sechalf(src),
327 BRW_MATH_DATA_VECTOR,
328 BRW_MATH_PRECISION_FULL);
329
330 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
331 }
332 }
333
334 void
335 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
336 {
337 int msg_type = -1;
338 int rlen = 4;
339 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
340 uint32_t return_format;
341
342 switch (dst.type) {
343 case BRW_REGISTER_TYPE_D:
344 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
345 break;
346 case BRW_REGISTER_TYPE_UD:
347 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
348 break;
349 default:
350 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
351 break;
352 }
353
354 if (dispatch_width == 16)
355 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
356
357 if (intel->gen >= 5) {
358 switch (inst->opcode) {
359 case SHADER_OPCODE_TEX:
360 if (inst->shadow_compare) {
361 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
362 } else {
363 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
364 }
365 break;
366 case FS_OPCODE_TXB:
367 if (inst->shadow_compare) {
368 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
369 } else {
370 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
371 }
372 break;
373 case SHADER_OPCODE_TXL:
374 if (inst->shadow_compare) {
375 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
376 } else {
377 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
378 }
379 break;
380 case SHADER_OPCODE_TXS:
381 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
382 break;
383 case SHADER_OPCODE_TXD:
384 if (inst->shadow_compare) {
385 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
386 assert(intel->is_haswell);
387 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
388 } else {
389 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
390 }
391 break;
392 case SHADER_OPCODE_TXF:
393 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
394 break;
395 case SHADER_OPCODE_TXF_MS:
396 if (intel->gen >= 7)
397 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
398 else
399 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
400 break;
401 case SHADER_OPCODE_LOD:
402 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
403 break;
404 default:
405 assert(!"not reached");
406 break;
407 }
408 } else {
409 switch (inst->opcode) {
410 case SHADER_OPCODE_TEX:
411 /* Note that G45 and older determines shadow compare and dispatch width
412 * from message length for most messages.
413 */
414 assert(dispatch_width == 8);
415 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
416 if (inst->shadow_compare) {
417 assert(inst->mlen == 6);
418 } else {
419 assert(inst->mlen <= 4);
420 }
421 break;
422 case FS_OPCODE_TXB:
423 if (inst->shadow_compare) {
424 assert(inst->mlen == 6);
425 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
426 } else {
427 assert(inst->mlen == 9);
428 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
429 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
430 }
431 break;
432 case SHADER_OPCODE_TXL:
433 if (inst->shadow_compare) {
434 assert(inst->mlen == 6);
435 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
436 } else {
437 assert(inst->mlen == 9);
438 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
439 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
440 }
441 break;
442 case SHADER_OPCODE_TXD:
443 /* There is no sample_d_c message; comparisons are done manually */
444 assert(inst->mlen == 7 || inst->mlen == 10);
445 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
446 break;
447 case SHADER_OPCODE_TXF:
448 assert(inst->mlen == 9);
449 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
450 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
451 break;
452 case SHADER_OPCODE_TXS:
453 assert(inst->mlen == 3);
454 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
455 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
456 break;
457 default:
458 assert(!"not reached");
459 break;
460 }
461 }
462 assert(msg_type != -1);
463
464 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
465 rlen = 8;
466 dst = vec16(dst);
467 }
468
469 /* Load the message header if present. If there's a texture offset,
470 * we need to set it up explicitly and load the offset bitfield.
471 * Otherwise, we can use an implied move from g0 to the first message reg.
472 */
473 if (inst->texture_offset) {
474 brw_push_insn_state(p);
475 brw_set_mask_control(p, BRW_MASK_DISABLE);
476 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
477 /* Explicitly set up the message header by copying g0 to the MRF. */
478 brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
479 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
480
481 /* Then set the offset bits in DWord 2. */
482 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
483 inst->base_mrf, 2), BRW_REGISTER_TYPE_UD),
484 brw_imm_ud(inst->texture_offset));
485 brw_pop_insn_state(p);
486 } else if (inst->header_present) {
487 /* Set up an implied move from g0 to the MRF. */
488 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
489 }
490
491 brw_SAMPLE(p,
492 retype(dst, BRW_REGISTER_TYPE_UW),
493 inst->base_mrf,
494 src,
495 SURF_INDEX_TEXTURE(inst->sampler),
496 inst->sampler,
497 msg_type,
498 rlen,
499 inst->mlen,
500 inst->header_present,
501 simd_mode,
502 return_format);
503 }
504
505
506 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
507 * looking like:
508 *
509 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
510 *
511 * and we're trying to produce:
512 *
513 * DDX DDY
514 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
515 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
516 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
517 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
518 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
519 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
520 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
521 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
522 *
523 * and add another set of two more subspans if in 16-pixel dispatch mode.
524 *
525 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
526 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
527 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
528 * between each other. We could probably do it like ddx and swizzle the right
529 * order later, but bail for now and just produce
530 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
531 */
532 void
533 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
534 {
535 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
536 BRW_REGISTER_TYPE_F,
537 BRW_VERTICAL_STRIDE_2,
538 BRW_WIDTH_2,
539 BRW_HORIZONTAL_STRIDE_0,
540 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
541 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
542 BRW_REGISTER_TYPE_F,
543 BRW_VERTICAL_STRIDE_2,
544 BRW_WIDTH_2,
545 BRW_HORIZONTAL_STRIDE_0,
546 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
547 brw_ADD(p, dst, src0, negate(src1));
548 }
549
550 /* The negate_value boolean is used to negate the derivative computation for
551 * FBOs, since they place the origin at the upper left instead of the lower
552 * left.
553 */
554 void
555 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
556 bool negate_value)
557 {
558 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
559 BRW_REGISTER_TYPE_F,
560 BRW_VERTICAL_STRIDE_4,
561 BRW_WIDTH_4,
562 BRW_HORIZONTAL_STRIDE_0,
563 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
564 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
565 BRW_REGISTER_TYPE_F,
566 BRW_VERTICAL_STRIDE_4,
567 BRW_WIDTH_4,
568 BRW_HORIZONTAL_STRIDE_0,
569 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
570 if (negate_value)
571 brw_ADD(p, dst, src1, negate(src0));
572 else
573 brw_ADD(p, dst, src0, negate(src1));
574 }
575
576 void
577 fs_generator::generate_discard_jump(fs_inst *inst)
578 {
579 assert(intel->gen >= 6);
580
581 /* This HALT will be patched up at FB write time to point UIP at the end of
582 * the program, and at brw_uip_jip() JIP will be set to the end of the
583 * current block (or the program).
584 */
585 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
586
587 brw_push_insn_state(p);
588 brw_set_mask_control(p, BRW_MASK_DISABLE);
589 gen6_HALT(p);
590 brw_pop_insn_state(p);
591 }
592
593 void
594 fs_generator::generate_spill(fs_inst *inst, struct brw_reg src)
595 {
596 assert(inst->mlen != 0);
597
598 brw_MOV(p,
599 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
600 retype(src, BRW_REGISTER_TYPE_UD));
601 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf), 1,
602 inst->offset);
603 }
604
605 void
606 fs_generator::generate_unspill(fs_inst *inst, struct brw_reg dst)
607 {
608 assert(inst->mlen != 0);
609
610 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf), 1,
611 inst->offset);
612 }
613
614 void
615 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
616 struct brw_reg dst,
617 struct brw_reg index,
618 struct brw_reg offset)
619 {
620 assert(inst->mlen != 0);
621
622 assert(index.file == BRW_IMMEDIATE_VALUE &&
623 index.type == BRW_REGISTER_TYPE_UD);
624 uint32_t surf_index = index.dw1.ud;
625
626 assert(offset.file == BRW_IMMEDIATE_VALUE &&
627 offset.type == BRW_REGISTER_TYPE_UD);
628 uint32_t read_offset = offset.dw1.ud;
629
630 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
631 read_offset, surf_index);
632 }
633
634 void
635 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
636 struct brw_reg dst,
637 struct brw_reg index,
638 struct brw_reg offset)
639 {
640 assert(inst->mlen == 0);
641
642 assert(index.file == BRW_IMMEDIATE_VALUE &&
643 index.type == BRW_REGISTER_TYPE_UD);
644 uint32_t surf_index = index.dw1.ud;
645
646 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
647 /* Reference just the dword we need, to avoid angering validate_reg(). */
648 offset = brw_vec1_grf(offset.nr, 0);
649
650 brw_push_insn_state(p);
651 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
652 brw_set_mask_control(p, BRW_MASK_DISABLE);
653 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
654 brw_pop_insn_state(p);
655
656 /* We use the SIMD4x2 mode because we want to end up with 4 components in
657 * the destination loaded consecutively from the same offset (which appears
658 * in the first component, and the rest are ignored).
659 */
660 dst.width = BRW_WIDTH_4;
661 brw_set_dest(p, send, dst);
662 brw_set_src0(p, send, offset);
663 brw_set_sampler_message(p, send,
664 surf_index,
665 0, /* LD message ignores sampler unit */
666 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
667 1, /* rlen */
668 1, /* mlen */
669 false, /* no header */
670 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
671 0);
672 }
673
674 void
675 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
676 struct brw_reg dst,
677 struct brw_reg index,
678 struct brw_reg offset)
679 {
680 assert(intel->gen < 7); /* Should use the gen7 variant. */
681 assert(inst->header_present);
682 assert(inst->mlen);
683
684 assert(index.file == BRW_IMMEDIATE_VALUE &&
685 index.type == BRW_REGISTER_TYPE_UD);
686 uint32_t surf_index = index.dw1.ud;
687
688 uint32_t simd_mode, rlen, msg_type;
689 if (dispatch_width == 16) {
690 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
691 rlen = 8;
692 } else {
693 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
694 rlen = 4;
695 }
696
697 if (intel->gen >= 5)
698 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
699 else {
700 /* We always use the SIMD16 message so that we only have to load U, and
701 * not V or R.
702 */
703 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
704 assert(inst->mlen == 3);
705 assert(inst->regs_written == 8);
706 rlen = 8;
707 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
708 }
709
710 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
711 BRW_REGISTER_TYPE_D);
712 brw_MOV(p, offset_mrf, offset);
713
714 struct brw_reg header = brw_vec8_grf(0, 0);
715 gen6_resolve_implied_move(p, &header, inst->base_mrf);
716
717 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
718 send->header.compression_control = BRW_COMPRESSION_NONE;
719 brw_set_dest(p, send, dst);
720 brw_set_src0(p, send, header);
721 if (intel->gen < 6)
722 send->header.destreg__conditionalmod = inst->base_mrf;
723
724 /* Our surface is set up as floats, regardless of what actual data is
725 * stored in it.
726 */
727 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
728 brw_set_sampler_message(p, send,
729 surf_index,
730 0, /* sampler (unused) */
731 msg_type,
732 rlen,
733 inst->mlen,
734 inst->header_present,
735 simd_mode,
736 return_format);
737 }
738
739 void
740 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
741 struct brw_reg dst,
742 struct brw_reg index,
743 struct brw_reg offset)
744 {
745 assert(intel->gen >= 7);
746 /* Varying-offset pull constant loads are treated as a normal expression on
747 * gen7, so the fact that it's a send message is hidden at the IR level.
748 */
749 assert(!inst->header_present);
750 assert(!inst->mlen);
751
752 assert(index.file == BRW_IMMEDIATE_VALUE &&
753 index.type == BRW_REGISTER_TYPE_UD);
754 uint32_t surf_index = index.dw1.ud;
755
756 uint32_t simd_mode, rlen, mlen;
757 if (dispatch_width == 16) {
758 mlen = 2;
759 rlen = 8;
760 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
761 } else {
762 mlen = 1;
763 rlen = 4;
764 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
765 }
766
767 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
768 brw_set_dest(p, send, dst);
769 brw_set_src0(p, send, offset);
770 brw_set_sampler_message(p, send,
771 surf_index,
772 0, /* LD message ignores sampler unit */
773 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
774 rlen,
775 mlen,
776 false, /* no header */
777 simd_mode,
778 0);
779 }
780
781 /**
782 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
783 * into the flags register (f0.0).
784 *
785 * Used only on Gen6 and above.
786 */
787 void
788 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
789 {
790 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
791 struct brw_reg dispatch_mask;
792
793 if (intel->gen >= 6)
794 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
795 else
796 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
797
798 brw_push_insn_state(p);
799 brw_set_mask_control(p, BRW_MASK_DISABLE);
800 brw_MOV(p, flags, dispatch_mask);
801 brw_pop_insn_state(p);
802 }
803
804
805 static uint32_t brw_file_from_reg(fs_reg *reg)
806 {
807 switch (reg->file) {
808 case ARF:
809 return BRW_ARCHITECTURE_REGISTER_FILE;
810 case GRF:
811 return BRW_GENERAL_REGISTER_FILE;
812 case MRF:
813 return BRW_MESSAGE_REGISTER_FILE;
814 case IMM:
815 return BRW_IMMEDIATE_VALUE;
816 default:
817 assert(!"not reached");
818 return BRW_GENERAL_REGISTER_FILE;
819 }
820 }
821
822 static struct brw_reg
823 brw_reg_from_fs_reg(fs_reg *reg)
824 {
825 struct brw_reg brw_reg;
826
827 switch (reg->file) {
828 case GRF:
829 case ARF:
830 case MRF:
831 if (reg->smear == -1) {
832 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
833 } else {
834 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, reg->smear);
835 }
836 brw_reg = retype(brw_reg, reg->type);
837 if (reg->sechalf)
838 brw_reg = sechalf(brw_reg);
839 break;
840 case IMM:
841 switch (reg->type) {
842 case BRW_REGISTER_TYPE_F:
843 brw_reg = brw_imm_f(reg->imm.f);
844 break;
845 case BRW_REGISTER_TYPE_D:
846 brw_reg = brw_imm_d(reg->imm.i);
847 break;
848 case BRW_REGISTER_TYPE_UD:
849 brw_reg = brw_imm_ud(reg->imm.u);
850 break;
851 default:
852 assert(!"not reached");
853 brw_reg = brw_null_reg();
854 break;
855 }
856 break;
857 case HW_REG:
858 brw_reg = reg->fixed_hw_reg;
859 break;
860 case BAD_FILE:
861 /* Probably unused. */
862 brw_reg = brw_null_reg();
863 break;
864 case UNIFORM:
865 assert(!"not reached");
866 brw_reg = brw_null_reg();
867 break;
868 default:
869 assert(!"not reached");
870 brw_reg = brw_null_reg();
871 break;
872 }
873 if (reg->abs)
874 brw_reg = brw_abs(brw_reg);
875 if (reg->negate)
876 brw_reg = negate(brw_reg);
877
878 return brw_reg;
879 }
880
881 /**
882 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
883 * sampler LD messages.
884 *
885 * We don't want to bake it into the send message's code generation because
886 * that means we don't get a chance to schedule the instructions.
887 */
888 void
889 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
890 struct brw_reg dst,
891 struct brw_reg value)
892 {
893 assert(value.file == BRW_IMMEDIATE_VALUE);
894
895 brw_push_insn_state(p);
896 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
897 brw_set_mask_control(p, BRW_MASK_DISABLE);
898 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
899 brw_pop_insn_state(p);
900 }
901
902 /**
903 * Change the register's data type from UD to W, doubling the strides in order
904 * to compensate for halving the data type width.
905 */
906 static struct brw_reg
907 ud_reg_to_w(struct brw_reg r)
908 {
909 assert(r.type == BRW_REGISTER_TYPE_UD);
910 r.type = BRW_REGISTER_TYPE_W;
911
912 /* The BRW_*_STRIDE enums are defined so that incrementing the field
913 * doubles the real stride.
914 */
915 if (r.hstride != 0)
916 ++r.hstride;
917 if (r.vstride != 0)
918 ++r.vstride;
919
920 return r;
921 }
922
923 void
924 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
925 struct brw_reg dst,
926 struct brw_reg x,
927 struct brw_reg y)
928 {
929 assert(intel->gen >= 7);
930 assert(dst.type == BRW_REGISTER_TYPE_UD);
931 assert(x.type == BRW_REGISTER_TYPE_F);
932 assert(y.type == BRW_REGISTER_TYPE_F);
933
934 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
935 *
936 * Because this instruction does not have a 16-bit floating-point type,
937 * the destination data type must be Word (W).
938 *
939 * The destination must be DWord-aligned and specify a horizontal stride
940 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
941 * each destination channel and the upper word is not modified.
942 */
943 struct brw_reg dst_w = ud_reg_to_w(dst);
944
945 /* Give each 32-bit channel of dst the form below , where "." means
946 * unchanged.
947 * 0x....hhhh
948 */
949 brw_F32TO16(p, dst_w, y);
950
951 /* Now the form:
952 * 0xhhhh0000
953 */
954 brw_SHL(p, dst, dst, brw_imm_ud(16u));
955
956 /* And, finally the form of packHalf2x16's output:
957 * 0xhhhhllll
958 */
959 brw_F32TO16(p, dst_w, x);
960 }
961
962 void
963 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
964 struct brw_reg dst,
965 struct brw_reg src)
966 {
967 assert(intel->gen >= 7);
968 assert(dst.type == BRW_REGISTER_TYPE_F);
969 assert(src.type == BRW_REGISTER_TYPE_UD);
970
971 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
972 *
973 * Because this instruction does not have a 16-bit floating-point type,
974 * the source data type must be Word (W). The destination type must be
975 * F (Float).
976 */
977 struct brw_reg src_w = ud_reg_to_w(src);
978
979 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
980 * For the Y case, we wish to access only the upper word; therefore
981 * a 16-bit subregister offset is needed.
982 */
983 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
984 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
985 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
986 src_w.subnr += 2;
987
988 brw_F16TO32(p, dst, src_w);
989 }
990
991 void
992 fs_generator::generate_shader_time_add(fs_inst *inst,
993 struct brw_reg payload,
994 struct brw_reg offset,
995 struct brw_reg value)
996 {
997 assert(intel->gen >= 7);
998 brw_push_insn_state(p);
999 brw_set_mask_control(p, true);
1000
1001 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1002 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1003 offset.type);
1004 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1005 value.type);
1006
1007 assert(offset.file == BRW_IMMEDIATE_VALUE);
1008 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1009 value.width = BRW_WIDTH_1;
1010 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1011 value.vstride = BRW_VERTICAL_STRIDE_0;
1012 } else {
1013 assert(value.file == BRW_IMMEDIATE_VALUE);
1014 }
1015
1016 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1017 * case, and we don't really care about squeezing every bit of performance
1018 * out of this path, so we just emit the MOVs from here.
1019 */
1020 brw_MOV(p, payload_offset, offset);
1021 brw_MOV(p, payload_value, value);
1022 brw_shader_time_add(p, payload, SURF_INDEX_WM_SHADER_TIME);
1023 brw_pop_insn_state(p);
1024 }
1025
1026 void
1027 fs_generator::generate_code(exec_list *instructions)
1028 {
1029 int last_native_insn_offset = p->next_insn_offset;
1030 const char *last_annotation_string = NULL;
1031 const void *last_annotation_ir = NULL;
1032
1033 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1034 if (shader) {
1035 printf("Native code for fragment shader %d (%d-wide dispatch):\n",
1036 prog->Name, dispatch_width);
1037 } else {
1038 printf("Native code for fragment program %d (%d-wide dispatch):\n",
1039 fp->Base.Id, dispatch_width);
1040 }
1041 }
1042
1043 cfg_t *cfg = NULL;
1044 if (unlikely(INTEL_DEBUG & DEBUG_WM))
1045 cfg = new(mem_ctx) cfg_t(mem_ctx, instructions);
1046
1047 foreach_list(node, instructions) {
1048 fs_inst *inst = (fs_inst *)node;
1049 struct brw_reg src[3], dst;
1050
1051 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1052 foreach_list(node, &cfg->block_list) {
1053 bblock_link *link = (bblock_link *)node;
1054 bblock_t *block = link->block;
1055
1056 if (block->start == inst) {
1057 printf(" START B%d", block->block_num);
1058 foreach_list(predecessor_node, &block->parents) {
1059 bblock_link *predecessor_link =
1060 (bblock_link *)predecessor_node;
1061 bblock_t *predecessor_block = predecessor_link->block;
1062 printf(" <-B%d", predecessor_block->block_num);
1063 }
1064 printf("\n");
1065 }
1066 }
1067
1068 if (last_annotation_ir != inst->ir) {
1069 last_annotation_ir = inst->ir;
1070 if (last_annotation_ir) {
1071 printf(" ");
1072 if (shader)
1073 ((ir_instruction *)inst->ir)->print();
1074 else {
1075 const prog_instruction *fpi;
1076 fpi = (const prog_instruction *)inst->ir;
1077 printf("%d: ", (int)(fpi - fp->Base.Instructions));
1078 _mesa_fprint_instruction_opt(stdout,
1079 fpi,
1080 0, PROG_PRINT_DEBUG, NULL);
1081 }
1082 printf("\n");
1083 }
1084 }
1085 if (last_annotation_string != inst->annotation) {
1086 last_annotation_string = inst->annotation;
1087 if (last_annotation_string)
1088 printf(" %s\n", last_annotation_string);
1089 }
1090 }
1091
1092 for (unsigned int i = 0; i < 3; i++) {
1093 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1094
1095 /* The accumulator result appears to get used for the
1096 * conditional modifier generation. When negating a UD
1097 * value, there is a 33rd bit generated for the sign in the
1098 * accumulator value, so now you can't check, for example,
1099 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1100 */
1101 assert(!inst->conditional_mod ||
1102 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1103 !inst->src[i].negate);
1104 }
1105 dst = brw_reg_from_fs_reg(&inst->dst);
1106
1107 brw_set_conditionalmod(p, inst->conditional_mod);
1108 brw_set_predicate_control(p, inst->predicate);
1109 brw_set_predicate_inverse(p, inst->predicate_inverse);
1110 brw_set_flag_reg(p, 0, inst->flag_subreg);
1111 brw_set_saturate(p, inst->saturate);
1112 brw_set_mask_control(p, inst->force_writemask_all);
1113
1114 if (inst->force_uncompressed || dispatch_width == 8) {
1115 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1116 } else if (inst->force_sechalf) {
1117 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1118 } else {
1119 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1120 }
1121
1122 switch (inst->opcode) {
1123 case BRW_OPCODE_MOV:
1124 brw_MOV(p, dst, src[0]);
1125 break;
1126 case BRW_OPCODE_ADD:
1127 brw_ADD(p, dst, src[0], src[1]);
1128 break;
1129 case BRW_OPCODE_MUL:
1130 brw_MUL(p, dst, src[0], src[1]);
1131 break;
1132 case BRW_OPCODE_MACH:
1133 brw_set_acc_write_control(p, 1);
1134 brw_MACH(p, dst, src[0], src[1]);
1135 brw_set_acc_write_control(p, 0);
1136 break;
1137
1138 case BRW_OPCODE_MAD:
1139 brw_set_access_mode(p, BRW_ALIGN_16);
1140 if (dispatch_width == 16) {
1141 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1142 brw_MAD(p, dst, src[0], src[1], src[2]);
1143 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1144 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1145 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1146 } else {
1147 brw_MAD(p, dst, src[0], src[1], src[2]);
1148 }
1149 brw_set_access_mode(p, BRW_ALIGN_1);
1150 break;
1151
1152 case BRW_OPCODE_LRP:
1153 brw_set_access_mode(p, BRW_ALIGN_16);
1154 if (dispatch_width == 16) {
1155 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1156 brw_LRP(p, dst, src[0], src[1], src[2]);
1157 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1158 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1159 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1160 } else {
1161 brw_LRP(p, dst, src[0], src[1], src[2]);
1162 }
1163 brw_set_access_mode(p, BRW_ALIGN_1);
1164 break;
1165
1166 case BRW_OPCODE_FRC:
1167 brw_FRC(p, dst, src[0]);
1168 break;
1169 case BRW_OPCODE_RNDD:
1170 brw_RNDD(p, dst, src[0]);
1171 break;
1172 case BRW_OPCODE_RNDE:
1173 brw_RNDE(p, dst, src[0]);
1174 break;
1175 case BRW_OPCODE_RNDZ:
1176 brw_RNDZ(p, dst, src[0]);
1177 break;
1178
1179 case BRW_OPCODE_AND:
1180 brw_AND(p, dst, src[0], src[1]);
1181 break;
1182 case BRW_OPCODE_OR:
1183 brw_OR(p, dst, src[0], src[1]);
1184 break;
1185 case BRW_OPCODE_XOR:
1186 brw_XOR(p, dst, src[0], src[1]);
1187 break;
1188 case BRW_OPCODE_NOT:
1189 brw_NOT(p, dst, src[0]);
1190 break;
1191 case BRW_OPCODE_ASR:
1192 brw_ASR(p, dst, src[0], src[1]);
1193 break;
1194 case BRW_OPCODE_SHR:
1195 brw_SHR(p, dst, src[0], src[1]);
1196 break;
1197 case BRW_OPCODE_SHL:
1198 brw_SHL(p, dst, src[0], src[1]);
1199 break;
1200 case BRW_OPCODE_F32TO16:
1201 brw_F32TO16(p, dst, src[0]);
1202 break;
1203 case BRW_OPCODE_F16TO32:
1204 brw_F16TO32(p, dst, src[0]);
1205 break;
1206 case BRW_OPCODE_CMP:
1207 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1208 break;
1209 case BRW_OPCODE_SEL:
1210 brw_SEL(p, dst, src[0], src[1]);
1211 break;
1212
1213 case BRW_OPCODE_IF:
1214 if (inst->src[0].file != BAD_FILE) {
1215 /* The instruction has an embedded compare (only allowed on gen6) */
1216 assert(intel->gen == 6);
1217 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1218 } else {
1219 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1220 }
1221 break;
1222
1223 case BRW_OPCODE_ELSE:
1224 brw_ELSE(p);
1225 break;
1226 case BRW_OPCODE_ENDIF:
1227 brw_ENDIF(p);
1228 break;
1229
1230 case BRW_OPCODE_DO:
1231 brw_DO(p, BRW_EXECUTE_8);
1232 break;
1233
1234 case BRW_OPCODE_BREAK:
1235 brw_BREAK(p);
1236 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1237 break;
1238 case BRW_OPCODE_CONTINUE:
1239 /* FINISHME: We need to write the loop instruction support still. */
1240 if (intel->gen >= 6)
1241 gen6_CONT(p);
1242 else
1243 brw_CONT(p);
1244 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1245 break;
1246
1247 case BRW_OPCODE_WHILE:
1248 brw_WHILE(p);
1249 break;
1250
1251 case SHADER_OPCODE_RCP:
1252 case SHADER_OPCODE_RSQ:
1253 case SHADER_OPCODE_SQRT:
1254 case SHADER_OPCODE_EXP2:
1255 case SHADER_OPCODE_LOG2:
1256 case SHADER_OPCODE_SIN:
1257 case SHADER_OPCODE_COS:
1258 if (intel->gen >= 7) {
1259 generate_math1_gen7(inst, dst, src[0]);
1260 } else if (intel->gen == 6) {
1261 generate_math1_gen6(inst, dst, src[0]);
1262 } else {
1263 generate_math_gen4(inst, dst, src[0]);
1264 }
1265 break;
1266 case SHADER_OPCODE_INT_QUOTIENT:
1267 case SHADER_OPCODE_INT_REMAINDER:
1268 case SHADER_OPCODE_POW:
1269 if (intel->gen >= 7) {
1270 generate_math2_gen7(inst, dst, src[0], src[1]);
1271 } else if (intel->gen == 6) {
1272 generate_math2_gen6(inst, dst, src[0], src[1]);
1273 } else {
1274 generate_math_gen4(inst, dst, src[0]);
1275 }
1276 break;
1277 case FS_OPCODE_PIXEL_X:
1278 generate_pixel_xy(dst, true);
1279 break;
1280 case FS_OPCODE_PIXEL_Y:
1281 generate_pixel_xy(dst, false);
1282 break;
1283 case FS_OPCODE_CINTERP:
1284 brw_MOV(p, dst, src[0]);
1285 break;
1286 case FS_OPCODE_LINTERP:
1287 generate_linterp(inst, dst, src);
1288 break;
1289 case SHADER_OPCODE_TEX:
1290 case FS_OPCODE_TXB:
1291 case SHADER_OPCODE_TXD:
1292 case SHADER_OPCODE_TXF:
1293 case SHADER_OPCODE_TXF_MS:
1294 case SHADER_OPCODE_TXL:
1295 case SHADER_OPCODE_TXS:
1296 case SHADER_OPCODE_LOD:
1297 generate_tex(inst, dst, src[0]);
1298 break;
1299 case FS_OPCODE_DDX:
1300 generate_ddx(inst, dst, src[0]);
1301 break;
1302 case FS_OPCODE_DDY:
1303 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1304 * guarantee that c->key.render_to_fbo is set).
1305 */
1306 assert(fp->UsesDFdy);
1307 generate_ddy(inst, dst, src[0], c->key.render_to_fbo);
1308 break;
1309
1310 case FS_OPCODE_SPILL:
1311 generate_spill(inst, src[0]);
1312 break;
1313
1314 case FS_OPCODE_UNSPILL:
1315 generate_unspill(inst, dst);
1316 break;
1317
1318 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1319 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1320 break;
1321
1322 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1323 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1324 break;
1325
1326 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1327 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1328 break;
1329
1330 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1331 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1332 break;
1333
1334 case FS_OPCODE_FB_WRITE:
1335 generate_fb_write(inst);
1336 break;
1337
1338 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1339 generate_mov_dispatch_to_flags(inst);
1340 break;
1341
1342 case FS_OPCODE_DISCARD_JUMP:
1343 generate_discard_jump(inst);
1344 break;
1345
1346 case SHADER_OPCODE_SHADER_TIME_ADD:
1347 generate_shader_time_add(inst, src[0], src[1], src[2]);
1348 break;
1349
1350 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1351 generate_set_simd4x2_offset(inst, dst, src[0]);
1352 break;
1353
1354 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1355 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1356 break;
1357
1358 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1359 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1360 generate_unpack_half_2x16_split(inst, dst, src[0]);
1361 break;
1362
1363 case FS_OPCODE_PLACEHOLDER_HALT:
1364 /* This is the place where the final HALT needs to be inserted if
1365 * we've emitted any discards. If not, this will emit no code.
1366 */
1367 patch_discard_jumps_to_fb_writes();
1368 break;
1369
1370 default:
1371 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1372 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1373 opcode_descs[inst->opcode].name);
1374 } else {
1375 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1376 }
1377 abort();
1378 }
1379
1380 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1381 brw_dump_compile(p, stdout,
1382 last_native_insn_offset, p->next_insn_offset);
1383
1384 foreach_list(node, &cfg->block_list) {
1385 bblock_link *link = (bblock_link *)node;
1386 bblock_t *block = link->block;
1387
1388 if (block->end == inst) {
1389 printf(" END B%d", block->block_num);
1390 foreach_list(successor_node, &block->children) {
1391 bblock_link *successor_link =
1392 (bblock_link *)successor_node;
1393 bblock_t *successor_block = successor_link->block;
1394 printf(" ->B%d", successor_block->block_num);
1395 }
1396 printf("\n");
1397 }
1398 }
1399 }
1400
1401 last_native_insn_offset = p->next_insn_offset;
1402 }
1403
1404 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1405 printf("\n");
1406 }
1407
1408 brw_set_uip_jip(p);
1409
1410 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
1411 * emit issues, it doesn't get the jump distances into the output,
1412 * which is often something we want to debug. So this is here in
1413 * case you're doing that.
1414 */
1415 if (0) {
1416 brw_dump_compile(p, stdout, 0, p->next_insn_offset);
1417 }
1418 }
1419
1420 const unsigned *
1421 fs_generator::generate_assembly(exec_list *simd8_instructions,
1422 exec_list *simd16_instructions,
1423 unsigned *assembly_size)
1424 {
1425 dispatch_width = 8;
1426 generate_code(simd8_instructions);
1427
1428 if (simd16_instructions) {
1429 /* We have to do a compaction pass now, or the one at the end of
1430 * execution will squash down where our prog_offset start needs
1431 * to be.
1432 */
1433 brw_compact_instructions(p);
1434
1435 /* align to 64 byte boundary. */
1436 while ((p->nr_insn * sizeof(struct brw_instruction)) % 64) {
1437 brw_NOP(p);
1438 }
1439
1440 /* Save off the start of this 16-wide program */
1441 c->prog_data.prog_offset_16 = p->nr_insn * sizeof(struct brw_instruction);
1442
1443 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1444
1445 dispatch_width = 16;
1446 generate_code(simd16_instructions);
1447 }
1448
1449 return brw_get_program(p, assembly_size);
1450 }