2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_emit.cpp
26 * This file supports emitting code from the FS LIR to the actual
27 * native instructions.
31 #include "main/macros.h"
32 #include "brw_context.h"
38 #include "glsl/ir_print_visitor.h"
40 fs_generator::fs_generator(struct brw_context
*brw
,
41 struct brw_wm_compile
*c
,
42 struct gl_shader_program
*prog
,
43 struct gl_fragment_program
*fp
,
44 bool dual_source_output
)
46 : brw(brw
), c(c
), prog(prog
), fp(fp
), dual_source_output(dual_source_output
)
51 shader
= prog
? prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
] : NULL
;
55 p
= rzalloc(mem_ctx
, struct brw_compile
);
56 brw_init_compile(brw
, p
, mem_ctx
);
59 fs_generator::~fs_generator()
64 fs_generator::patch_discard_jumps_to_fb_writes()
66 if (intel
->gen
< 6 || this->discard_halt_patches
.is_empty())
69 /* There is a somewhat strange undocumented requirement of using
70 * HALT, according to the simulator. If some channel has HALTed to
71 * a particular UIP, then by the end of the program, every channel
72 * must have HALTed to that UIP. Furthermore, the tracking is a
73 * stack, so you can't do the final halt of a UIP after starting
74 * halting to a new UIP.
76 * Symptoms of not emitting this instruction on actual hardware
77 * included GPU hangs and sparkly rendering on the piglit discard
80 struct brw_instruction
*last_halt
= gen6_HALT(p
);
81 last_halt
->bits3
.break_cont
.uip
= 2;
82 last_halt
->bits3
.break_cont
.jip
= 2;
86 foreach_list(node
, &this->discard_halt_patches
) {
87 ip_record
*patch_ip
= (ip_record
*)node
;
88 struct brw_instruction
*patch
= &p
->store
[patch_ip
->ip
];
90 assert(patch
->header
.opcode
== BRW_OPCODE_HALT
);
91 /* HALT takes a half-instruction distance from the pre-incremented IP. */
92 patch
->bits3
.break_cont
.uip
= (ip
- patch_ip
->ip
) * 2;
95 this->discard_halt_patches
.make_empty();
99 fs_generator::generate_fb_write(fs_inst
*inst
)
101 bool eot
= inst
->eot
;
102 struct brw_reg implied_header
;
103 uint32_t msg_control
;
105 /* Note that the jumps emitted to this point mean that the g0 ->
106 * base_mrf setup must be inside of this function, so that we jump
107 * to a point containing it.
109 patch_discard_jumps_to_fb_writes();
111 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
114 brw_push_insn_state(p
);
115 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
116 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
119 struct brw_reg pixel_mask
;
122 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
124 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
126 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
129 if (inst
->header_present
) {
130 if (intel
->gen
>= 6) {
131 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
133 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
),
134 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
135 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
137 if (inst
->target
> 0 &&
138 c
->key
.nr_color_regions
> 1 &&
139 c
->key
.sample_alpha_to_coverage
) {
140 /* Set "Source0 Alpha Present to RenderTarget" bit in message
144 vec1(retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
)),
145 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
146 brw_imm_ud(0x1 << 11));
149 if (inst
->target
> 0) {
150 /* Set the render target index for choosing BLEND_STATE. */
151 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
,
153 BRW_REGISTER_TYPE_UD
),
154 brw_imm_ud(inst
->target
));
157 implied_header
= brw_null_reg();
159 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
162 brw_message_reg(inst
->base_mrf
+ 1),
166 implied_header
= brw_null_reg();
169 if (this->dual_source_output
)
170 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
171 else if (dispatch_width
== 16)
172 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
174 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
176 brw_pop_insn_state(p
);
187 inst
->header_present
);
190 /* Computes the integer pixel x,y values from the origin.
192 * This is the basis of gl_FragCoord computation, but is also used
193 * pre-gen6 for computing the deltas from v0 for computing
197 fs_generator::generate_pixel_xy(struct brw_reg dst
, bool is_x
)
199 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
201 struct brw_reg deltas
;
204 src
= stride(suboffset(g1_uw
, 4), 2, 4, 0);
205 deltas
= brw_imm_v(0x10101010);
207 src
= stride(suboffset(g1_uw
, 5), 2, 4, 0);
208 deltas
= brw_imm_v(0x11001100);
211 if (dispatch_width
== 16) {
215 /* We do this 8 or 16-wide, but since the destination is UW we
216 * don't do compression in the 16-wide case.
218 brw_push_insn_state(p
);
219 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
220 brw_ADD(p
, dst
, src
, deltas
);
221 brw_pop_insn_state(p
);
225 fs_generator::generate_linterp(fs_inst
*inst
,
226 struct brw_reg dst
, struct brw_reg
*src
)
228 struct brw_reg delta_x
= src
[0];
229 struct brw_reg delta_y
= src
[1];
230 struct brw_reg interp
= src
[2];
233 delta_y
.nr
== delta_x
.nr
+ 1 &&
234 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
235 brw_PLN(p
, dst
, interp
, delta_x
);
237 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
238 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
243 fs_generator::generate_math1_gen7(fs_inst
*inst
,
247 assert(inst
->mlen
== 0);
249 brw_math_function(inst
->opcode
),
251 BRW_MATH_DATA_VECTOR
,
252 BRW_MATH_PRECISION_FULL
);
256 fs_generator::generate_math2_gen7(fs_inst
*inst
,
261 assert(inst
->mlen
== 0);
262 brw_math2(p
, dst
, brw_math_function(inst
->opcode
), src0
, src1
);
266 fs_generator::generate_math1_gen6(fs_inst
*inst
,
270 int op
= brw_math_function(inst
->opcode
);
272 assert(inst
->mlen
== 0);
274 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
278 BRW_MATH_DATA_VECTOR
,
279 BRW_MATH_PRECISION_FULL
);
281 if (dispatch_width
== 16) {
282 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
283 brw_math(p
, sechalf(dst
),
286 BRW_MATH_DATA_VECTOR
,
287 BRW_MATH_PRECISION_FULL
);
288 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
293 fs_generator::generate_math2_gen6(fs_inst
*inst
,
298 int op
= brw_math_function(inst
->opcode
);
300 assert(inst
->mlen
== 0);
302 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
303 brw_math2(p
, dst
, op
, src0
, src1
);
305 if (dispatch_width
== 16) {
306 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
307 brw_math2(p
, sechalf(dst
), op
, sechalf(src0
), sechalf(src1
));
308 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
313 fs_generator::generate_math_gen4(fs_inst
*inst
,
317 int op
= brw_math_function(inst
->opcode
);
319 assert(inst
->mlen
>= 1);
321 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
325 BRW_MATH_DATA_VECTOR
,
326 BRW_MATH_PRECISION_FULL
);
328 if (dispatch_width
== 16) {
329 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
330 brw_math(p
, sechalf(dst
),
332 inst
->base_mrf
+ 1, sechalf(src
),
333 BRW_MATH_DATA_VECTOR
,
334 BRW_MATH_PRECISION_FULL
);
336 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
341 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
345 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
346 uint32_t return_format
;
349 case BRW_REGISTER_TYPE_D
:
350 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
352 case BRW_REGISTER_TYPE_UD
:
353 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
356 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
360 if (dispatch_width
== 16)
361 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
363 if (intel
->gen
>= 5) {
364 switch (inst
->opcode
) {
365 case SHADER_OPCODE_TEX
:
366 if (inst
->shadow_compare
) {
367 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
369 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
373 if (inst
->shadow_compare
) {
374 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
376 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
379 case SHADER_OPCODE_TXL
:
380 if (inst
->shadow_compare
) {
381 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
383 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
386 case SHADER_OPCODE_TXS
:
387 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
389 case SHADER_OPCODE_TXD
:
390 if (inst
->shadow_compare
) {
391 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
392 assert(intel
->is_haswell
);
393 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
395 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
398 case SHADER_OPCODE_TXF
:
399 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
401 case SHADER_OPCODE_TXF_MS
:
403 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
405 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
407 case SHADER_OPCODE_LOD
:
408 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
411 assert(!"not reached");
415 switch (inst
->opcode
) {
416 case SHADER_OPCODE_TEX
:
417 /* Note that G45 and older determines shadow compare and dispatch width
418 * from message length for most messages.
420 assert(dispatch_width
== 8);
421 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
422 if (inst
->shadow_compare
) {
423 assert(inst
->mlen
== 6);
425 assert(inst
->mlen
<= 4);
429 if (inst
->shadow_compare
) {
430 assert(inst
->mlen
== 6);
431 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
433 assert(inst
->mlen
== 9);
434 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
435 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
438 case SHADER_OPCODE_TXL
:
439 if (inst
->shadow_compare
) {
440 assert(inst
->mlen
== 6);
441 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
443 assert(inst
->mlen
== 9);
444 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
445 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
448 case SHADER_OPCODE_TXD
:
449 /* There is no sample_d_c message; comparisons are done manually */
450 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
451 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
453 case SHADER_OPCODE_TXF
:
454 assert(inst
->mlen
== 9);
455 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
456 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
458 case SHADER_OPCODE_TXS
:
459 assert(inst
->mlen
== 3);
460 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
461 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
464 assert(!"not reached");
468 assert(msg_type
!= -1);
470 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
475 /* Load the message header if present. If there's a texture offset,
476 * we need to set it up explicitly and load the offset bitfield.
477 * Otherwise, we can use an implied move from g0 to the first message reg.
479 if (inst
->texture_offset
) {
480 brw_push_insn_state(p
);
481 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
482 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
483 /* Explicitly set up the message header by copying g0 to the MRF. */
484 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
),
485 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
487 /* Then set the offset bits in DWord 2. */
488 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
,
489 inst
->base_mrf
, 2), BRW_REGISTER_TYPE_UD
),
490 brw_imm_ud(inst
->texture_offset
));
491 brw_pop_insn_state(p
);
492 } else if (inst
->header_present
) {
493 /* Set up an implied move from g0 to the MRF. */
494 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
498 retype(dst
, BRW_REGISTER_TYPE_UW
),
501 SURF_INDEX_TEXTURE(inst
->sampler
),
506 inst
->header_present
,
512 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
515 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
517 * and we're trying to produce:
520 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
521 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
522 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
523 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
524 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
525 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
526 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
527 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
529 * and add another set of two more subspans if in 16-pixel dispatch mode.
531 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
532 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
533 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
534 * between each other. We could probably do it like ddx and swizzle the right
535 * order later, but bail for now and just produce
536 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
539 fs_generator::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
541 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
543 BRW_VERTICAL_STRIDE_2
,
545 BRW_HORIZONTAL_STRIDE_0
,
546 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
547 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
549 BRW_VERTICAL_STRIDE_2
,
551 BRW_HORIZONTAL_STRIDE_0
,
552 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
553 brw_ADD(p
, dst
, src0
, negate(src1
));
556 /* The negate_value boolean is used to negate the derivative computation for
557 * FBOs, since they place the origin at the upper left instead of the lower
561 fs_generator::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
564 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
566 BRW_VERTICAL_STRIDE_4
,
568 BRW_HORIZONTAL_STRIDE_0
,
569 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
570 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
572 BRW_VERTICAL_STRIDE_4
,
574 BRW_HORIZONTAL_STRIDE_0
,
575 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
577 brw_ADD(p
, dst
, src1
, negate(src0
));
579 brw_ADD(p
, dst
, src0
, negate(src1
));
583 fs_generator::generate_discard_jump(fs_inst
*inst
)
585 assert(intel
->gen
>= 6);
587 /* This HALT will be patched up at FB write time to point UIP at the end of
588 * the program, and at brw_uip_jip() JIP will be set to the end of the
589 * current block (or the program).
591 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
593 brw_push_insn_state(p
);
594 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
596 brw_pop_insn_state(p
);
600 fs_generator::generate_spill(fs_inst
*inst
, struct brw_reg src
)
602 assert(inst
->mlen
!= 0);
605 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
606 retype(src
, BRW_REGISTER_TYPE_UD
));
607 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
), 1,
612 fs_generator::generate_unspill(fs_inst
*inst
, struct brw_reg dst
)
614 assert(inst
->mlen
!= 0);
616 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
), 1,
621 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
623 struct brw_reg index
,
624 struct brw_reg offset
)
626 assert(inst
->mlen
!= 0);
628 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
629 index
.type
== BRW_REGISTER_TYPE_UD
);
630 uint32_t surf_index
= index
.dw1
.ud
;
632 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
633 offset
.type
== BRW_REGISTER_TYPE_UD
);
634 uint32_t read_offset
= offset
.dw1
.ud
;
636 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
637 read_offset
, surf_index
);
641 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
643 struct brw_reg index
,
644 struct brw_reg offset
)
646 assert(inst
->mlen
== 0);
648 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
649 index
.type
== BRW_REGISTER_TYPE_UD
);
650 uint32_t surf_index
= index
.dw1
.ud
;
652 assert(offset
.file
== BRW_GENERAL_REGISTER_FILE
);
653 /* Reference just the dword we need, to avoid angering validate_reg(). */
654 offset
= brw_vec1_grf(offset
.nr
, 0);
656 brw_push_insn_state(p
);
657 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
658 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
659 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
660 brw_pop_insn_state(p
);
662 /* We use the SIMD4x2 mode because we want to end up with 4 components in
663 * the destination loaded consecutively from the same offset (which appears
664 * in the first component, and the rest are ignored).
666 dst
.width
= BRW_WIDTH_4
;
667 brw_set_dest(p
, send
, dst
);
668 brw_set_src0(p
, send
, offset
);
669 brw_set_sampler_message(p
, send
,
671 0, /* LD message ignores sampler unit */
672 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
675 false, /* no header */
676 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
681 fs_generator::generate_varying_pull_constant_load(fs_inst
*inst
,
683 struct brw_reg index
)
685 assert(intel
->gen
< 7); /* Should use the gen7 variant. */
686 assert(inst
->header_present
);
688 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
689 index
.type
== BRW_REGISTER_TYPE_UD
);
690 uint32_t surf_index
= index
.dw1
.ud
;
692 uint32_t msg_type
, msg_control
, rlen
;
694 msg_type
= GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ
;
695 else if (intel
->gen
== 5 || intel
->is_g4x
)
696 msg_type
= G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ
;
698 msg_type
= BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ
;
700 if (dispatch_width
== 16) {
701 msg_control
= BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS
;
704 msg_control
= BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS
;
708 struct brw_reg header
= brw_vec8_grf(0, 0);
709 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
711 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
712 brw_set_dest(p
, send
, dst
);
713 brw_set_src0(p
, send
, header
);
715 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
716 brw_set_dp_read_message(p
, send
,
720 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
722 inst
->header_present
,
727 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
729 struct brw_reg index
,
730 struct brw_reg offset
)
732 assert(intel
->gen
>= 7);
733 /* Varying-offset pull constant loads are treated as a normal expression on
734 * gen7, so the fact that it's a send message is hidden at the IR level.
736 assert(!inst
->header_present
);
739 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
740 index
.type
== BRW_REGISTER_TYPE_UD
);
741 uint32_t surf_index
= index
.dw1
.ud
;
743 uint32_t msg_control
, rlen
, mlen
;
744 if (dispatch_width
== 16) {
745 msg_control
= BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS
;
748 msg_control
= BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS
;
752 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
753 brw_set_dest(p
, send
, dst
);
754 brw_set_src0(p
, send
, offset
);
756 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
757 brw_set_dp_read_message(p
, send
,
760 GEN7_DATAPORT_DC_DWORD_SCATTERED_READ
,
761 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
763 inst
->header_present
,
768 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
769 * into the flags register (f0.0).
771 * Used only on Gen6 and above.
774 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
776 struct brw_reg flags
= brw_flag_reg(0, inst
->flag_subreg
);
777 struct brw_reg dispatch_mask
;
780 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
782 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
784 brw_push_insn_state(p
);
785 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
786 brw_MOV(p
, flags
, dispatch_mask
);
787 brw_pop_insn_state(p
);
791 static uint32_t brw_file_from_reg(fs_reg
*reg
)
795 return BRW_ARCHITECTURE_REGISTER_FILE
;
797 return BRW_GENERAL_REGISTER_FILE
;
799 return BRW_MESSAGE_REGISTER_FILE
;
801 return BRW_IMMEDIATE_VALUE
;
803 assert(!"not reached");
804 return BRW_GENERAL_REGISTER_FILE
;
808 static struct brw_reg
809 brw_reg_from_fs_reg(fs_reg
*reg
)
811 struct brw_reg brw_reg
;
817 if (reg
->smear
== -1) {
818 brw_reg
= brw_vec8_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
820 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->reg
, reg
->smear
);
822 brw_reg
= retype(brw_reg
, reg
->type
);
824 brw_reg
= sechalf(brw_reg
);
828 case BRW_REGISTER_TYPE_F
:
829 brw_reg
= brw_imm_f(reg
->imm
.f
);
831 case BRW_REGISTER_TYPE_D
:
832 brw_reg
= brw_imm_d(reg
->imm
.i
);
834 case BRW_REGISTER_TYPE_UD
:
835 brw_reg
= brw_imm_ud(reg
->imm
.u
);
838 assert(!"not reached");
839 brw_reg
= brw_null_reg();
844 brw_reg
= reg
->fixed_hw_reg
;
847 /* Probably unused. */
848 brw_reg
= brw_null_reg();
851 assert(!"not reached");
852 brw_reg
= brw_null_reg();
855 assert(!"not reached");
856 brw_reg
= brw_null_reg();
860 brw_reg
= brw_abs(brw_reg
);
862 brw_reg
= negate(brw_reg
);
868 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
869 * sampler LD messages.
871 * We don't want to bake it into the send message's code generation because
872 * that means we don't get a chance to schedule the instructions.
875 fs_generator::generate_set_simd4x2_offset(fs_inst
*inst
,
877 struct brw_reg value
)
879 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
881 brw_push_insn_state(p
);
882 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
883 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
884 brw_MOV(p
, retype(brw_vec1_reg(dst
.file
, dst
.nr
, 0), value
.type
), value
);
885 brw_pop_insn_state(p
);
889 * Change the register's data type from UD to W, doubling the strides in order
890 * to compensate for halving the data type width.
892 static struct brw_reg
893 ud_reg_to_w(struct brw_reg r
)
895 assert(r
.type
== BRW_REGISTER_TYPE_UD
);
896 r
.type
= BRW_REGISTER_TYPE_W
;
898 /* The BRW_*_STRIDE enums are defined so that incrementing the field
899 * doubles the real stride.
910 fs_generator::generate_pack_half_2x16_split(fs_inst
*inst
,
915 assert(intel
->gen
>= 7);
916 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
917 assert(x
.type
== BRW_REGISTER_TYPE_F
);
918 assert(y
.type
== BRW_REGISTER_TYPE_F
);
920 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
922 * Because this instruction does not have a 16-bit floating-point type,
923 * the destination data type must be Word (W).
925 * The destination must be DWord-aligned and specify a horizontal stride
926 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
927 * each destination channel and the upper word is not modified.
929 struct brw_reg dst_w
= ud_reg_to_w(dst
);
931 /* Give each 32-bit channel of dst the form below , where "." means
935 brw_F32TO16(p
, dst_w
, y
);
940 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
942 /* And, finally the form of packHalf2x16's output:
945 brw_F32TO16(p
, dst_w
, x
);
949 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
953 assert(intel
->gen
>= 7);
954 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
955 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
957 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
959 * Because this instruction does not have a 16-bit floating-point type,
960 * the source data type must be Word (W). The destination type must be
963 struct brw_reg src_w
= ud_reg_to_w(src
);
965 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
966 * For the Y case, we wish to access only the upper word; therefore
967 * a 16-bit subregister offset is needed.
969 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
970 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
971 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
974 brw_F16TO32(p
, dst
, src_w
);
978 fs_generator::generate_shader_time_add(fs_inst
*inst
,
979 struct brw_reg payload
,
980 struct brw_reg offset
,
981 struct brw_reg value
)
983 assert(intel
->gen
>= 7);
984 brw_push_insn_state(p
);
985 brw_set_mask_control(p
, true);
987 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
988 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
990 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
993 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
994 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
995 value
.width
= BRW_WIDTH_1
;
996 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
997 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
999 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1002 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1003 * case, and we don't really care about squeezing every bit of performance
1004 * out of this path, so we just emit the MOVs from here.
1006 brw_MOV(p
, payload_offset
, offset
);
1007 brw_MOV(p
, payload_value
, value
);
1008 brw_shader_time_add(p
, payload
, SURF_INDEX_WM_SHADER_TIME
);
1009 brw_pop_insn_state(p
);
1013 fs_generator::generate_code(exec_list
*instructions
)
1015 int last_native_insn_offset
= p
->next_insn_offset
;
1016 const char *last_annotation_string
= NULL
;
1017 const void *last_annotation_ir
= NULL
;
1019 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1021 printf("Native code for fragment shader %d (%d-wide dispatch):\n",
1022 prog
->Name
, dispatch_width
);
1024 printf("Native code for fragment program %d (%d-wide dispatch):\n",
1025 fp
->Base
.Id
, dispatch_width
);
1030 if (unlikely(INTEL_DEBUG
& DEBUG_WM
))
1031 cfg
= new(mem_ctx
) cfg_t(mem_ctx
, instructions
);
1033 foreach_list(node
, instructions
) {
1034 fs_inst
*inst
= (fs_inst
*)node
;
1035 struct brw_reg src
[3], dst
;
1037 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1038 foreach_list(node
, &cfg
->block_list
) {
1039 bblock_link
*link
= (bblock_link
*)node
;
1040 bblock_t
*block
= link
->block
;
1042 if (block
->start
== inst
) {
1043 printf(" START B%d", block
->block_num
);
1044 foreach_list(predecessor_node
, &block
->parents
) {
1045 bblock_link
*predecessor_link
=
1046 (bblock_link
*)predecessor_node
;
1047 bblock_t
*predecessor_block
= predecessor_link
->block
;
1048 printf(" <-B%d", predecessor_block
->block_num
);
1054 if (last_annotation_ir
!= inst
->ir
) {
1055 last_annotation_ir
= inst
->ir
;
1056 if (last_annotation_ir
) {
1059 ((ir_instruction
*)inst
->ir
)->print();
1061 const prog_instruction
*fpi
;
1062 fpi
= (const prog_instruction
*)inst
->ir
;
1063 printf("%d: ", (int)(fpi
- fp
->Base
.Instructions
));
1064 _mesa_fprint_instruction_opt(stdout
,
1066 0, PROG_PRINT_DEBUG
, NULL
);
1071 if (last_annotation_string
!= inst
->annotation
) {
1072 last_annotation_string
= inst
->annotation
;
1073 if (last_annotation_string
)
1074 printf(" %s\n", last_annotation_string
);
1078 for (unsigned int i
= 0; i
< 3; i
++) {
1079 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
1081 /* The accumulator result appears to get used for the
1082 * conditional modifier generation. When negating a UD
1083 * value, there is a 33rd bit generated for the sign in the
1084 * accumulator value, so now you can't check, for example,
1085 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1087 assert(!inst
->conditional_mod
||
1088 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1089 !inst
->src
[i
].negate
);
1091 dst
= brw_reg_from_fs_reg(&inst
->dst
);
1093 brw_set_conditionalmod(p
, inst
->conditional_mod
);
1094 brw_set_predicate_control(p
, inst
->predicate
);
1095 brw_set_predicate_inverse(p
, inst
->predicate_inverse
);
1096 brw_set_flag_reg(p
, 0, inst
->flag_subreg
);
1097 brw_set_saturate(p
, inst
->saturate
);
1098 brw_set_mask_control(p
, inst
->force_writemask_all
);
1100 if (inst
->force_uncompressed
|| dispatch_width
== 8) {
1101 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1102 } else if (inst
->force_sechalf
) {
1103 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1105 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1108 switch (inst
->opcode
) {
1109 case BRW_OPCODE_MOV
:
1110 brw_MOV(p
, dst
, src
[0]);
1112 case BRW_OPCODE_ADD
:
1113 brw_ADD(p
, dst
, src
[0], src
[1]);
1115 case BRW_OPCODE_MUL
:
1116 brw_MUL(p
, dst
, src
[0], src
[1]);
1118 case BRW_OPCODE_MACH
:
1119 brw_set_acc_write_control(p
, 1);
1120 brw_MACH(p
, dst
, src
[0], src
[1]);
1121 brw_set_acc_write_control(p
, 0);
1124 case BRW_OPCODE_MAD
:
1125 brw_set_access_mode(p
, BRW_ALIGN_16
);
1126 if (dispatch_width
== 16) {
1127 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1128 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1129 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1130 brw_MAD(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1131 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1133 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1135 brw_set_access_mode(p
, BRW_ALIGN_1
);
1138 case BRW_OPCODE_LRP
:
1139 brw_set_access_mode(p
, BRW_ALIGN_16
);
1140 if (dispatch_width
== 16) {
1141 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1142 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1143 brw_set_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1144 brw_LRP(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1145 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1147 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1149 brw_set_access_mode(p
, BRW_ALIGN_1
);
1152 case BRW_OPCODE_FRC
:
1153 brw_FRC(p
, dst
, src
[0]);
1155 case BRW_OPCODE_RNDD
:
1156 brw_RNDD(p
, dst
, src
[0]);
1158 case BRW_OPCODE_RNDE
:
1159 brw_RNDE(p
, dst
, src
[0]);
1161 case BRW_OPCODE_RNDZ
:
1162 brw_RNDZ(p
, dst
, src
[0]);
1165 case BRW_OPCODE_AND
:
1166 brw_AND(p
, dst
, src
[0], src
[1]);
1169 brw_OR(p
, dst
, src
[0], src
[1]);
1171 case BRW_OPCODE_XOR
:
1172 brw_XOR(p
, dst
, src
[0], src
[1]);
1174 case BRW_OPCODE_NOT
:
1175 brw_NOT(p
, dst
, src
[0]);
1177 case BRW_OPCODE_ASR
:
1178 brw_ASR(p
, dst
, src
[0], src
[1]);
1180 case BRW_OPCODE_SHR
:
1181 brw_SHR(p
, dst
, src
[0], src
[1]);
1183 case BRW_OPCODE_SHL
:
1184 brw_SHL(p
, dst
, src
[0], src
[1]);
1186 case BRW_OPCODE_F32TO16
:
1187 brw_F32TO16(p
, dst
, src
[0]);
1189 case BRW_OPCODE_F16TO32
:
1190 brw_F16TO32(p
, dst
, src
[0]);
1192 case BRW_OPCODE_CMP
:
1193 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1195 case BRW_OPCODE_SEL
:
1196 brw_SEL(p
, dst
, src
[0], src
[1]);
1200 if (inst
->src
[0].file
!= BAD_FILE
) {
1201 /* The instruction has an embedded compare (only allowed on gen6) */
1202 assert(intel
->gen
== 6);
1203 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1205 brw_IF(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
1209 case BRW_OPCODE_ELSE
:
1212 case BRW_OPCODE_ENDIF
:
1217 brw_DO(p
, BRW_EXECUTE_8
);
1220 case BRW_OPCODE_BREAK
:
1222 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1224 case BRW_OPCODE_CONTINUE
:
1225 /* FINISHME: We need to write the loop instruction support still. */
1226 if (intel
->gen
>= 6)
1230 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1233 case BRW_OPCODE_WHILE
:
1237 case SHADER_OPCODE_RCP
:
1238 case SHADER_OPCODE_RSQ
:
1239 case SHADER_OPCODE_SQRT
:
1240 case SHADER_OPCODE_EXP2
:
1241 case SHADER_OPCODE_LOG2
:
1242 case SHADER_OPCODE_SIN
:
1243 case SHADER_OPCODE_COS
:
1244 if (intel
->gen
>= 7) {
1245 generate_math1_gen7(inst
, dst
, src
[0]);
1246 } else if (intel
->gen
== 6) {
1247 generate_math1_gen6(inst
, dst
, src
[0]);
1249 generate_math_gen4(inst
, dst
, src
[0]);
1252 case SHADER_OPCODE_INT_QUOTIENT
:
1253 case SHADER_OPCODE_INT_REMAINDER
:
1254 case SHADER_OPCODE_POW
:
1255 if (intel
->gen
>= 7) {
1256 generate_math2_gen7(inst
, dst
, src
[0], src
[1]);
1257 } else if (intel
->gen
== 6) {
1258 generate_math2_gen6(inst
, dst
, src
[0], src
[1]);
1260 generate_math_gen4(inst
, dst
, src
[0]);
1263 case FS_OPCODE_PIXEL_X
:
1264 generate_pixel_xy(dst
, true);
1266 case FS_OPCODE_PIXEL_Y
:
1267 generate_pixel_xy(dst
, false);
1269 case FS_OPCODE_CINTERP
:
1270 brw_MOV(p
, dst
, src
[0]);
1272 case FS_OPCODE_LINTERP
:
1273 generate_linterp(inst
, dst
, src
);
1275 case SHADER_OPCODE_TEX
:
1277 case SHADER_OPCODE_TXD
:
1278 case SHADER_OPCODE_TXF
:
1279 case SHADER_OPCODE_TXF_MS
:
1280 case SHADER_OPCODE_TXL
:
1281 case SHADER_OPCODE_TXS
:
1282 case SHADER_OPCODE_LOD
:
1283 generate_tex(inst
, dst
, src
[0]);
1286 generate_ddx(inst
, dst
, src
[0]);
1289 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1290 * guarantee that c->key.render_to_fbo is set).
1292 assert(fp
->UsesDFdy
);
1293 generate_ddy(inst
, dst
, src
[0], c
->key
.render_to_fbo
);
1296 case FS_OPCODE_SPILL
:
1297 generate_spill(inst
, src
[0]);
1300 case FS_OPCODE_UNSPILL
:
1301 generate_unspill(inst
, dst
);
1304 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1305 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1308 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
1309 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1312 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
1313 generate_varying_pull_constant_load(inst
, dst
, src
[0]);
1316 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
1317 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1320 case FS_OPCODE_FB_WRITE
:
1321 generate_fb_write(inst
);
1324 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
1325 generate_mov_dispatch_to_flags(inst
);
1328 case FS_OPCODE_DISCARD_JUMP
:
1329 generate_discard_jump(inst
);
1332 case SHADER_OPCODE_SHADER_TIME_ADD
:
1333 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
1336 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
1337 generate_set_simd4x2_offset(inst
, dst
, src
[0]);
1340 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
1341 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
1344 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
1345 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
1346 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
1350 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
1351 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
1352 opcode_descs
[inst
->opcode
].name
);
1354 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
1359 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1360 brw_dump_compile(p
, stdout
,
1361 last_native_insn_offset
, p
->next_insn_offset
);
1363 foreach_list(node
, &cfg
->block_list
) {
1364 bblock_link
*link
= (bblock_link
*)node
;
1365 bblock_t
*block
= link
->block
;
1367 if (block
->end
== inst
) {
1368 printf(" END B%d", block
->block_num
);
1369 foreach_list(successor_node
, &block
->children
) {
1370 bblock_link
*successor_link
=
1371 (bblock_link
*)successor_node
;
1372 bblock_t
*successor_block
= successor_link
->block
;
1373 printf(" ->B%d", successor_block
->block_num
);
1380 last_native_insn_offset
= p
->next_insn_offset
;
1383 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
1389 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
1390 * emit issues, it doesn't get the jump distances into the output,
1391 * which is often something we want to debug. So this is here in
1392 * case you're doing that.
1395 brw_dump_compile(p
, stdout
, 0, p
->next_insn_offset
);
1400 fs_generator::generate_assembly(exec_list
*simd8_instructions
,
1401 exec_list
*simd16_instructions
,
1402 unsigned *assembly_size
)
1405 generate_code(simd8_instructions
);
1407 if (simd16_instructions
) {
1408 /* We have to do a compaction pass now, or the one at the end of
1409 * execution will squash down where our prog_offset start needs
1412 brw_compact_instructions(p
);
1414 /* align to 64 byte boundary. */
1415 while ((p
->nr_insn
* sizeof(struct brw_instruction
)) % 64) {
1419 /* Save off the start of this 16-wide program */
1420 c
->prog_data
.prog_offset_16
= p
->nr_insn
* sizeof(struct brw_instruction
);
1422 brw_set_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1424 dispatch_width
= 16;
1425 generate_code(simd16_instructions
);
1428 return brw_get_program(p
, assembly_size
);