2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
33 #include "brw_program.h"
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg
*reg
)
40 return BRW_ARCHITECTURE_REGISTER_FILE
;
43 return BRW_GENERAL_REGISTER_FILE
;
45 return BRW_MESSAGE_REGISTER_FILE
;
47 return BRW_IMMEDIATE_VALUE
;
51 unreachable("not reached");
53 return BRW_ARCHITECTURE_REGISTER_FILE
;
57 brw_reg_from_fs_reg(const struct brw_codegen
*p
,
58 fs_inst
*inst
, fs_reg
*reg
, unsigned gen
)
60 struct brw_reg brw_reg
;
64 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(gen
));
67 if (reg
->stride
== 0) {
68 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
69 } else if (!p
->compressed
&&
70 inst
->exec_size
* reg
->stride
* type_sz(reg
->type
) <= 32) {
71 brw_reg
= brw_vecn_reg(inst
->exec_size
, brw_file_from_reg(reg
),
73 brw_reg
= stride(brw_reg
, inst
->exec_size
* reg
->stride
,
74 inst
->exec_size
, reg
->stride
);
76 /* From the Haswell PRM:
78 * VertStride must be used to cross GRF register boundaries. This
79 * rule implies that elements within a 'Width' cannot cross GRF
82 * So, for registers that are large enough, we have to split the exec
83 * size in two and trust the compression state to sort it out.
85 assert(inst
->exec_size
/ 2 * reg
->stride
* type_sz(reg
->type
) <= 32);
86 brw_reg
= brw_vecn_reg(inst
->exec_size
/ 2, brw_file_from_reg(reg
),
88 brw_reg
= stride(brw_reg
, inst
->exec_size
/ 2 * reg
->stride
,
89 inst
->exec_size
/ 2, reg
->stride
);
92 brw_reg
= retype(brw_reg
, reg
->type
);
93 brw_reg
= byte_offset(brw_reg
, reg
->subreg_offset
);
94 brw_reg
.abs
= reg
->abs
;
95 brw_reg
.negate
= reg
->negate
;
100 brw_reg
= reg
->as_brw_reg();
103 /* Probably unused. */
104 brw_reg
= brw_null_reg();
108 unreachable("not reached");
114 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
117 struct brw_stage_prog_data
*prog_data
,
118 unsigned promoted_constants
,
119 bool runtime_check_aads_emit
,
120 gl_shader_stage stage
)
122 : compiler(compiler
), log_data(log_data
),
123 devinfo(compiler
->devinfo
), key(key
),
124 prog_data(prog_data
),
125 promoted_constants(promoted_constants
),
126 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
127 stage(stage
), mem_ctx(mem_ctx
)
129 p
= rzalloc(mem_ctx
, struct brw_codegen
);
130 brw_init_codegen(devinfo
, p
, mem_ctx
);
133 fs_generator::~fs_generator()
137 class ip_record
: public exec_node
{
139 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
150 fs_generator::patch_discard_jumps_to_fb_writes()
152 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
155 int scale
= brw_jump_scale(p
->devinfo
);
157 /* There is a somewhat strange undocumented requirement of using
158 * HALT, according to the simulator. If some channel has HALTed to
159 * a particular UIP, then by the end of the program, every channel
160 * must have HALTed to that UIP. Furthermore, the tracking is a
161 * stack, so you can't do the final halt of a UIP after starting
162 * halting to a new UIP.
164 * Symptoms of not emitting this instruction on actual hardware
165 * included GPU hangs and sparkly rendering on the piglit discard
168 brw_inst
*last_halt
= gen6_HALT(p
);
169 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
170 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
174 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
175 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
177 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
178 /* HALT takes a half-instruction distance from the pre-incremented IP. */
179 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
182 this->discard_halt_patches
.make_empty();
187 fs_generator::fire_fb_write(fs_inst
*inst
,
188 struct brw_reg payload
,
189 struct brw_reg implied_header
,
192 uint32_t msg_control
;
194 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
196 if (devinfo
->gen
< 6) {
197 brw_push_insn_state(p
);
198 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
199 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
200 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
201 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
202 brw_MOV(p
, offset(payload
, 1), brw_vec8_grf(1, 0));
203 brw_pop_insn_state(p
);
206 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
)
207 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
208 else if (prog_data
->dual_src_blend
) {
209 if (!inst
->force_sechalf
)
210 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
212 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
213 } else if (inst
->exec_size
== 16)
214 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
216 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
218 uint32_t surf_index
=
219 prog_data
->binding_table
.render_target_start
+ inst
->target
;
221 bool last_render_target
= inst
->eot
||
222 (prog_data
->dual_src_blend
&& dispatch_width
== 16);
235 inst
->header_size
!= 0);
237 brw_mark_surface_used(&prog_data
->base
, surf_index
);
241 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
243 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
244 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
245 struct brw_reg implied_header
;
247 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
248 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
251 if (inst
->base_mrf
>= 0)
252 payload
= brw_message_reg(inst
->base_mrf
);
254 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
257 if (inst
->header_size
!= 0) {
258 brw_push_insn_state(p
);
259 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
260 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
261 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
262 brw_set_default_flag_reg(p
, 0, 0);
264 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
267 if (prog_data
->uses_kill
) {
268 struct brw_reg pixel_mask
;
270 if (devinfo
->gen
>= 6)
271 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
273 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
275 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
278 if (devinfo
->gen
>= 6) {
279 brw_push_insn_state(p
);
280 brw_set_default_exec_size(p
, BRW_EXECUTE_16
);
281 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
283 retype(payload
, BRW_REGISTER_TYPE_UD
),
284 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
285 brw_pop_insn_state(p
);
287 if (inst
->target
> 0 && key
->replicate_alpha
) {
288 /* Set "Source0 Alpha Present to RenderTarget" bit in message
292 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
293 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
294 brw_imm_ud(0x1 << 11));
297 if (inst
->target
> 0) {
298 /* Set the render target index for choosing BLEND_STATE. */
299 brw_MOV(p
, retype(vec1(suboffset(payload
, 2)),
300 BRW_REGISTER_TYPE_UD
),
301 brw_imm_ud(inst
->target
));
304 /* Set computes stencil to render target */
305 if (prog_data
->computed_stencil
) {
307 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
308 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
309 brw_imm_ud(0x1 << 14));
312 implied_header
= brw_null_reg();
314 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
317 brw_pop_insn_state(p
);
319 implied_header
= brw_null_reg();
322 if (!runtime_check_aads_emit
) {
323 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
325 /* This can only happen in gen < 6 */
326 assert(devinfo
->gen
< 6);
328 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
330 /* Check runtime bit to detect if we have to send AA data or not */
331 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
334 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
336 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
338 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
339 brw_inst_set_exec_size(p
->devinfo
, brw_last_inst
, BRW_EXECUTE_1
);
341 /* Don't send AA data */
342 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
344 brw_land_fwd_jump(p
, jmp
);
345 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
350 fs_generator::generate_mov_indirect(fs_inst
*inst
,
353 struct brw_reg indirect_byte_offset
)
355 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
356 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
358 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
360 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
361 imm_byte_offset
+= indirect_byte_offset
.ud
;
363 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
364 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
365 brw_MOV(p
, dst
, reg
);
367 /* Prior to Broadwell, there are only 8 address registers. */
368 assert(inst
->exec_size
== 8 || devinfo
->gen
>= 8);
370 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
371 struct brw_reg addr
= vec8(brw_address_reg(0));
373 /* The destination stride of an instruction (in bytes) must be greater
374 * than or equal to the size of the rest of the instruction. Since the
375 * address register is of type UW, we can't use a D-type instruction.
376 * In order to get around this, re retype to UW and use a stride.
378 indirect_byte_offset
=
379 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
381 struct brw_reg ind_src
;
382 if (devinfo
->gen
< 8) {
383 /* From the Haswell PRM section "Register Region Restrictions":
385 * "The lower bits of the AddressImmediate must not overflow to
386 * change the register address. The lower 5 bits of Address
387 * Immediate when added to lower 5 bits of address register gives
388 * the sub-register offset. The upper bits of Address Immediate
389 * when added to upper bits of address register gives the register
390 * address. Any overflow from sub-register offset is dropped."
392 * This restriction is only listed in the Haswell PRM but emperical
393 * testing indicates that it applies on all older generations and is
394 * lifted on Broadwell.
396 * Since the indirect may cause us to cross a register boundary, this
397 * makes the base offset almost useless. We could try and do
398 * something clever where we use a actual base offset if
399 * base_offset % 32 == 0 but that would mean we were generating
400 * different code depending on the base offset. Instead, for the
401 * sake of consistency, we'll just do the add ourselves.
403 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
404 ind_src
= brw_VxH_indirect(0, 0);
406 brw_MOV(p
, addr
, indirect_byte_offset
);
407 ind_src
= brw_VxH_indirect(0, imm_byte_offset
);
410 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, dst
.type
));
412 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
413 !inst
->get_next()->is_tail_sentinel() &&
414 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
415 /* From the Sandybridge PRM:
417 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
418 * instruction that “indexed/indirect” source AND is followed by a
419 * send, the instruction requires a “Switch”. This is to avoid
420 * race condition where send may dispatch before MRF is updated."
422 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
428 fs_generator::generate_urb_read(fs_inst
*inst
,
430 struct brw_reg header
)
432 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
433 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
435 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
436 brw_set_dest(p
, send
, dst
);
437 brw_set_src0(p
, send
, header
);
438 brw_set_src1(p
, send
, brw_imm_ud(0u));
440 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
441 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
443 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
444 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
446 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
447 brw_inst_set_rlen(p
->devinfo
, send
, inst
->regs_written
);
448 brw_inst_set_header_present(p
->devinfo
, send
, true);
449 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
453 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
457 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
459 brw_set_dest(p
, insn
, brw_null_reg());
460 brw_set_src0(p
, insn
, payload
);
461 brw_set_src1(p
, insn
, brw_imm_d(0));
463 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
464 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
466 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
467 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
468 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
470 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
471 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
472 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
474 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
475 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
476 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
477 brw_inst_set_header_present(p
->devinfo
, insn
, true);
478 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
482 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
484 struct brw_inst
*insn
;
486 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
488 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
489 brw_set_src0(p
, insn
, payload
);
490 brw_set_src1(p
, insn
, brw_imm_d(0));
492 /* Terminate a compute shader by sending a message to the thread spawner.
494 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
495 brw_inst_set_mlen(devinfo
, insn
, 1);
496 brw_inst_set_rlen(devinfo
, insn
, 0);
497 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
498 brw_inst_set_header_present(devinfo
, insn
, false);
500 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
501 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
503 /* Note that even though the thread has a URB resource associated with it,
504 * we set the "do not dereference URB" bit, because the URB resource is
505 * managed by the fixed-function unit, so it will free it automatically.
507 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
509 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
513 fs_generator::generate_barrier(fs_inst
*inst
, struct brw_reg src
)
520 fs_generator::generate_linterp(fs_inst
*inst
,
521 struct brw_reg dst
, struct brw_reg
*src
)
525 * -----------------------------------
526 * | src1+0 | src1+1 | src1+2 | src1+3 |
527 * |-----------------------------------|
528 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
529 * -----------------------------------
531 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
533 * -----------------------------------
534 * | src1+0 | src1+1 | src1+2 | src1+3 |
535 * |-----------------------------------|
536 * |(x0, x1)|(y0, y1)| | | in SIMD8
537 * |-----------------------------------|
538 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
539 * -----------------------------------
541 * See also: emit_interpolation_setup_gen4().
543 struct brw_reg delta_x
= src
[0];
544 struct brw_reg delta_y
= offset(src
[0], dispatch_width
/ 8);
545 struct brw_reg interp
= src
[1];
547 if (devinfo
->has_pln
&&
548 (devinfo
->gen
>= 7 || (delta_x
.nr
& 1) == 0)) {
549 brw_PLN(p
, dst
, interp
, delta_x
);
551 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
552 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
557 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
560 struct brw_reg surf_index
)
562 assert(devinfo
->gen
>= 7);
563 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
568 switch (inst
->exec_size
) {
570 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
573 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
576 unreachable("Invalid width for texture instruction");
579 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
585 retype(dst
, BRW_REGISTER_TYPE_UW
),
590 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
591 rlen
, /* response length */
593 inst
->header_size
> 0,
595 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
597 brw_mark_surface_used(prog_data
, surf_index
.ud
);
601 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
602 struct brw_reg surface_index
,
603 struct brw_reg sampler_index
)
607 uint32_t return_format
;
608 bool is_combined_send
= inst
->eot
;
611 case BRW_REGISTER_TYPE_D
:
612 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
614 case BRW_REGISTER_TYPE_UD
:
615 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
618 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
622 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
623 * is set as part of the message descriptor. On gen4, the PRM seems to
624 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
625 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
626 * gone from the message descriptor entirely and you just get UINT32 all
627 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
628 * just stomp it to UINT32 all the time.
630 if (inst
->opcode
== SHADER_OPCODE_TXS
)
631 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
633 switch (inst
->exec_size
) {
635 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
638 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
641 unreachable("Invalid width for texture instruction");
644 if (devinfo
->gen
>= 5) {
645 switch (inst
->opcode
) {
646 case SHADER_OPCODE_TEX
:
647 if (inst
->shadow_compare
) {
648 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
650 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
654 if (inst
->shadow_compare
) {
655 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
657 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
660 case SHADER_OPCODE_TXL
:
661 if (inst
->shadow_compare
) {
662 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
664 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
667 case SHADER_OPCODE_TXL_LZ
:
668 assert(devinfo
->gen
>= 9);
669 if (inst
->shadow_compare
) {
670 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ
;
672 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LZ
;
675 case SHADER_OPCODE_TXS
:
676 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
678 case SHADER_OPCODE_TXD
:
679 if (inst
->shadow_compare
) {
680 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
681 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
682 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
684 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
687 case SHADER_OPCODE_TXF
:
688 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
690 case SHADER_OPCODE_TXF_LZ
:
691 assert(devinfo
->gen
>= 9);
692 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ
;
694 case SHADER_OPCODE_TXF_CMS_W
:
695 assert(devinfo
->gen
>= 9);
696 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
698 case SHADER_OPCODE_TXF_CMS
:
699 if (devinfo
->gen
>= 7)
700 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
702 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
704 case SHADER_OPCODE_TXF_UMS
:
705 assert(devinfo
->gen
>= 7);
706 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
708 case SHADER_OPCODE_TXF_MCS
:
709 assert(devinfo
->gen
>= 7);
710 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
712 case SHADER_OPCODE_LOD
:
713 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
715 case SHADER_OPCODE_TG4
:
716 if (inst
->shadow_compare
) {
717 assert(devinfo
->gen
>= 7);
718 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
720 assert(devinfo
->gen
>= 6);
721 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
724 case SHADER_OPCODE_TG4_OFFSET
:
725 assert(devinfo
->gen
>= 7);
726 if (inst
->shadow_compare
) {
727 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
729 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
732 case SHADER_OPCODE_SAMPLEINFO
:
733 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
736 unreachable("not reached");
739 switch (inst
->opcode
) {
740 case SHADER_OPCODE_TEX
:
741 /* Note that G45 and older determines shadow compare and dispatch width
742 * from message length for most messages.
744 if (inst
->exec_size
== 8) {
745 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
746 if (inst
->shadow_compare
) {
747 assert(inst
->mlen
== 6);
749 assert(inst
->mlen
<= 4);
752 if (inst
->shadow_compare
) {
753 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
754 assert(inst
->mlen
== 9);
756 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
757 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
762 if (inst
->shadow_compare
) {
763 assert(inst
->exec_size
== 8);
764 assert(inst
->mlen
== 6);
765 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
767 assert(inst
->mlen
== 9);
768 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
769 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
772 case SHADER_OPCODE_TXL
:
773 if (inst
->shadow_compare
) {
774 assert(inst
->exec_size
== 8);
775 assert(inst
->mlen
== 6);
776 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
778 assert(inst
->mlen
== 9);
779 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
780 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
783 case SHADER_OPCODE_TXD
:
784 /* There is no sample_d_c message; comparisons are done manually */
785 assert(inst
->exec_size
== 8);
786 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
787 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
789 case SHADER_OPCODE_TXF
:
790 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
791 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
792 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
794 case SHADER_OPCODE_TXS
:
795 assert(inst
->mlen
== 3);
796 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
797 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
800 unreachable("not reached");
803 assert(msg_type
!= -1);
805 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
809 assert(devinfo
->gen
< 7 || inst
->header_size
== 0 ||
810 src
.file
== BRW_GENERAL_REGISTER_FILE
);
812 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
814 /* Load the message header if present. If there's a texture offset,
815 * we need to set it up explicitly and load the offset bitfield.
816 * Otherwise, we can use an implied move from g0 to the first message reg.
818 if (inst
->header_size
!= 0) {
819 if (devinfo
->gen
< 6 && !inst
->offset
) {
820 /* Set up an implied move from g0 to the MRF. */
821 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
823 struct brw_reg header_reg
;
825 if (devinfo
->gen
>= 7) {
828 assert(inst
->base_mrf
!= -1);
829 header_reg
= brw_message_reg(inst
->base_mrf
);
832 brw_push_insn_state(p
);
833 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
834 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
835 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
836 /* Explicitly set up the message header by copying g0 to the MRF. */
837 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
840 /* Set the offset bits in DWord 2. */
841 brw_MOV(p
, get_element_ud(header_reg
, 2),
842 brw_imm_ud(inst
->offset
));
843 } else if (stage
!= MESA_SHADER_VERTEX
&&
844 stage
!= MESA_SHADER_FRAGMENT
) {
845 /* The vertex and fragment stages have g0.2 set to 0, so
846 * header0.2 is 0 when g0 is copied. Other stages may not, so we
847 * must set it to 0 to avoid setting undesirable bits in the
850 brw_MOV(p
, get_element_ud(header_reg
, 2), brw_imm_ud(0));
853 brw_adjust_sampler_state_pointer(p
, header_reg
, sampler_index
);
854 brw_pop_insn_state(p
);
858 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
859 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
860 ? prog_data
->binding_table
.gather_texture_start
861 : prog_data
->binding_table
.texture_start
;
863 if (surface_index
.file
== BRW_IMMEDIATE_VALUE
&&
864 sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
865 uint32_t surface
= surface_index
.ud
;
866 uint32_t sampler
= sampler_index
.ud
;
869 retype(dst
, BRW_REGISTER_TYPE_UW
),
872 surface
+ base_binding_table_index
,
877 inst
->header_size
!= 0,
881 brw_mark_surface_used(prog_data
, surface
+ base_binding_table_index
);
883 /* Non-const sampler index */
885 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
886 struct brw_reg surface_reg
= vec1(retype(surface_index
, BRW_REGISTER_TYPE_UD
));
887 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
889 brw_push_insn_state(p
);
890 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
891 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
893 if (brw_regs_equal(&surface_reg
, &sampler_reg
)) {
894 brw_MUL(p
, addr
, sampler_reg
, brw_imm_uw(0x101));
896 brw_SHL(p
, addr
, sampler_reg
, brw_imm_ud(8));
897 brw_OR(p
, addr
, addr
, surface_reg
);
899 if (base_binding_table_index
)
900 brw_ADD(p
, addr
, addr
, brw_imm_ud(base_binding_table_index
));
901 brw_AND(p
, addr
, addr
, brw_imm_ud(0xfff));
903 brw_pop_insn_state(p
);
905 /* dst = send(offset, a0.0 | <descriptor>) */
906 brw_inst
*insn
= brw_send_indirect_message(
907 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
908 brw_set_sampler_message(p
, insn
,
913 inst
->mlen
/* mlen */,
914 inst
->header_size
!= 0 /* header */,
918 /* visitor knows more than we do about the surface limit required,
919 * so has already done marking.
923 if (is_combined_send
) {
924 brw_inst_set_eot(p
->devinfo
, brw_last_inst
, true);
925 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
930 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
933 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
935 * Ideally, we want to produce:
938 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
939 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
940 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
941 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
942 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
943 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
944 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
945 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
947 * and add another set of two more subspans if in 16-pixel dispatch mode.
949 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
950 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
951 * pair. But the ideal approximation may impose a huge performance cost on
952 * sample_d. On at least Haswell, sample_d instruction does some
953 * optimizations if the same LOD is used for all pixels in the subspan.
955 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
956 * appropriate swizzling.
959 fs_generator::generate_ddx(enum opcode opcode
,
960 struct brw_reg dst
, struct brw_reg src
)
962 unsigned vstride
, width
;
964 if (opcode
== FS_OPCODE_DDX_FINE
) {
965 /* produce accurate derivatives */
966 vstride
= BRW_VERTICAL_STRIDE_2
;
969 /* replicate the derivative at the top-left pixel to other pixels */
970 vstride
= BRW_VERTICAL_STRIDE_4
;
974 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
979 BRW_HORIZONTAL_STRIDE_0
,
980 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
981 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
986 BRW_HORIZONTAL_STRIDE_0
,
987 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
988 brw_ADD(p
, dst
, src0
, negate(src1
));
991 /* The negate_value boolean is used to negate the derivative computation for
992 * FBOs, since they place the origin at the upper left instead of the lower
996 fs_generator::generate_ddy(enum opcode opcode
,
997 struct brw_reg dst
, struct brw_reg src
)
999 if (opcode
== FS_OPCODE_DDY_FINE
) {
1000 /* produce accurate derivatives */
1001 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1002 src
.negate
, src
.abs
,
1003 BRW_REGISTER_TYPE_F
,
1004 BRW_VERTICAL_STRIDE_4
,
1006 BRW_HORIZONTAL_STRIDE_1
,
1007 BRW_SWIZZLE_XYXY
, WRITEMASK_XYZW
);
1008 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
1009 src
.negate
, src
.abs
,
1010 BRW_REGISTER_TYPE_F
,
1011 BRW_VERTICAL_STRIDE_4
,
1013 BRW_HORIZONTAL_STRIDE_1
,
1014 BRW_SWIZZLE_ZWZW
, WRITEMASK_XYZW
);
1015 brw_push_insn_state(p
);
1016 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1017 brw_ADD(p
, dst
, negate(src0
), src1
);
1018 brw_pop_insn_state(p
);
1020 /* replicate the derivative at the top-left pixel to other pixels */
1021 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1022 src
.negate
, src
.abs
,
1023 BRW_REGISTER_TYPE_F
,
1024 BRW_VERTICAL_STRIDE_4
,
1026 BRW_HORIZONTAL_STRIDE_0
,
1027 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1028 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
1029 src
.negate
, src
.abs
,
1030 BRW_REGISTER_TYPE_F
,
1031 BRW_VERTICAL_STRIDE_4
,
1033 BRW_HORIZONTAL_STRIDE_0
,
1034 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1035 brw_ADD(p
, dst
, negate(src0
), src1
);
1040 fs_generator::generate_discard_jump(fs_inst
*inst
)
1042 assert(devinfo
->gen
>= 6);
1044 /* This HALT will be patched up at FB write time to point UIP at the end of
1045 * the program, and at brw_uip_jip() JIP will be set to the end of the
1046 * current block (or the program).
1048 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1050 brw_push_insn_state(p
);
1051 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1053 brw_pop_insn_state(p
);
1057 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1059 assert(inst
->mlen
!= 0);
1062 brw_uvec_mrf(inst
->exec_size
, (inst
->base_mrf
+ 1), 0),
1063 retype(src
, BRW_REGISTER_TYPE_UD
));
1064 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1065 inst
->exec_size
/ 8, inst
->offset
);
1069 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1071 assert(inst
->mlen
!= 0);
1073 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1074 inst
->exec_size
/ 8, inst
->offset
);
1078 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1080 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1084 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1086 struct brw_reg index
,
1087 struct brw_reg offset
)
1089 assert(inst
->mlen
!= 0);
1091 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1092 index
.type
== BRW_REGISTER_TYPE_UD
);
1093 uint32_t surf_index
= index
.ud
;
1095 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1096 offset
.type
== BRW_REGISTER_TYPE_UD
);
1097 uint32_t read_offset
= offset
.ud
;
1099 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1100 read_offset
, surf_index
);
1104 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1106 struct brw_reg index
,
1107 struct brw_reg offset
)
1109 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1111 assert(offset
.file
== BRW_GENERAL_REGISTER_FILE
);
1112 /* Reference just the dword we need, to avoid angering validate_reg(). */
1113 offset
= brw_vec1_grf(offset
.nr
, 0);
1115 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1116 * the destination loaded consecutively from the same offset (which appears
1117 * in the first component, and the rest are ignored).
1119 dst
.width
= BRW_WIDTH_4
;
1121 struct brw_reg src
= offset
;
1122 bool header_present
= false;
1124 if (devinfo
->gen
>= 9) {
1125 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1126 src
= retype(brw_vec4_grf(offset
.nr
, 0), BRW_REGISTER_TYPE_UD
);
1127 header_present
= true;
1129 brw_push_insn_state(p
);
1130 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1131 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1132 brw_MOV(p
, vec8(src
), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1133 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1135 brw_MOV(p
, get_element_ud(src
, 2),
1136 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
));
1137 brw_pop_insn_state(p
);
1140 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1142 uint32_t surf_index
= index
.ud
;
1144 brw_push_insn_state(p
);
1145 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1146 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1147 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1148 brw_inst_set_exec_size(devinfo
, send
, BRW_EXECUTE_4
);
1149 brw_pop_insn_state(p
);
1151 brw_set_dest(p
, send
, dst
);
1152 brw_set_src0(p
, send
, src
);
1153 brw_set_sampler_message(p
, send
,
1155 0, /* LD message ignores sampler unit */
1156 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1160 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1164 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1166 brw_push_insn_state(p
);
1167 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1168 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1170 /* a0.0 = surf_index & 0xff */
1171 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1172 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1173 brw_set_dest(p
, insn_and
, addr
);
1174 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1175 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1177 /* dst = send(payload, a0.0 | <descriptor>) */
1178 brw_inst
*insn
= brw_send_indirect_message(
1179 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
1180 brw_set_sampler_message(p
, insn
,
1182 0, /* LD message ignores sampler unit */
1183 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1187 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1190 brw_pop_insn_state(p
);
1195 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1197 struct brw_reg index
)
1199 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1200 assert(inst
->header_size
!= 0);
1203 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1204 index
.type
== BRW_REGISTER_TYPE_UD
);
1205 uint32_t surf_index
= index
.ud
;
1207 uint32_t simd_mode
, rlen
, msg_type
;
1208 if (dispatch_width
== 16) {
1209 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1212 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1216 if (devinfo
->gen
>= 5)
1217 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1219 /* We always use the SIMD16 message so that we only have to load U, and
1222 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1223 assert(inst
->mlen
== 3);
1224 assert(inst
->regs_written
== 8);
1226 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1229 struct brw_reg header
= brw_vec8_grf(0, 0);
1230 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1232 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1233 brw_inst_set_compression(devinfo
, send
, false);
1234 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1235 brw_set_src0(p
, send
, header
);
1236 if (devinfo
->gen
< 6)
1237 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1239 /* Our surface is set up as floats, regardless of what actual data is
1242 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1243 brw_set_sampler_message(p
, send
,
1245 0, /* sampler (unused) */
1249 inst
->header_size
!= 0,
1255 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1257 struct brw_reg index
,
1258 struct brw_reg offset
)
1260 assert(devinfo
->gen
>= 7);
1261 /* Varying-offset pull constant loads are treated as a normal expression on
1262 * gen7, so the fact that it's a send message is hidden at the IR level.
1264 assert(inst
->header_size
== 0);
1265 assert(!inst
->mlen
);
1266 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1268 uint32_t simd_mode
, rlen
, mlen
;
1269 if (dispatch_width
== 16) {
1272 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1276 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1279 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1281 uint32_t surf_index
= index
.ud
;
1283 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1284 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1285 brw_set_src0(p
, send
, offset
);
1286 brw_set_sampler_message(p
, send
,
1288 0, /* LD message ignores sampler unit */
1289 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1292 false, /* no header */
1298 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1300 brw_push_insn_state(p
);
1301 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1302 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1304 /* a0.0 = surf_index & 0xff */
1305 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1306 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1307 brw_set_dest(p
, insn_and
, addr
);
1308 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1309 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1311 brw_pop_insn_state(p
);
1313 /* dst = send(offset, a0.0 | <descriptor>) */
1314 brw_inst
*insn
= brw_send_indirect_message(
1315 p
, BRW_SFID_SAMPLER
, retype(dst
, BRW_REGISTER_TYPE_UW
),
1317 brw_set_sampler_message(p
, insn
,
1320 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1330 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1331 * into the flags register (f0.0).
1333 * Used only on Gen6 and above.
1336 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
1338 struct brw_reg flags
= brw_flag_reg(0, inst
->flag_subreg
);
1339 struct brw_reg dispatch_mask
;
1341 if (devinfo
->gen
>= 6)
1342 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1344 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1346 brw_push_insn_state(p
);
1347 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1348 brw_MOV(p
, flags
, dispatch_mask
);
1349 brw_pop_insn_state(p
);
1353 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1356 struct brw_reg msg_data
,
1359 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1361 brw_pixel_interpolator_query(p
,
1362 retype(dst
, BRW_REGISTER_TYPE_UW
),
1364 inst
->pi_noperspective
,
1368 inst
->regs_written
);
1373 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1374 * sampler LD messages.
1376 * We don't want to bake it into the send message's code generation because
1377 * that means we don't get a chance to schedule the instructions.
1380 fs_generator::generate_set_simd4x2_offset(fs_inst
*inst
,
1382 struct brw_reg value
)
1384 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1386 brw_push_insn_state(p
);
1387 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1388 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1389 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1390 brw_MOV(p
, retype(brw_vec1_reg(dst
.file
, dst
.nr
, 0), value
.type
), value
);
1391 brw_pop_insn_state(p
);
1394 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1395 * the ADD instruction.
1398 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1400 struct brw_reg src0
,
1401 struct brw_reg src1
)
1403 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1404 dst
.type
== BRW_REGISTER_TYPE_UD
);
1405 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1406 src0
.type
== BRW_REGISTER_TYPE_UD
);
1408 struct brw_reg reg
= stride(src1
, 1, 4, 0);
1409 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
1410 brw_ADD(p
, dst
, src0
, reg
);
1411 } else if (dispatch_width
== 16) {
1412 brw_push_insn_state(p
);
1413 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1414 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1415 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), reg
);
1416 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1417 brw_ADD(p
, sechalf(dst
), sechalf(src0
), suboffset(reg
, 2));
1418 brw_pop_insn_state(p
);
1423 fs_generator::generate_pack_half_2x16_split(fs_inst
*inst
,
1428 assert(devinfo
->gen
>= 7);
1429 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1430 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1431 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1433 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1435 * Because this instruction does not have a 16-bit floating-point type,
1436 * the destination data type must be Word (W).
1438 * The destination must be DWord-aligned and specify a horizontal stride
1439 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1440 * each destination channel and the upper word is not modified.
1442 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1444 /* Give each 32-bit channel of dst the form below, where "." means
1448 brw_F32TO16(p
, dst_w
, y
);
1453 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1455 /* And, finally the form of packHalf2x16's output:
1458 brw_F32TO16(p
, dst_w
, x
);
1462 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
1466 assert(devinfo
->gen
>= 7);
1467 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1468 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1470 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1472 * Because this instruction does not have a 16-bit floating-point type,
1473 * the source data type must be Word (W). The destination type must be
1476 struct brw_reg src_w
= spread(retype(src
, BRW_REGISTER_TYPE_W
), 2);
1478 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1479 * For the Y case, we wish to access only the upper word; therefore
1480 * a 16-bit subregister offset is needed.
1482 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1483 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1484 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1487 brw_F16TO32(p
, dst
, src_w
);
1491 fs_generator::generate_shader_time_add(fs_inst
*inst
,
1492 struct brw_reg payload
,
1493 struct brw_reg offset
,
1494 struct brw_reg value
)
1496 assert(devinfo
->gen
>= 7);
1497 brw_push_insn_state(p
);
1498 brw_set_default_mask_control(p
, true);
1500 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1501 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1503 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1506 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1507 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1508 value
.width
= BRW_WIDTH_1
;
1509 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1510 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1512 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1515 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1516 * case, and we don't really care about squeezing every bit of performance
1517 * out of this path, so we just emit the MOVs from here.
1519 brw_MOV(p
, payload_offset
, offset
);
1520 brw_MOV(p
, payload_value
, value
);
1521 brw_shader_time_add(p
, payload
,
1522 prog_data
->binding_table
.shader_time_start
);
1523 brw_pop_insn_state(p
);
1525 brw_mark_surface_used(prog_data
,
1526 prog_data
->binding_table
.shader_time_start
);
1530 fs_generator::enable_debug(const char *shader_name
)
1533 this->shader_name
= shader_name
;
1537 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1539 /* align to 64 byte boundary. */
1540 while (p
->next_insn_offset
% 64)
1543 this->dispatch_width
= dispatch_width
;
1545 int start_offset
= p
->next_insn_offset
;
1546 int spill_count
= 0, fill_count
= 0;
1549 struct annotation_info annotation
;
1550 memset(&annotation
, 0, sizeof(annotation
));
1552 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1553 struct brw_reg src
[3], dst
;
1554 unsigned int last_insn_offset
= p
->next_insn_offset
;
1555 bool multiple_instructions_emitted
= false;
1557 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1558 * "Register Region Restrictions" section: for BDW, SKL:
1560 * "A POW/FDIV operation must not be followed by an instruction
1561 * that requires two destination registers."
1563 * The documentation is often lacking annotations for Atom parts,
1564 * and empirically this affects CHV as well.
1566 if (devinfo
->gen
>= 8 &&
1568 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1569 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1570 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1572 last_insn_offset
= p
->next_insn_offset
;
1575 if (unlikely(debug_flag
))
1576 annotate(p
->devinfo
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1578 /* If the instruction writes to more than one register, it needs to be
1579 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1580 * hardware figures out by itself what the right compression mode is,
1581 * but we still need to know whether the instruction is compressed to
1582 * set up the source register regions appropriately.
1584 * XXX - This is wrong for instructions that write a single register but
1585 * read more than one which should strictly speaking be treated as
1586 * compressed. For instructions that don't write any registers it
1587 * relies on the destination being a null register of the correct
1588 * type and regioning so the instruction is considered compressed
1589 * or not accordingly.
1591 p
->compressed
= inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
;
1592 brw_set_default_compression(p
, p
->compressed
);
1593 brw_set_default_group(p
, inst
->force_sechalf
? 8 : 0);
1595 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1596 src
[i
] = brw_reg_from_fs_reg(p
, inst
, &inst
->src
[i
], devinfo
->gen
);
1598 /* The accumulator result appears to get used for the
1599 * conditional modifier generation. When negating a UD
1600 * value, there is a 33rd bit generated for the sign in the
1601 * accumulator value, so now you can't check, for example,
1602 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1604 assert(!inst
->conditional_mod
||
1605 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1606 !inst
->src
[i
].negate
);
1608 dst
= brw_reg_from_fs_reg(p
, inst
, &inst
->dst
, devinfo
->gen
);
1610 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1611 brw_set_default_predicate_control(p
, inst
->predicate
);
1612 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1613 brw_set_default_flag_reg(p
, 0, inst
->flag_subreg
);
1614 brw_set_default_saturate(p
, inst
->saturate
);
1615 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1616 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1617 brw_set_default_exec_size(p
, cvt(inst
->exec_size
) - 1);
1619 assert(inst
->force_writemask_all
|| inst
->exec_size
>= 8);
1620 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1621 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1623 switch (inst
->opcode
) {
1624 case BRW_OPCODE_MOV
:
1625 brw_MOV(p
, dst
, src
[0]);
1627 case BRW_OPCODE_ADD
:
1628 brw_ADD(p
, dst
, src
[0], src
[1]);
1630 case BRW_OPCODE_MUL
:
1631 brw_MUL(p
, dst
, src
[0], src
[1]);
1633 case BRW_OPCODE_AVG
:
1634 brw_AVG(p
, dst
, src
[0], src
[1]);
1636 case BRW_OPCODE_MACH
:
1637 brw_MACH(p
, dst
, src
[0], src
[1]);
1640 case BRW_OPCODE_LINE
:
1641 brw_LINE(p
, dst
, src
[0], src
[1]);
1644 case BRW_OPCODE_MAD
:
1645 assert(devinfo
->gen
>= 6);
1646 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1647 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1650 case BRW_OPCODE_LRP
:
1651 assert(devinfo
->gen
>= 6);
1652 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1653 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1656 case BRW_OPCODE_FRC
:
1657 brw_FRC(p
, dst
, src
[0]);
1659 case BRW_OPCODE_RNDD
:
1660 brw_RNDD(p
, dst
, src
[0]);
1662 case BRW_OPCODE_RNDE
:
1663 brw_RNDE(p
, dst
, src
[0]);
1665 case BRW_OPCODE_RNDZ
:
1666 brw_RNDZ(p
, dst
, src
[0]);
1669 case BRW_OPCODE_AND
:
1670 brw_AND(p
, dst
, src
[0], src
[1]);
1673 brw_OR(p
, dst
, src
[0], src
[1]);
1675 case BRW_OPCODE_XOR
:
1676 brw_XOR(p
, dst
, src
[0], src
[1]);
1678 case BRW_OPCODE_NOT
:
1679 brw_NOT(p
, dst
, src
[0]);
1681 case BRW_OPCODE_ASR
:
1682 brw_ASR(p
, dst
, src
[0], src
[1]);
1684 case BRW_OPCODE_SHR
:
1685 brw_SHR(p
, dst
, src
[0], src
[1]);
1687 case BRW_OPCODE_SHL
:
1688 brw_SHL(p
, dst
, src
[0], src
[1]);
1690 case BRW_OPCODE_F32TO16
:
1691 assert(devinfo
->gen
>= 7);
1692 brw_F32TO16(p
, dst
, src
[0]);
1694 case BRW_OPCODE_F16TO32
:
1695 assert(devinfo
->gen
>= 7);
1696 brw_F16TO32(p
, dst
, src
[0]);
1698 case BRW_OPCODE_CMP
:
1699 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1700 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1701 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1702 * implemented in the compiler is not sufficient. Overriding the
1703 * type when the destination is the null register is necessary but
1704 * not sufficient by itself.
1706 assert(dst
.nr
== BRW_ARF_NULL
);
1707 dst
.type
= BRW_REGISTER_TYPE_D
;
1709 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1711 case BRW_OPCODE_SEL
:
1712 brw_SEL(p
, dst
, src
[0], src
[1]);
1714 case BRW_OPCODE_BFREV
:
1715 assert(devinfo
->gen
>= 7);
1716 /* BFREV only supports UD type for src and dst. */
1717 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1718 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1720 case BRW_OPCODE_FBH
:
1721 assert(devinfo
->gen
>= 7);
1722 /* FBH only supports UD type for dst. */
1723 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1725 case BRW_OPCODE_FBL
:
1726 assert(devinfo
->gen
>= 7);
1727 /* FBL only supports UD type for dst. */
1728 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1730 case BRW_OPCODE_CBIT
:
1731 assert(devinfo
->gen
>= 7);
1732 /* CBIT only supports UD type for dst. */
1733 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1735 case BRW_OPCODE_ADDC
:
1736 assert(devinfo
->gen
>= 7);
1737 brw_ADDC(p
, dst
, src
[0], src
[1]);
1739 case BRW_OPCODE_SUBB
:
1740 assert(devinfo
->gen
>= 7);
1741 brw_SUBB(p
, dst
, src
[0], src
[1]);
1743 case BRW_OPCODE_MAC
:
1744 brw_MAC(p
, dst
, src
[0], src
[1]);
1747 case BRW_OPCODE_BFE
:
1748 assert(devinfo
->gen
>= 7);
1749 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1750 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1753 case BRW_OPCODE_BFI1
:
1754 assert(devinfo
->gen
>= 7);
1755 brw_BFI1(p
, dst
, src
[0], src
[1]);
1757 case BRW_OPCODE_BFI2
:
1758 assert(devinfo
->gen
>= 7);
1759 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1760 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1764 if (inst
->src
[0].file
!= BAD_FILE
) {
1765 /* The instruction has an embedded compare (only allowed on gen6) */
1766 assert(devinfo
->gen
== 6);
1767 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1769 brw_IF(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
1773 case BRW_OPCODE_ELSE
:
1776 case BRW_OPCODE_ENDIF
:
1781 brw_DO(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
1784 case BRW_OPCODE_BREAK
:
1786 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1788 case BRW_OPCODE_CONTINUE
:
1790 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1793 case BRW_OPCODE_WHILE
:
1798 case SHADER_OPCODE_RCP
:
1799 case SHADER_OPCODE_RSQ
:
1800 case SHADER_OPCODE_SQRT
:
1801 case SHADER_OPCODE_EXP2
:
1802 case SHADER_OPCODE_LOG2
:
1803 case SHADER_OPCODE_SIN
:
1804 case SHADER_OPCODE_COS
:
1805 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1806 if (devinfo
->gen
>= 6) {
1807 assert(inst
->mlen
== 0);
1808 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
1809 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
1810 src
[0], brw_null_reg());
1812 assert(inst
->mlen
>= 1);
1813 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
1815 brw_math_function(inst
->opcode
),
1816 inst
->base_mrf
, src
[0],
1817 BRW_MATH_PRECISION_FULL
);
1820 case SHADER_OPCODE_INT_QUOTIENT
:
1821 case SHADER_OPCODE_INT_REMAINDER
:
1822 case SHADER_OPCODE_POW
:
1823 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1824 if (devinfo
->gen
>= 6) {
1825 assert(inst
->mlen
== 0);
1826 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
1827 inst
->exec_size
== 8);
1828 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1830 assert(inst
->mlen
>= 1);
1831 assert(inst
->exec_size
== 8);
1832 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
1833 inst
->base_mrf
, src
[0],
1834 BRW_MATH_PRECISION_FULL
);
1837 case FS_OPCODE_CINTERP
:
1838 brw_MOV(p
, dst
, src
[0]);
1840 case FS_OPCODE_LINTERP
:
1841 generate_linterp(inst
, dst
, src
);
1843 case FS_OPCODE_PIXEL_X
:
1844 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1845 src
[0].subnr
= 0 * type_sz(src
[0].type
);
1846 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1848 case FS_OPCODE_PIXEL_Y
:
1849 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1850 src
[0].subnr
= 4 * type_sz(src
[0].type
);
1851 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1853 case FS_OPCODE_GET_BUFFER_SIZE
:
1854 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
1856 case SHADER_OPCODE_TEX
:
1858 case SHADER_OPCODE_TXD
:
1859 case SHADER_OPCODE_TXF
:
1860 case SHADER_OPCODE_TXF_LZ
:
1861 case SHADER_OPCODE_TXF_CMS
:
1862 case SHADER_OPCODE_TXF_CMS_W
:
1863 case SHADER_OPCODE_TXF_UMS
:
1864 case SHADER_OPCODE_TXF_MCS
:
1865 case SHADER_OPCODE_TXL
:
1866 case SHADER_OPCODE_TXL_LZ
:
1867 case SHADER_OPCODE_TXS
:
1868 case SHADER_OPCODE_LOD
:
1869 case SHADER_OPCODE_TG4
:
1870 case SHADER_OPCODE_TG4_OFFSET
:
1871 case SHADER_OPCODE_SAMPLEINFO
:
1872 generate_tex(inst
, dst
, src
[0], src
[1], src
[2]);
1874 case FS_OPCODE_DDX_COARSE
:
1875 case FS_OPCODE_DDX_FINE
:
1876 generate_ddx(inst
->opcode
, dst
, src
[0]);
1878 case FS_OPCODE_DDY_COARSE
:
1879 case FS_OPCODE_DDY_FINE
:
1880 generate_ddy(inst
->opcode
, dst
, src
[0]);
1883 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1884 generate_scratch_write(inst
, src
[0]);
1888 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1889 generate_scratch_read(inst
, dst
);
1893 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
1894 generate_scratch_read_gen7(inst
, dst
);
1898 case SHADER_OPCODE_MOV_INDIRECT
:
1899 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
1902 case SHADER_OPCODE_URB_READ_SIMD8
:
1903 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
1904 generate_urb_read(inst
, dst
, src
[0]);
1907 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1908 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
1909 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
1910 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
1911 generate_urb_write(inst
, src
[0]);
1914 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1915 assert(inst
->force_writemask_all
);
1916 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1919 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
1920 assert(inst
->force_writemask_all
);
1921 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1924 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1925 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
1928 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
1929 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1932 case FS_OPCODE_REP_FB_WRITE
:
1933 case FS_OPCODE_FB_WRITE
:
1934 generate_fb_write(inst
, src
[0]);
1937 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
1938 generate_mov_dispatch_to_flags(inst
);
1941 case FS_OPCODE_DISCARD_JUMP
:
1942 generate_discard_jump(inst
);
1945 case SHADER_OPCODE_SHADER_TIME_ADD
:
1946 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
1949 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1950 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1951 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
,
1952 inst
->mlen
, !inst
->dst
.is_null());
1955 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1956 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1957 brw_untyped_surface_read(p
, dst
, src
[0], src
[1],
1958 inst
->mlen
, src
[2].ud
);
1961 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
1962 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1963 brw_untyped_surface_write(p
, src
[0], src
[1],
1964 inst
->mlen
, src
[2].ud
);
1967 case SHADER_OPCODE_TYPED_ATOMIC
:
1968 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1969 brw_typed_atomic(p
, dst
, src
[0], src
[1],
1970 src
[2].ud
, inst
->mlen
, !inst
->dst
.is_null());
1973 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1974 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1975 brw_typed_surface_read(p
, dst
, src
[0], src
[1],
1976 inst
->mlen
, src
[2].ud
);
1979 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
1980 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1981 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
, src
[2].ud
);
1984 case SHADER_OPCODE_MEMORY_FENCE
:
1985 brw_memory_fence(p
, dst
);
1988 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
1989 generate_set_simd4x2_offset(inst
, dst
, src
[0]);
1992 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1993 brw_find_live_channel(p
, dst
);
1996 case SHADER_OPCODE_BROADCAST
:
1997 brw_broadcast(p
, dst
, src
[0], src
[1]);
2000 case FS_OPCODE_SET_SAMPLE_ID
:
2001 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2004 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2005 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2008 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
2009 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
2010 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
2013 case FS_OPCODE_PLACEHOLDER_HALT
:
2014 /* This is the place where the final HALT needs to be inserted if
2015 * we've emitted any discards. If not, this will emit no code.
2017 if (!patch_discard_jumps_to_fb_writes()) {
2018 if (unlikely(debug_flag
)) {
2019 annotation
.ann_count
--;
2024 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
2025 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2026 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID
);
2029 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2030 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2031 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2034 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2035 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2036 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2039 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2040 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2041 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2044 case CS_OPCODE_CS_TERMINATE
:
2045 generate_cs_terminate(inst
, src
[0]);
2048 case SHADER_OPCODE_BARRIER
:
2049 generate_barrier(inst
, src
[0]);
2053 unreachable("Unsupported opcode");
2055 case SHADER_OPCODE_LOAD_PAYLOAD
:
2056 unreachable("Should be lowered by lower_load_payload()");
2059 if (multiple_instructions_emitted
)
2062 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2063 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2064 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2065 "emitting more than 1 instruction");
2067 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2069 if (inst
->conditional_mod
)
2070 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2071 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2072 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2077 annotation_finalize(&annotation
, p
->next_insn_offset
);
2080 bool validated
= brw_validate_instructions(p
, start_offset
, &annotation
);
2082 if (unlikely(debug_flag
))
2083 brw_validate_instructions(p
, start_offset
, &annotation
);
2086 int before_size
= p
->next_insn_offset
- start_offset
;
2087 brw_compact_instructions(p
, start_offset
, annotation
.ann_count
,
2089 int after_size
= p
->next_insn_offset
- start_offset
;
2091 if (unlikely(debug_flag
)) {
2092 fprintf(stderr
, "Native code for %s\n"
2093 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2094 " bytes (%.0f%%)\n",
2095 shader_name
, dispatch_width
, before_size
/ 16, loop_count
, cfg
->cycle_count
,
2096 spill_count
, fill_count
, promoted_constants
, before_size
, after_size
,
2097 100.0f
* (before_size
- after_size
) / before_size
);
2099 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
,
2101 ralloc_free(annotation
.mem_ctx
);
2105 compiler
->shader_debug_log(log_data
,
2106 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2107 "%d:%d spills:fills, Promoted %u constants, "
2108 "compacted %d to %d bytes.",
2109 _mesa_shader_stage_to_abbrev(stage
),
2110 dispatch_width
, before_size
/ 16,
2111 loop_count
, cfg
->cycle_count
, spill_count
,
2112 fill_count
, promoted_constants
, before_size
,
2115 return start_offset
;
2119 fs_generator::get_assembly(unsigned int *assembly_size
)
2121 return brw_get_program(p
, assembly_size
);