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i965/fs: Add support for sub-register byte offsets to the FS back-end IR.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 fs_generator::fs_generator(struct brw_context *brw,
40 struct brw_wm_compile *c,
41 struct gl_shader_program *prog,
42 struct gl_fragment_program *fp,
43 bool dual_source_output)
44
45 : brw(brw), c(c), prog(prog), fp(fp), dual_source_output(dual_source_output)
46 {
47 ctx = &brw->ctx;
48
49 mem_ctx = c;
50
51 p = rzalloc(mem_ctx, struct brw_compile);
52 brw_init_compile(brw, p, mem_ctx);
53 }
54
55 fs_generator::~fs_generator()
56 {
57 }
58
59 void
60 fs_generator::mark_surface_used(unsigned surf_index)
61 {
62 assert(surf_index < BRW_MAX_SURFACES);
63
64 c->prog_data.base.binding_table.size_bytes =
65 MAX2(c->prog_data.base.binding_table.size_bytes, (surf_index + 1) * 4);
66 }
67
68 void
69 fs_generator::patch_discard_jumps_to_fb_writes()
70 {
71 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
72 return;
73
74 /* There is a somewhat strange undocumented requirement of using
75 * HALT, according to the simulator. If some channel has HALTed to
76 * a particular UIP, then by the end of the program, every channel
77 * must have HALTed to that UIP. Furthermore, the tracking is a
78 * stack, so you can't do the final halt of a UIP after starting
79 * halting to a new UIP.
80 *
81 * Symptoms of not emitting this instruction on actual hardware
82 * included GPU hangs and sparkly rendering on the piglit discard
83 * tests.
84 */
85 struct brw_instruction *last_halt = gen6_HALT(p);
86 last_halt->bits3.break_cont.uip = 2;
87 last_halt->bits3.break_cont.jip = 2;
88
89 int ip = p->nr_insn;
90
91 foreach_list(node, &this->discard_halt_patches) {
92 ip_record *patch_ip = (ip_record *)node;
93 struct brw_instruction *patch = &p->store[patch_ip->ip];
94
95 assert(patch->header.opcode == BRW_OPCODE_HALT);
96 /* HALT takes a half-instruction distance from the pre-incremented IP. */
97 patch->bits3.break_cont.uip = (ip - patch_ip->ip) * 2;
98 }
99
100 this->discard_halt_patches.make_empty();
101 }
102
103 void
104 fs_generator::generate_fb_write(fs_inst *inst)
105 {
106 bool eot = inst->eot;
107 struct brw_reg implied_header;
108 uint32_t msg_control;
109
110 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
111 * move, here's g1.
112 */
113 brw_push_insn_state(p);
114 brw_set_mask_control(p, BRW_MASK_DISABLE);
115 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
116
117 if ((fp && fp->UsesKill) || c->key.alpha_test_func) {
118 struct brw_reg pixel_mask;
119
120 if (brw->gen >= 6)
121 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
122 else
123 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
124
125 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
126 }
127
128 if (inst->header_present) {
129 if (brw->gen >= 6) {
130 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
131 brw_MOV(p,
132 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
133 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
134 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
135
136 if (inst->target > 0 && c->key.replicate_alpha) {
137 /* Set "Source0 Alpha Present to RenderTarget" bit in message
138 * header.
139 */
140 brw_OR(p,
141 vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)),
142 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
143 brw_imm_ud(0x1 << 11));
144 }
145
146 if (inst->target > 0) {
147 /* Set the render target index for choosing BLEND_STATE. */
148 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
149 inst->base_mrf, 2),
150 BRW_REGISTER_TYPE_UD),
151 brw_imm_ud(inst->target));
152 }
153
154 implied_header = brw_null_reg();
155 } else {
156 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
157
158 brw_MOV(p,
159 brw_message_reg(inst->base_mrf + 1),
160 brw_vec8_grf(1, 0));
161 }
162 } else {
163 implied_header = brw_null_reg();
164 }
165
166 if (this->dual_source_output)
167 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
168 else if (dispatch_width == 16)
169 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
170 else
171 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
172
173 brw_pop_insn_state(p);
174
175 uint32_t surf_index =
176 c->prog_data.binding_table.render_target_start + inst->target;
177 brw_fb_WRITE(p,
178 dispatch_width,
179 inst->base_mrf,
180 implied_header,
181 msg_control,
182 surf_index,
183 inst->mlen,
184 0,
185 eot,
186 inst->header_present);
187
188 mark_surface_used(surf_index);
189 }
190
191 void
192 fs_generator::generate_blorp_fb_write(fs_inst *inst)
193 {
194 brw_fb_WRITE(p,
195 16 /* dispatch_width */,
196 inst->base_mrf,
197 brw_reg_from_fs_reg(&inst->src[0]),
198 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
199 inst->target,
200 inst->mlen,
201 0,
202 true,
203 inst->header_present);
204 }
205
206 /* Computes the integer pixel x,y values from the origin.
207 *
208 * This is the basis of gl_FragCoord computation, but is also used
209 * pre-gen6 for computing the deltas from v0 for computing
210 * interpolation.
211 */
212 void
213 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
214 {
215 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
216 struct brw_reg src;
217 struct brw_reg deltas;
218
219 if (is_x) {
220 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
221 deltas = brw_imm_v(0x10101010);
222 } else {
223 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
224 deltas = brw_imm_v(0x11001100);
225 }
226
227 if (dispatch_width == 16) {
228 dst = vec16(dst);
229 }
230
231 /* We do this SIMD8 or SIMD16, but since the destination is UW we
232 * don't do compression in the SIMD16 case.
233 */
234 brw_push_insn_state(p);
235 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
236 brw_ADD(p, dst, src, deltas);
237 brw_pop_insn_state(p);
238 }
239
240 void
241 fs_generator::generate_linterp(fs_inst *inst,
242 struct brw_reg dst, struct brw_reg *src)
243 {
244 struct brw_reg delta_x = src[0];
245 struct brw_reg delta_y = src[1];
246 struct brw_reg interp = src[2];
247
248 if (brw->has_pln &&
249 delta_y.nr == delta_x.nr + 1 &&
250 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
251 brw_PLN(p, dst, interp, delta_x);
252 } else {
253 brw_LINE(p, brw_null_reg(), interp, delta_x);
254 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
255 }
256 }
257
258 void
259 fs_generator::generate_math1_gen7(fs_inst *inst,
260 struct brw_reg dst,
261 struct brw_reg src0)
262 {
263 assert(inst->mlen == 0);
264 brw_math(p, dst,
265 brw_math_function(inst->opcode),
266 0, src0,
267 BRW_MATH_DATA_VECTOR,
268 BRW_MATH_PRECISION_FULL);
269 }
270
271 void
272 fs_generator::generate_math2_gen7(fs_inst *inst,
273 struct brw_reg dst,
274 struct brw_reg src0,
275 struct brw_reg src1)
276 {
277 assert(inst->mlen == 0);
278 brw_math2(p, dst, brw_math_function(inst->opcode), src0, src1);
279 }
280
281 void
282 fs_generator::generate_math1_gen6(fs_inst *inst,
283 struct brw_reg dst,
284 struct brw_reg src0)
285 {
286 int op = brw_math_function(inst->opcode);
287
288 assert(inst->mlen == 0);
289
290 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
291 brw_math(p, dst,
292 op,
293 0, src0,
294 BRW_MATH_DATA_VECTOR,
295 BRW_MATH_PRECISION_FULL);
296
297 if (dispatch_width == 16) {
298 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
299 brw_math(p, sechalf(dst),
300 op,
301 0, sechalf(src0),
302 BRW_MATH_DATA_VECTOR,
303 BRW_MATH_PRECISION_FULL);
304 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
305 }
306 }
307
308 void
309 fs_generator::generate_math2_gen6(fs_inst *inst,
310 struct brw_reg dst,
311 struct brw_reg src0,
312 struct brw_reg src1)
313 {
314 int op = brw_math_function(inst->opcode);
315
316 assert(inst->mlen == 0);
317
318 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
319 brw_math2(p, dst, op, src0, src1);
320
321 if (dispatch_width == 16) {
322 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
323 brw_math2(p, sechalf(dst), op, sechalf(src0), sechalf(src1));
324 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
325 }
326 }
327
328 void
329 fs_generator::generate_math_gen4(fs_inst *inst,
330 struct brw_reg dst,
331 struct brw_reg src)
332 {
333 int op = brw_math_function(inst->opcode);
334
335 assert(inst->mlen >= 1);
336
337 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
338 brw_math(p, dst,
339 op,
340 inst->base_mrf, src,
341 BRW_MATH_DATA_VECTOR,
342 BRW_MATH_PRECISION_FULL);
343
344 if (dispatch_width == 16) {
345 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
346 brw_math(p, sechalf(dst),
347 op,
348 inst->base_mrf + 1, sechalf(src),
349 BRW_MATH_DATA_VECTOR,
350 BRW_MATH_PRECISION_FULL);
351
352 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
353 }
354 }
355
356 void
357 fs_generator::generate_math_g45(fs_inst *inst,
358 struct brw_reg dst,
359 struct brw_reg src)
360 {
361 if (inst->opcode == SHADER_OPCODE_POW ||
362 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
363 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
364 generate_math_gen4(inst, dst, src);
365 return;
366 }
367
368 int op = brw_math_function(inst->opcode);
369
370 assert(inst->mlen >= 1);
371
372 brw_math(p, dst,
373 op,
374 inst->base_mrf, src,
375 BRW_MATH_DATA_VECTOR,
376 BRW_MATH_PRECISION_FULL);
377 }
378
379 void
380 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
381 {
382 int msg_type = -1;
383 int rlen = 4;
384 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
385 uint32_t return_format;
386
387 switch (dst.type) {
388 case BRW_REGISTER_TYPE_D:
389 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
390 break;
391 case BRW_REGISTER_TYPE_UD:
392 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
393 break;
394 default:
395 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
396 break;
397 }
398
399 if (dispatch_width == 16 &&
400 !inst->force_uncompressed && !inst->force_sechalf)
401 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
402
403 if (brw->gen >= 5) {
404 switch (inst->opcode) {
405 case SHADER_OPCODE_TEX:
406 if (inst->shadow_compare) {
407 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
408 } else {
409 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
410 }
411 break;
412 case FS_OPCODE_TXB:
413 if (inst->shadow_compare) {
414 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
415 } else {
416 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
417 }
418 break;
419 case SHADER_OPCODE_TXL:
420 if (inst->shadow_compare) {
421 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
422 } else {
423 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
424 }
425 break;
426 case SHADER_OPCODE_TXS:
427 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
428 break;
429 case SHADER_OPCODE_TXD:
430 if (inst->shadow_compare) {
431 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
432 assert(brw->is_haswell);
433 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
434 } else {
435 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
436 }
437 break;
438 case SHADER_OPCODE_TXF:
439 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
440 break;
441 case SHADER_OPCODE_TXF_CMS:
442 if (brw->gen >= 7)
443 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
444 else
445 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
446 break;
447 case SHADER_OPCODE_TXF_UMS:
448 assert(brw->gen >= 7);
449 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
450 break;
451 case SHADER_OPCODE_TXF_MCS:
452 assert(brw->gen >= 7);
453 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
454 break;
455 case SHADER_OPCODE_LOD:
456 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
457 break;
458 case SHADER_OPCODE_TG4:
459 if (inst->shadow_compare) {
460 assert(brw->gen >= 7);
461 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
462 } else {
463 assert(brw->gen >= 6);
464 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
465 }
466 break;
467 case SHADER_OPCODE_TG4_OFFSET:
468 assert(brw->gen >= 7);
469 if (inst->shadow_compare) {
470 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
471 } else {
472 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
473 }
474 break;
475 default:
476 assert(!"not reached");
477 break;
478 }
479 } else {
480 switch (inst->opcode) {
481 case SHADER_OPCODE_TEX:
482 /* Note that G45 and older determines shadow compare and dispatch width
483 * from message length for most messages.
484 */
485 assert(dispatch_width == 8);
486 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
487 if (inst->shadow_compare) {
488 assert(inst->mlen == 6);
489 } else {
490 assert(inst->mlen <= 4);
491 }
492 break;
493 case FS_OPCODE_TXB:
494 if (inst->shadow_compare) {
495 assert(inst->mlen == 6);
496 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
497 } else {
498 assert(inst->mlen == 9);
499 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
500 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
501 }
502 break;
503 case SHADER_OPCODE_TXL:
504 if (inst->shadow_compare) {
505 assert(inst->mlen == 6);
506 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
507 } else {
508 assert(inst->mlen == 9);
509 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
510 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
511 }
512 break;
513 case SHADER_OPCODE_TXD:
514 /* There is no sample_d_c message; comparisons are done manually */
515 assert(inst->mlen == 7 || inst->mlen == 10);
516 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
517 break;
518 case SHADER_OPCODE_TXF:
519 assert(inst->mlen == 9);
520 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
521 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
522 break;
523 case SHADER_OPCODE_TXS:
524 assert(inst->mlen == 3);
525 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
526 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
527 break;
528 default:
529 assert(!"not reached");
530 break;
531 }
532 }
533 assert(msg_type != -1);
534
535 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
536 rlen = 8;
537 dst = vec16(dst);
538 }
539
540 if (brw->gen >= 7 && inst->header_present && dispatch_width == 16) {
541 /* The send-from-GRF for SIMD16 texturing with a header has an extra
542 * hardware register allocated to it, which we need to skip over (since
543 * our coordinates in the payload are in the even-numbered registers,
544 * and the header comes right before the first one).
545 */
546 assert(src.file == BRW_GENERAL_REGISTER_FILE);
547 src.nr++;
548 }
549
550 /* Load the message header if present. If there's a texture offset,
551 * we need to set it up explicitly and load the offset bitfield.
552 * Otherwise, we can use an implied move from g0 to the first message reg.
553 */
554 if (inst->header_present) {
555 if (brw->gen < 6 && !inst->texture_offset) {
556 /* Set up an implied move from g0 to the MRF. */
557 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
558 } else {
559 struct brw_reg header_reg;
560
561 if (brw->gen >= 7) {
562 header_reg = src;
563 } else {
564 assert(inst->base_mrf != -1);
565 header_reg = brw_message_reg(inst->base_mrf);
566 }
567
568 brw_push_insn_state(p);
569 brw_set_mask_control(p, BRW_MASK_DISABLE);
570 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
571 /* Explicitly set up the message header by copying g0 to the MRF. */
572 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
573
574 if (inst->texture_offset) {
575 /* Set the offset bits in DWord 2. */
576 brw_MOV(p, get_element_ud(header_reg, 2),
577 brw_imm_ud(inst->texture_offset));
578 }
579
580 if (inst->sampler >= 16) {
581 /* The "Sampler Index" field can only store values between 0 and 15.
582 * However, we can add an offset to the "Sampler State Pointer"
583 * field, effectively selecting a different set of 16 samplers.
584 *
585 * The "Sampler State Pointer" needs to be aligned to a 32-byte
586 * offset, and each sampler state is only 16-bytes, so we can't
587 * exclusively use the offset - we have to use both.
588 */
589 assert(brw->is_haswell); /* field only exists on Haswell */
590 brw_ADD(p,
591 get_element_ud(header_reg, 3),
592 get_element_ud(brw_vec8_grf(0, 0), 3),
593 brw_imm_ud(16 * (inst->sampler / 16) *
594 sizeof(gen7_sampler_state)));
595 }
596 brw_pop_insn_state(p);
597 }
598 }
599
600 uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
601 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
602 ? c->prog_data.base.binding_table.gather_texture_start
603 : c->prog_data.base.binding_table.texture_start) + inst->sampler;
604
605 brw_SAMPLE(p,
606 retype(dst, BRW_REGISTER_TYPE_UW),
607 inst->base_mrf,
608 src,
609 surface_index,
610 inst->sampler % 16,
611 msg_type,
612 rlen,
613 inst->mlen,
614 inst->header_present,
615 simd_mode,
616 return_format);
617
618 mark_surface_used(surface_index);
619 }
620
621
622 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
623 * looking like:
624 *
625 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
626 *
627 * Ideally, we want to produce:
628 *
629 * DDX DDY
630 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
631 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
632 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
633 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
634 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
635 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
636 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
637 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
638 *
639 * and add another set of two more subspans if in 16-pixel dispatch mode.
640 *
641 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
642 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
643 * pair. But the ideal approximation may impose a huge performance cost on
644 * sample_d. On at least Haswell, sample_d instruction does some
645 * optimizations if the same LOD is used for all pixels in the subspan.
646 *
647 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
648 * appropriate swizzling.
649 */
650 void
651 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
652 {
653 unsigned vstride, width;
654
655 if (c->key.high_quality_derivatives) {
656 /* produce accurate derivatives */
657 vstride = BRW_VERTICAL_STRIDE_2;
658 width = BRW_WIDTH_2;
659 }
660 else {
661 /* replicate the derivative at the top-left pixel to other pixels */
662 vstride = BRW_VERTICAL_STRIDE_4;
663 width = BRW_WIDTH_4;
664 }
665
666 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
667 BRW_REGISTER_TYPE_F,
668 vstride,
669 width,
670 BRW_HORIZONTAL_STRIDE_0,
671 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
672 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
673 BRW_REGISTER_TYPE_F,
674 vstride,
675 width,
676 BRW_HORIZONTAL_STRIDE_0,
677 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
678 brw_ADD(p, dst, src0, negate(src1));
679 }
680
681 /* The negate_value boolean is used to negate the derivative computation for
682 * FBOs, since they place the origin at the upper left instead of the lower
683 * left.
684 */
685 void
686 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
687 bool negate_value)
688 {
689 if (c->key.high_quality_derivatives) {
690 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
691 * Region Restrictions):
692 *
693 * In Align16 access mode, SIMD16 is not allowed for DW operations
694 * and SIMD8 is not allowed for DF operations.
695 *
696 * In this context, "DW operations" means "operations acting on 32-bit
697 * values", so it includes operations on floats.
698 *
699 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
700 * (Instruction Compression -> Rules and Restrictions):
701 *
702 * A compressed instruction must be in Align1 access mode. Align16
703 * mode instructions cannot be compressed.
704 *
705 * Similar text exists in the g45 PRM.
706 *
707 * On these platforms, if we're building a SIMD16 shader, we need to
708 * manually unroll to a pair of SIMD8 instructions.
709 */
710 bool unroll_to_simd8 =
711 (dispatch_width == 16 &&
712 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
713
714 /* produce accurate derivatives */
715 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
716 BRW_REGISTER_TYPE_F,
717 BRW_VERTICAL_STRIDE_4,
718 BRW_WIDTH_4,
719 BRW_HORIZONTAL_STRIDE_1,
720 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
721 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
722 BRW_REGISTER_TYPE_F,
723 BRW_VERTICAL_STRIDE_4,
724 BRW_WIDTH_4,
725 BRW_HORIZONTAL_STRIDE_1,
726 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
727 brw_push_insn_state(p);
728 brw_set_access_mode(p, BRW_ALIGN_16);
729 if (unroll_to_simd8)
730 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
731 if (negate_value)
732 brw_ADD(p, dst, src1, negate(src0));
733 else
734 brw_ADD(p, dst, src0, negate(src1));
735 if (unroll_to_simd8) {
736 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
737 src0 = sechalf(src0);
738 src1 = sechalf(src1);
739 dst = sechalf(dst);
740 if (negate_value)
741 brw_ADD(p, dst, src1, negate(src0));
742 else
743 brw_ADD(p, dst, src0, negate(src1));
744 }
745 brw_pop_insn_state(p);
746 } else {
747 /* replicate the derivative at the top-left pixel to other pixels */
748 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
749 BRW_REGISTER_TYPE_F,
750 BRW_VERTICAL_STRIDE_4,
751 BRW_WIDTH_4,
752 BRW_HORIZONTAL_STRIDE_0,
753 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
754 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
755 BRW_REGISTER_TYPE_F,
756 BRW_VERTICAL_STRIDE_4,
757 BRW_WIDTH_4,
758 BRW_HORIZONTAL_STRIDE_0,
759 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
760 if (negate_value)
761 brw_ADD(p, dst, src1, negate(src0));
762 else
763 brw_ADD(p, dst, src0, negate(src1));
764 }
765 }
766
767 void
768 fs_generator::generate_discard_jump(fs_inst *inst)
769 {
770 assert(brw->gen >= 6);
771
772 /* This HALT will be patched up at FB write time to point UIP at the end of
773 * the program, and at brw_uip_jip() JIP will be set to the end of the
774 * current block (or the program).
775 */
776 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
777
778 brw_push_insn_state(p);
779 brw_set_mask_control(p, BRW_MASK_DISABLE);
780 gen6_HALT(p);
781 brw_pop_insn_state(p);
782 }
783
784 void
785 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
786 {
787 assert(inst->mlen != 0);
788
789 brw_MOV(p,
790 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
791 retype(src, BRW_REGISTER_TYPE_UD));
792 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
793 dispatch_width / 8, inst->offset);
794 }
795
796 void
797 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
798 {
799 assert(inst->mlen != 0);
800
801 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
802 dispatch_width / 8, inst->offset);
803 }
804
805 void
806 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
807 {
808 gen7_block_read_scratch(p, dst, dispatch_width / 8, inst->offset);
809 }
810
811 void
812 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
813 struct brw_reg dst,
814 struct brw_reg index,
815 struct brw_reg offset)
816 {
817 assert(inst->mlen != 0);
818
819 assert(index.file == BRW_IMMEDIATE_VALUE &&
820 index.type == BRW_REGISTER_TYPE_UD);
821 uint32_t surf_index = index.dw1.ud;
822
823 assert(offset.file == BRW_IMMEDIATE_VALUE &&
824 offset.type == BRW_REGISTER_TYPE_UD);
825 uint32_t read_offset = offset.dw1.ud;
826
827 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
828 read_offset, surf_index);
829
830 mark_surface_used(surf_index);
831 }
832
833 void
834 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
835 struct brw_reg dst,
836 struct brw_reg index,
837 struct brw_reg offset)
838 {
839 assert(inst->mlen == 0);
840
841 assert(index.file == BRW_IMMEDIATE_VALUE &&
842 index.type == BRW_REGISTER_TYPE_UD);
843 uint32_t surf_index = index.dw1.ud;
844
845 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
846 /* Reference just the dword we need, to avoid angering validate_reg(). */
847 offset = brw_vec1_grf(offset.nr, 0);
848
849 brw_push_insn_state(p);
850 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
851 brw_set_mask_control(p, BRW_MASK_DISABLE);
852 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
853 brw_pop_insn_state(p);
854
855 /* We use the SIMD4x2 mode because we want to end up with 4 components in
856 * the destination loaded consecutively from the same offset (which appears
857 * in the first component, and the rest are ignored).
858 */
859 dst.width = BRW_WIDTH_4;
860 brw_set_dest(p, send, dst);
861 brw_set_src0(p, send, offset);
862 brw_set_sampler_message(p, send,
863 surf_index,
864 0, /* LD message ignores sampler unit */
865 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
866 1, /* rlen */
867 1, /* mlen */
868 false, /* no header */
869 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
870 0);
871
872 mark_surface_used(surf_index);
873 }
874
875 void
876 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
877 struct brw_reg dst,
878 struct brw_reg index,
879 struct brw_reg offset)
880 {
881 assert(brw->gen < 7); /* Should use the gen7 variant. */
882 assert(inst->header_present);
883 assert(inst->mlen);
884
885 assert(index.file == BRW_IMMEDIATE_VALUE &&
886 index.type == BRW_REGISTER_TYPE_UD);
887 uint32_t surf_index = index.dw1.ud;
888
889 uint32_t simd_mode, rlen, msg_type;
890 if (dispatch_width == 16) {
891 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
892 rlen = 8;
893 } else {
894 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
895 rlen = 4;
896 }
897
898 if (brw->gen >= 5)
899 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
900 else {
901 /* We always use the SIMD16 message so that we only have to load U, and
902 * not V or R.
903 */
904 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
905 assert(inst->mlen == 3);
906 assert(inst->regs_written == 8);
907 rlen = 8;
908 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
909 }
910
911 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
912 BRW_REGISTER_TYPE_D);
913 brw_MOV(p, offset_mrf, offset);
914
915 struct brw_reg header = brw_vec8_grf(0, 0);
916 gen6_resolve_implied_move(p, &header, inst->base_mrf);
917
918 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
919 send->header.compression_control = BRW_COMPRESSION_NONE;
920 brw_set_dest(p, send, dst);
921 brw_set_src0(p, send, header);
922 if (brw->gen < 6)
923 send->header.destreg__conditionalmod = inst->base_mrf;
924
925 /* Our surface is set up as floats, regardless of what actual data is
926 * stored in it.
927 */
928 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
929 brw_set_sampler_message(p, send,
930 surf_index,
931 0, /* sampler (unused) */
932 msg_type,
933 rlen,
934 inst->mlen,
935 inst->header_present,
936 simd_mode,
937 return_format);
938
939 mark_surface_used(surf_index);
940 }
941
942 void
943 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
944 struct brw_reg dst,
945 struct brw_reg index,
946 struct brw_reg offset)
947 {
948 assert(brw->gen >= 7);
949 /* Varying-offset pull constant loads are treated as a normal expression on
950 * gen7, so the fact that it's a send message is hidden at the IR level.
951 */
952 assert(!inst->header_present);
953 assert(!inst->mlen);
954
955 assert(index.file == BRW_IMMEDIATE_VALUE &&
956 index.type == BRW_REGISTER_TYPE_UD);
957 uint32_t surf_index = index.dw1.ud;
958
959 uint32_t simd_mode, rlen, mlen;
960 if (dispatch_width == 16) {
961 mlen = 2;
962 rlen = 8;
963 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
964 } else {
965 mlen = 1;
966 rlen = 4;
967 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
968 }
969
970 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
971 brw_set_dest(p, send, dst);
972 brw_set_src0(p, send, offset);
973 brw_set_sampler_message(p, send,
974 surf_index,
975 0, /* LD message ignores sampler unit */
976 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
977 rlen,
978 mlen,
979 false, /* no header */
980 simd_mode,
981 0);
982
983 mark_surface_used(surf_index);
984 }
985
986 /**
987 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
988 * into the flags register (f0.0).
989 *
990 * Used only on Gen6 and above.
991 */
992 void
993 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
994 {
995 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
996 struct brw_reg dispatch_mask;
997
998 if (brw->gen >= 6)
999 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1000 else
1001 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1002
1003 brw_push_insn_state(p);
1004 brw_set_mask_control(p, BRW_MASK_DISABLE);
1005 brw_MOV(p, flags, dispatch_mask);
1006 brw_pop_insn_state(p);
1007 }
1008
1009
1010 static uint32_t brw_file_from_reg(fs_reg *reg)
1011 {
1012 switch (reg->file) {
1013 case GRF:
1014 return BRW_GENERAL_REGISTER_FILE;
1015 case MRF:
1016 return BRW_MESSAGE_REGISTER_FILE;
1017 case IMM:
1018 return BRW_IMMEDIATE_VALUE;
1019 default:
1020 assert(!"not reached");
1021 return BRW_GENERAL_REGISTER_FILE;
1022 }
1023 }
1024
1025 struct brw_reg
1026 brw_reg_from_fs_reg(fs_reg *reg)
1027 {
1028 struct brw_reg brw_reg;
1029
1030 switch (reg->file) {
1031 case GRF:
1032 case MRF:
1033 if (reg->smear == -1) {
1034 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1035 } else {
1036 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, reg->smear);
1037 }
1038 brw_reg = retype(brw_reg, reg->type);
1039 if (reg->sechalf)
1040 brw_reg = sechalf(brw_reg);
1041 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
1042 break;
1043 case IMM:
1044 switch (reg->type) {
1045 case BRW_REGISTER_TYPE_F:
1046 brw_reg = brw_imm_f(reg->imm.f);
1047 break;
1048 case BRW_REGISTER_TYPE_D:
1049 brw_reg = brw_imm_d(reg->imm.i);
1050 break;
1051 case BRW_REGISTER_TYPE_UD:
1052 brw_reg = brw_imm_ud(reg->imm.u);
1053 break;
1054 default:
1055 assert(!"not reached");
1056 brw_reg = brw_null_reg();
1057 break;
1058 }
1059 break;
1060 case HW_REG:
1061 brw_reg = reg->fixed_hw_reg;
1062 break;
1063 case BAD_FILE:
1064 /* Probably unused. */
1065 brw_reg = brw_null_reg();
1066 break;
1067 case UNIFORM:
1068 assert(!"not reached");
1069 brw_reg = brw_null_reg();
1070 break;
1071 default:
1072 assert(!"not reached");
1073 brw_reg = brw_null_reg();
1074 break;
1075 }
1076 if (reg->abs)
1077 brw_reg = brw_abs(brw_reg);
1078 if (reg->negate)
1079 brw_reg = negate(brw_reg);
1080
1081 return brw_reg;
1082 }
1083
1084 /**
1085 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1086 * sampler LD messages.
1087 *
1088 * We don't want to bake it into the send message's code generation because
1089 * that means we don't get a chance to schedule the instructions.
1090 */
1091 void
1092 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1093 struct brw_reg dst,
1094 struct brw_reg value)
1095 {
1096 assert(value.file == BRW_IMMEDIATE_VALUE);
1097
1098 brw_push_insn_state(p);
1099 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1100 brw_set_mask_control(p, BRW_MASK_DISABLE);
1101 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1102 brw_pop_insn_state(p);
1103 }
1104
1105 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1106 * (when mask is passed as a uniform) of register mask before moving it
1107 * to register dst.
1108 */
1109 void
1110 fs_generator::generate_set_omask(fs_inst *inst,
1111 struct brw_reg dst,
1112 struct brw_reg mask)
1113 {
1114 bool stride_8_8_1 =
1115 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1116 mask.width == BRW_WIDTH_8 &&
1117 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1118
1119 bool stride_0_1_0 =
1120 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1121 mask.width == BRW_WIDTH_1 &&
1122 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1123
1124 assert(stride_8_8_1 || stride_0_1_0);
1125 assert(dst.type == BRW_REGISTER_TYPE_UW);
1126
1127 if (dispatch_width == 16)
1128 dst = vec16(dst);
1129 brw_push_insn_state(p);
1130 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1131 brw_set_mask_control(p, BRW_MASK_DISABLE);
1132
1133 if (stride_8_8_1) {
1134 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1135 } else if (stride_0_1_0) {
1136 brw_MOV(p, dst, retype(mask, dst.type));
1137 }
1138 brw_pop_insn_state(p);
1139 }
1140
1141 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1142 * the ADD instruction.
1143 */
1144 void
1145 fs_generator::generate_set_sample_id(fs_inst *inst,
1146 struct brw_reg dst,
1147 struct brw_reg src0,
1148 struct brw_reg src1)
1149 {
1150 assert(dst.type == BRW_REGISTER_TYPE_D ||
1151 dst.type == BRW_REGISTER_TYPE_UD);
1152 assert(src0.type == BRW_REGISTER_TYPE_D ||
1153 src0.type == BRW_REGISTER_TYPE_UD);
1154
1155 brw_push_insn_state(p);
1156 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1157 brw_set_mask_control(p, BRW_MASK_DISABLE);
1158 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1159 brw_ADD(p, dst, src0, reg);
1160 if (dispatch_width == 16)
1161 brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
1162 brw_pop_insn_state(p);
1163 }
1164
1165 /**
1166 * Change the register's data type from UD to W, doubling the strides in order
1167 * to compensate for halving the data type width.
1168 */
1169 static struct brw_reg
1170 ud_reg_to_w(struct brw_reg r)
1171 {
1172 assert(r.type == BRW_REGISTER_TYPE_UD);
1173 r.type = BRW_REGISTER_TYPE_W;
1174
1175 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1176 * doubles the real stride.
1177 */
1178 if (r.hstride != 0)
1179 ++r.hstride;
1180 if (r.vstride != 0)
1181 ++r.vstride;
1182
1183 return r;
1184 }
1185
1186 void
1187 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1188 struct brw_reg dst,
1189 struct brw_reg x,
1190 struct brw_reg y)
1191 {
1192 assert(brw->gen >= 7);
1193 assert(dst.type == BRW_REGISTER_TYPE_UD);
1194 assert(x.type == BRW_REGISTER_TYPE_F);
1195 assert(y.type == BRW_REGISTER_TYPE_F);
1196
1197 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1198 *
1199 * Because this instruction does not have a 16-bit floating-point type,
1200 * the destination data type must be Word (W).
1201 *
1202 * The destination must be DWord-aligned and specify a horizontal stride
1203 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1204 * each destination channel and the upper word is not modified.
1205 */
1206 struct brw_reg dst_w = ud_reg_to_w(dst);
1207
1208 /* Give each 32-bit channel of dst the form below , where "." means
1209 * unchanged.
1210 * 0x....hhhh
1211 */
1212 brw_F32TO16(p, dst_w, y);
1213
1214 /* Now the form:
1215 * 0xhhhh0000
1216 */
1217 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1218
1219 /* And, finally the form of packHalf2x16's output:
1220 * 0xhhhhllll
1221 */
1222 brw_F32TO16(p, dst_w, x);
1223 }
1224
1225 void
1226 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1227 struct brw_reg dst,
1228 struct brw_reg src)
1229 {
1230 assert(brw->gen >= 7);
1231 assert(dst.type == BRW_REGISTER_TYPE_F);
1232 assert(src.type == BRW_REGISTER_TYPE_UD);
1233
1234 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1235 *
1236 * Because this instruction does not have a 16-bit floating-point type,
1237 * the source data type must be Word (W). The destination type must be
1238 * F (Float).
1239 */
1240 struct brw_reg src_w = ud_reg_to_w(src);
1241
1242 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1243 * For the Y case, we wish to access only the upper word; therefore
1244 * a 16-bit subregister offset is needed.
1245 */
1246 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1247 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1248 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1249 src_w.subnr += 2;
1250
1251 brw_F16TO32(p, dst, src_w);
1252 }
1253
1254 void
1255 fs_generator::generate_shader_time_add(fs_inst *inst,
1256 struct brw_reg payload,
1257 struct brw_reg offset,
1258 struct brw_reg value)
1259 {
1260 assert(brw->gen >= 7);
1261 brw_push_insn_state(p);
1262 brw_set_mask_control(p, true);
1263
1264 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1265 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1266 offset.type);
1267 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1268 value.type);
1269
1270 assert(offset.file == BRW_IMMEDIATE_VALUE);
1271 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1272 value.width = BRW_WIDTH_1;
1273 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1274 value.vstride = BRW_VERTICAL_STRIDE_0;
1275 } else {
1276 assert(value.file == BRW_IMMEDIATE_VALUE);
1277 }
1278
1279 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1280 * case, and we don't really care about squeezing every bit of performance
1281 * out of this path, so we just emit the MOVs from here.
1282 */
1283 brw_MOV(p, payload_offset, offset);
1284 brw_MOV(p, payload_value, value);
1285 brw_shader_time_add(p, payload,
1286 c->prog_data.base.binding_table.shader_time_start);
1287 brw_pop_insn_state(p);
1288
1289 mark_surface_used(c->prog_data.base.binding_table.shader_time_start);
1290 }
1291
1292 void
1293 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1294 struct brw_reg atomic_op,
1295 struct brw_reg surf_index)
1296 {
1297 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1298 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1299 surf_index.file == BRW_IMMEDIATE_VALUE &&
1300 surf_index.type == BRW_REGISTER_TYPE_UD);
1301
1302 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1303 atomic_op.dw1.ud, surf_index.dw1.ud,
1304 inst->mlen, dispatch_width / 8);
1305
1306 mark_surface_used(surf_index.dw1.ud);
1307 }
1308
1309 void
1310 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1311 struct brw_reg surf_index)
1312 {
1313 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1314 surf_index.type == BRW_REGISTER_TYPE_UD);
1315
1316 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1317 surf_index.dw1.ud,
1318 inst->mlen, dispatch_width / 8);
1319
1320 mark_surface_used(surf_index.dw1.ud);
1321 }
1322
1323 void
1324 fs_generator::generate_code(exec_list *instructions, FILE *dump_file)
1325 {
1326 int last_native_insn_offset = p->next_insn_offset;
1327 const char *last_annotation_string = NULL;
1328 const void *last_annotation_ir = NULL;
1329
1330 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1331 if (prog) {
1332 printf("Native code for fragment shader %d (SIMD%d dispatch):\n",
1333 prog->Name, dispatch_width);
1334 } else if (fp) {
1335 printf("Native code for fragment program %d (SIMD%d dispatch):\n",
1336 fp->Base.Id, dispatch_width);
1337 } else {
1338 printf("Native code for blorp program (SIMD%d dispatch):\n",
1339 dispatch_width);
1340 }
1341 }
1342
1343 cfg_t *cfg = NULL;
1344 if (unlikely(INTEL_DEBUG & DEBUG_WM))
1345 cfg = new(mem_ctx) cfg_t(instructions);
1346
1347 foreach_list(node, instructions) {
1348 fs_inst *inst = (fs_inst *)node;
1349 struct brw_reg src[3], dst;
1350
1351 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1352 foreach_list(node, &cfg->block_list) {
1353 bblock_link *link = (bblock_link *)node;
1354 bblock_t *block = link->block;
1355
1356 if (block->start == inst) {
1357 printf(" START B%d", block->block_num);
1358 foreach_list(predecessor_node, &block->parents) {
1359 bblock_link *predecessor_link =
1360 (bblock_link *)predecessor_node;
1361 bblock_t *predecessor_block = predecessor_link->block;
1362 printf(" <-B%d", predecessor_block->block_num);
1363 }
1364 printf("\n");
1365 }
1366 }
1367
1368 if (last_annotation_ir != inst->ir) {
1369 last_annotation_ir = inst->ir;
1370 if (last_annotation_ir) {
1371 printf(" ");
1372 if (prog)
1373 ((ir_instruction *)inst->ir)->print();
1374 else {
1375 const prog_instruction *fpi;
1376 fpi = (const prog_instruction *)inst->ir;
1377 printf("%d: ", (int)(fpi - (fp ? fp->Base.Instructions : 0)));
1378 _mesa_fprint_instruction_opt(stdout,
1379 fpi,
1380 0, PROG_PRINT_DEBUG, NULL);
1381 }
1382 printf("\n");
1383 }
1384 }
1385 if (last_annotation_string != inst->annotation) {
1386 last_annotation_string = inst->annotation;
1387 if (last_annotation_string)
1388 printf(" %s\n", last_annotation_string);
1389 }
1390 }
1391
1392 for (unsigned int i = 0; i < 3; i++) {
1393 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1394
1395 /* The accumulator result appears to get used for the
1396 * conditional modifier generation. When negating a UD
1397 * value, there is a 33rd bit generated for the sign in the
1398 * accumulator value, so now you can't check, for example,
1399 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1400 */
1401 assert(!inst->conditional_mod ||
1402 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1403 !inst->src[i].negate);
1404 }
1405 dst = brw_reg_from_fs_reg(&inst->dst);
1406
1407 brw_set_conditionalmod(p, inst->conditional_mod);
1408 brw_set_predicate_control(p, inst->predicate);
1409 brw_set_predicate_inverse(p, inst->predicate_inverse);
1410 brw_set_flag_reg(p, 0, inst->flag_subreg);
1411 brw_set_saturate(p, inst->saturate);
1412 brw_set_mask_control(p, inst->force_writemask_all);
1413
1414 if (inst->force_uncompressed || dispatch_width == 8) {
1415 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1416 } else if (inst->force_sechalf) {
1417 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1418 } else {
1419 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1420 }
1421
1422 switch (inst->opcode) {
1423 case BRW_OPCODE_MOV:
1424 brw_MOV(p, dst, src[0]);
1425 break;
1426 case BRW_OPCODE_ADD:
1427 brw_ADD(p, dst, src[0], src[1]);
1428 break;
1429 case BRW_OPCODE_MUL:
1430 brw_MUL(p, dst, src[0], src[1]);
1431 break;
1432 case BRW_OPCODE_AVG:
1433 brw_AVG(p, dst, src[0], src[1]);
1434 break;
1435 case BRW_OPCODE_MACH:
1436 brw_set_acc_write_control(p, 1);
1437 brw_MACH(p, dst, src[0], src[1]);
1438 brw_set_acc_write_control(p, 0);
1439 break;
1440
1441 case BRW_OPCODE_MAD:
1442 assert(brw->gen >= 6);
1443 brw_set_access_mode(p, BRW_ALIGN_16);
1444 if (dispatch_width == 16 && !brw->is_haswell) {
1445 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1446 brw_MAD(p, dst, src[0], src[1], src[2]);
1447 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1448 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1449 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1450 } else {
1451 brw_MAD(p, dst, src[0], src[1], src[2]);
1452 }
1453 brw_set_access_mode(p, BRW_ALIGN_1);
1454 break;
1455
1456 case BRW_OPCODE_LRP:
1457 assert(brw->gen >= 6);
1458 brw_set_access_mode(p, BRW_ALIGN_16);
1459 if (dispatch_width == 16 && !brw->is_haswell) {
1460 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1461 brw_LRP(p, dst, src[0], src[1], src[2]);
1462 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1463 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1464 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1465 } else {
1466 brw_LRP(p, dst, src[0], src[1], src[2]);
1467 }
1468 brw_set_access_mode(p, BRW_ALIGN_1);
1469 break;
1470
1471 case BRW_OPCODE_FRC:
1472 brw_FRC(p, dst, src[0]);
1473 break;
1474 case BRW_OPCODE_RNDD:
1475 brw_RNDD(p, dst, src[0]);
1476 break;
1477 case BRW_OPCODE_RNDE:
1478 brw_RNDE(p, dst, src[0]);
1479 break;
1480 case BRW_OPCODE_RNDZ:
1481 brw_RNDZ(p, dst, src[0]);
1482 break;
1483
1484 case BRW_OPCODE_AND:
1485 brw_AND(p, dst, src[0], src[1]);
1486 break;
1487 case BRW_OPCODE_OR:
1488 brw_OR(p, dst, src[0], src[1]);
1489 break;
1490 case BRW_OPCODE_XOR:
1491 brw_XOR(p, dst, src[0], src[1]);
1492 break;
1493 case BRW_OPCODE_NOT:
1494 brw_NOT(p, dst, src[0]);
1495 break;
1496 case BRW_OPCODE_ASR:
1497 brw_ASR(p, dst, src[0], src[1]);
1498 break;
1499 case BRW_OPCODE_SHR:
1500 brw_SHR(p, dst, src[0], src[1]);
1501 break;
1502 case BRW_OPCODE_SHL:
1503 brw_SHL(p, dst, src[0], src[1]);
1504 break;
1505 case BRW_OPCODE_F32TO16:
1506 assert(brw->gen >= 7);
1507 brw_F32TO16(p, dst, src[0]);
1508 break;
1509 case BRW_OPCODE_F16TO32:
1510 assert(brw->gen >= 7);
1511 brw_F16TO32(p, dst, src[0]);
1512 break;
1513 case BRW_OPCODE_CMP:
1514 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1515 break;
1516 case BRW_OPCODE_SEL:
1517 brw_SEL(p, dst, src[0], src[1]);
1518 break;
1519 case BRW_OPCODE_BFREV:
1520 assert(brw->gen >= 7);
1521 /* BFREV only supports UD type for src and dst. */
1522 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1523 retype(src[0], BRW_REGISTER_TYPE_UD));
1524 break;
1525 case BRW_OPCODE_FBH:
1526 assert(brw->gen >= 7);
1527 /* FBH only supports UD type for dst. */
1528 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1529 break;
1530 case BRW_OPCODE_FBL:
1531 assert(brw->gen >= 7);
1532 /* FBL only supports UD type for dst. */
1533 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1534 break;
1535 case BRW_OPCODE_CBIT:
1536 assert(brw->gen >= 7);
1537 /* CBIT only supports UD type for dst. */
1538 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1539 break;
1540 case BRW_OPCODE_ADDC:
1541 assert(brw->gen >= 7);
1542 brw_set_acc_write_control(p, 1);
1543 brw_ADDC(p, dst, src[0], src[1]);
1544 brw_set_acc_write_control(p, 0);
1545 break;
1546 case BRW_OPCODE_SUBB:
1547 assert(brw->gen >= 7);
1548 brw_set_acc_write_control(p, 1);
1549 brw_SUBB(p, dst, src[0], src[1]);
1550 brw_set_acc_write_control(p, 0);
1551 break;
1552
1553 case BRW_OPCODE_BFE:
1554 assert(brw->gen >= 7);
1555 brw_set_access_mode(p, BRW_ALIGN_16);
1556 if (dispatch_width == 16 && !brw->is_haswell) {
1557 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1558 brw_BFE(p, dst, src[0], src[1], src[2]);
1559 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1560 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1561 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1562 } else {
1563 brw_BFE(p, dst, src[0], src[1], src[2]);
1564 }
1565 brw_set_access_mode(p, BRW_ALIGN_1);
1566 break;
1567
1568 case BRW_OPCODE_BFI1:
1569 assert(brw->gen >= 7);
1570 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1571 * should
1572 *
1573 * "Force BFI instructions to be executed always in SIMD8."
1574 */
1575 if (dispatch_width == 16 && brw->is_haswell) {
1576 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1577 brw_BFI1(p, dst, src[0], src[1]);
1578 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1579 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1580 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1581 } else {
1582 brw_BFI1(p, dst, src[0], src[1]);
1583 }
1584 break;
1585 case BRW_OPCODE_BFI2:
1586 assert(brw->gen >= 7);
1587 brw_set_access_mode(p, BRW_ALIGN_16);
1588 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1589 * should
1590 *
1591 * "Force BFI instructions to be executed always in SIMD8."
1592 *
1593 * Otherwise we would be able to emit compressed instructions like we
1594 * do for the other three-source instructions.
1595 */
1596 if (dispatch_width == 16) {
1597 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1598 brw_BFI2(p, dst, src[0], src[1], src[2]);
1599 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1600 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1601 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1602 } else {
1603 brw_BFI2(p, dst, src[0], src[1], src[2]);
1604 }
1605 brw_set_access_mode(p, BRW_ALIGN_1);
1606 break;
1607
1608 case BRW_OPCODE_IF:
1609 if (inst->src[0].file != BAD_FILE) {
1610 /* The instruction has an embedded compare (only allowed on gen6) */
1611 assert(brw->gen == 6);
1612 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1613 } else {
1614 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1615 }
1616 break;
1617
1618 case BRW_OPCODE_ELSE:
1619 brw_ELSE(p);
1620 break;
1621 case BRW_OPCODE_ENDIF:
1622 brw_ENDIF(p);
1623 break;
1624
1625 case BRW_OPCODE_DO:
1626 brw_DO(p, BRW_EXECUTE_8);
1627 break;
1628
1629 case BRW_OPCODE_BREAK:
1630 brw_BREAK(p);
1631 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1632 break;
1633 case BRW_OPCODE_CONTINUE:
1634 /* FINISHME: We need to write the loop instruction support still. */
1635 if (brw->gen >= 6)
1636 gen6_CONT(p);
1637 else
1638 brw_CONT(p);
1639 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1640 break;
1641
1642 case BRW_OPCODE_WHILE:
1643 brw_WHILE(p);
1644 break;
1645
1646 case SHADER_OPCODE_RCP:
1647 case SHADER_OPCODE_RSQ:
1648 case SHADER_OPCODE_SQRT:
1649 case SHADER_OPCODE_EXP2:
1650 case SHADER_OPCODE_LOG2:
1651 case SHADER_OPCODE_SIN:
1652 case SHADER_OPCODE_COS:
1653 if (brw->gen >= 7) {
1654 generate_math1_gen7(inst, dst, src[0]);
1655 } else if (brw->gen == 6) {
1656 generate_math1_gen6(inst, dst, src[0]);
1657 } else if (brw->gen == 5 || brw->is_g4x) {
1658 generate_math_g45(inst, dst, src[0]);
1659 } else {
1660 generate_math_gen4(inst, dst, src[0]);
1661 }
1662 break;
1663 case SHADER_OPCODE_INT_QUOTIENT:
1664 case SHADER_OPCODE_INT_REMAINDER:
1665 case SHADER_OPCODE_POW:
1666 if (brw->gen >= 7) {
1667 generate_math2_gen7(inst, dst, src[0], src[1]);
1668 } else if (brw->gen == 6) {
1669 generate_math2_gen6(inst, dst, src[0], src[1]);
1670 } else {
1671 generate_math_gen4(inst, dst, src[0]);
1672 }
1673 break;
1674 case FS_OPCODE_PIXEL_X:
1675 generate_pixel_xy(dst, true);
1676 break;
1677 case FS_OPCODE_PIXEL_Y:
1678 generate_pixel_xy(dst, false);
1679 break;
1680 case FS_OPCODE_CINTERP:
1681 brw_MOV(p, dst, src[0]);
1682 break;
1683 case FS_OPCODE_LINTERP:
1684 generate_linterp(inst, dst, src);
1685 break;
1686 case SHADER_OPCODE_TEX:
1687 case FS_OPCODE_TXB:
1688 case SHADER_OPCODE_TXD:
1689 case SHADER_OPCODE_TXF:
1690 case SHADER_OPCODE_TXF_CMS:
1691 case SHADER_OPCODE_TXF_UMS:
1692 case SHADER_OPCODE_TXF_MCS:
1693 case SHADER_OPCODE_TXL:
1694 case SHADER_OPCODE_TXS:
1695 case SHADER_OPCODE_LOD:
1696 case SHADER_OPCODE_TG4:
1697 case SHADER_OPCODE_TG4_OFFSET:
1698 generate_tex(inst, dst, src[0]);
1699 break;
1700 case FS_OPCODE_DDX:
1701 generate_ddx(inst, dst, src[0]);
1702 break;
1703 case FS_OPCODE_DDY:
1704 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1705 * guarantee that c->key.render_to_fbo is set).
1706 */
1707 assert(fp->UsesDFdy);
1708 generate_ddy(inst, dst, src[0], c->key.render_to_fbo);
1709 break;
1710
1711 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1712 generate_scratch_write(inst, src[0]);
1713 break;
1714
1715 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1716 generate_scratch_read(inst, dst);
1717 break;
1718
1719 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1720 generate_scratch_read_gen7(inst, dst);
1721 break;
1722
1723 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1724 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1725 break;
1726
1727 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1728 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1729 break;
1730
1731 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1732 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1733 break;
1734
1735 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1736 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1737 break;
1738
1739 case FS_OPCODE_FB_WRITE:
1740 generate_fb_write(inst);
1741 break;
1742
1743 case FS_OPCODE_BLORP_FB_WRITE:
1744 generate_blorp_fb_write(inst);
1745 break;
1746
1747 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1748 generate_mov_dispatch_to_flags(inst);
1749 break;
1750
1751 case FS_OPCODE_DISCARD_JUMP:
1752 generate_discard_jump(inst);
1753 break;
1754
1755 case SHADER_OPCODE_SHADER_TIME_ADD:
1756 generate_shader_time_add(inst, src[0], src[1], src[2]);
1757 break;
1758
1759 case SHADER_OPCODE_UNTYPED_ATOMIC:
1760 generate_untyped_atomic(inst, dst, src[0], src[1]);
1761 break;
1762
1763 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1764 generate_untyped_surface_read(inst, dst, src[0]);
1765 break;
1766
1767 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1768 generate_set_simd4x2_offset(inst, dst, src[0]);
1769 break;
1770
1771 case FS_OPCODE_SET_OMASK:
1772 generate_set_omask(inst, dst, src[0]);
1773 break;
1774
1775 case FS_OPCODE_SET_SAMPLE_ID:
1776 generate_set_sample_id(inst, dst, src[0], src[1]);
1777 break;
1778
1779 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1780 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1781 break;
1782
1783 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1784 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1785 generate_unpack_half_2x16_split(inst, dst, src[0]);
1786 break;
1787
1788 case FS_OPCODE_PLACEHOLDER_HALT:
1789 /* This is the place where the final HALT needs to be inserted if
1790 * we've emitted any discards. If not, this will emit no code.
1791 */
1792 patch_discard_jumps_to_fb_writes();
1793 break;
1794
1795 default:
1796 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1797 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1798 opcode_descs[inst->opcode].name);
1799 } else {
1800 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1801 }
1802 abort();
1803 }
1804
1805 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1806 brw_dump_compile(p, stdout,
1807 last_native_insn_offset, p->next_insn_offset);
1808
1809 foreach_list(node, &cfg->block_list) {
1810 bblock_link *link = (bblock_link *)node;
1811 bblock_t *block = link->block;
1812
1813 if (block->end == inst) {
1814 printf(" END B%d", block->block_num);
1815 foreach_list(successor_node, &block->children) {
1816 bblock_link *successor_link =
1817 (bblock_link *)successor_node;
1818 bblock_t *successor_block = successor_link->block;
1819 printf(" ->B%d", successor_block->block_num);
1820 }
1821 printf("\n");
1822 }
1823 }
1824 }
1825
1826 last_native_insn_offset = p->next_insn_offset;
1827 }
1828
1829 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1830 printf("\n");
1831 }
1832
1833 brw_set_uip_jip(p);
1834
1835 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
1836 * emit issues, it doesn't get the jump distances into the output,
1837 * which is often something we want to debug. So this is here in
1838 * case you're doing that.
1839 */
1840 if (dump_file) {
1841 brw_dump_compile(p, dump_file, 0, p->next_insn_offset);
1842 }
1843 }
1844
1845 const unsigned *
1846 fs_generator::generate_assembly(exec_list *simd8_instructions,
1847 exec_list *simd16_instructions,
1848 unsigned *assembly_size,
1849 FILE *dump_file)
1850 {
1851 assert(simd8_instructions || simd16_instructions);
1852
1853 if (simd8_instructions) {
1854 dispatch_width = 8;
1855 generate_code(simd8_instructions, dump_file);
1856 }
1857
1858 if (simd16_instructions) {
1859 /* We have to do a compaction pass now, or the one at the end of
1860 * execution will squash down where our prog_offset start needs
1861 * to be.
1862 */
1863 brw_compact_instructions(p);
1864
1865 /* align to 64 byte boundary. */
1866 while ((p->nr_insn * sizeof(struct brw_instruction)) % 64) {
1867 brw_NOP(p);
1868 }
1869
1870 /* Save off the start of this SIMD16 program */
1871 c->prog_data.prog_offset_16 = p->nr_insn * sizeof(struct brw_instruction);
1872
1873 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1874
1875 dispatch_width = 16;
1876 generate_code(simd16_instructions, dump_file);
1877 }
1878
1879 return brw_get_program(p, assembly_size);
1880 }