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i965/fs: Remove direct fs_generator brw_wm_prog_key dependence
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 fs_generator::fs_generator(struct brw_context *brw,
40 void *mem_ctx,
41 const struct brw_wm_prog_key *key,
42 struct brw_wm_prog_data *prog_data,
43 struct gl_shader_program *shader_prog,
44 struct gl_fragment_program *fp,
45 bool runtime_check_aads_emit,
46 bool debug_flag)
47
48 : brw(brw), stage(MESA_SHADER_FRAGMENT), key(key),
49 prog_data(&prog_data->base), shader_prog(shader_prog),
50 prog(&fp->Base), runtime_check_aads_emit(runtime_check_aads_emit),
51 debug_flag(debug_flag), mem_ctx(mem_ctx)
52 {
53 ctx = &brw->ctx;
54
55 p = rzalloc(mem_ctx, struct brw_compile);
56 brw_init_compile(brw, p, mem_ctx);
57 }
58
59 fs_generator::~fs_generator()
60 {
61 }
62
63 bool
64 fs_generator::patch_discard_jumps_to_fb_writes()
65 {
66 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
67 return false;
68
69 int scale = brw_jump_scale(brw);
70
71 /* There is a somewhat strange undocumented requirement of using
72 * HALT, according to the simulator. If some channel has HALTed to
73 * a particular UIP, then by the end of the program, every channel
74 * must have HALTed to that UIP. Furthermore, the tracking is a
75 * stack, so you can't do the final halt of a UIP after starting
76 * halting to a new UIP.
77 *
78 * Symptoms of not emitting this instruction on actual hardware
79 * included GPU hangs and sparkly rendering on the piglit discard
80 * tests.
81 */
82 brw_inst *last_halt = gen6_HALT(p);
83 brw_inst_set_uip(brw, last_halt, 1 * scale);
84 brw_inst_set_jip(brw, last_halt, 1 * scale);
85
86 int ip = p->nr_insn;
87
88 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
89 brw_inst *patch = &p->store[patch_ip->ip];
90
91 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
92 /* HALT takes a half-instruction distance from the pre-incremented IP. */
93 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
94 }
95
96 this->discard_halt_patches.make_empty();
97 return true;
98 }
99
100 void
101 fs_generator::fire_fb_write(fs_inst *inst,
102 GLuint base_reg,
103 struct brw_reg implied_header,
104 GLuint nr)
105 {
106 uint32_t msg_control;
107
108 assert(stage == MESA_SHADER_FRAGMENT);
109 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
110
111 if (brw->gen < 6) {
112 brw_push_insn_state(p);
113 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
114 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
115 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
116 brw_MOV(p,
117 brw_message_reg(base_reg + 1),
118 brw_vec8_grf(1, 0));
119 brw_pop_insn_state(p);
120 }
121
122 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
123 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
124 else if (prog_data->dual_src_blend)
125 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
126 else if (dispatch_width == 16)
127 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
128 else
129 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
130
131 uint32_t surf_index =
132 prog_data->binding_table.render_target_start + inst->target;
133
134 brw_fb_WRITE(p,
135 dispatch_width,
136 base_reg,
137 implied_header,
138 msg_control,
139 surf_index,
140 nr,
141 0,
142 inst->eot,
143 inst->header_present);
144
145 brw_mark_surface_used(&prog_data->base, surf_index);
146 }
147
148 void
149 fs_generator::generate_fb_write(fs_inst *inst)
150 {
151 assert(stage == MESA_SHADER_FRAGMENT);
152 gl_fragment_program *fp = (gl_fragment_program *) prog;
153 struct brw_reg implied_header;
154
155 assert(stage == MESA_SHADER_FRAGMENT);
156 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
157 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
158
159 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
160 * move, here's g1.
161 */
162 if (inst->header_present) {
163 brw_push_insn_state(p);
164 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
165 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
166 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
167 brw_set_default_flag_reg(p, 0, 0);
168
169 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
170 * present.
171 */
172 if (prog_data->uses_kill || key->alpha_test_func) {
173 struct brw_reg pixel_mask;
174
175 if (brw->gen >= 6)
176 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
177 else
178 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
179
180 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
181 }
182
183 if (brw->gen >= 6) {
184 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
185 brw_MOV(p,
186 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
187 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
188 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
189
190 if (inst->target > 0 && key->replicate_alpha) {
191 /* Set "Source0 Alpha Present to RenderTarget" bit in message
192 * header.
193 */
194 brw_OR(p,
195 vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)),
196 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
197 brw_imm_ud(0x1 << 11));
198 }
199
200 if (inst->target > 0) {
201 /* Set the render target index for choosing BLEND_STATE. */
202 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
203 inst->base_mrf, 2),
204 BRW_REGISTER_TYPE_UD),
205 brw_imm_ud(inst->target));
206 }
207
208 implied_header = brw_null_reg();
209 } else {
210 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
211 }
212
213 brw_pop_insn_state(p);
214 } else {
215 implied_header = brw_null_reg();
216 }
217
218 if (!runtime_check_aads_emit) {
219 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
220 } else {
221 /* This can only happen in gen < 6 */
222 assert(brw->gen < 6);
223
224 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
225
226 /* Check runtime bit to detect if we have to send AA data or not */
227 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
228 brw_AND(p,
229 v1_null_ud,
230 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
231 brw_imm_ud(1<<26));
232 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
233
234 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
235 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
236 {
237 /* Don't send AA data */
238 fire_fb_write(inst, inst->base_mrf+1, implied_header, inst->mlen-1);
239 }
240 brw_land_fwd_jump(p, jmp);
241 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
242 }
243 }
244
245 void
246 fs_generator::generate_blorp_fb_write(fs_inst *inst)
247 {
248 brw_fb_WRITE(p,
249 16 /* dispatch_width */,
250 inst->base_mrf,
251 brw_reg_from_fs_reg(&inst->src[0]),
252 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
253 inst->target,
254 inst->mlen,
255 0,
256 true,
257 inst->header_present);
258 }
259
260 /* Computes the integer pixel x,y values from the origin.
261 *
262 * This is the basis of gl_FragCoord computation, but is also used
263 * pre-gen6 for computing the deltas from v0 for computing
264 * interpolation.
265 */
266 void
267 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
268 {
269 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
270 struct brw_reg src;
271 struct brw_reg deltas;
272
273 if (is_x) {
274 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
275 deltas = brw_imm_v(0x10101010);
276 } else {
277 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
278 deltas = brw_imm_v(0x11001100);
279 }
280
281 if (dispatch_width == 16) {
282 dst = vec16(dst);
283 }
284
285 /* We do this SIMD8 or SIMD16, but since the destination is UW we
286 * don't do compression in the SIMD16 case.
287 */
288 brw_push_insn_state(p);
289 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
290 brw_ADD(p, dst, src, deltas);
291 brw_pop_insn_state(p);
292 }
293
294 void
295 fs_generator::generate_linterp(fs_inst *inst,
296 struct brw_reg dst, struct brw_reg *src)
297 {
298 struct brw_reg delta_x = src[0];
299 struct brw_reg delta_y = src[1];
300 struct brw_reg interp = src[2];
301
302 if (brw->has_pln &&
303 delta_y.nr == delta_x.nr + 1 &&
304 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
305 brw_PLN(p, dst, interp, delta_x);
306 } else {
307 brw_LINE(p, brw_null_reg(), interp, delta_x);
308 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
309 }
310 }
311
312 void
313 fs_generator::generate_math_gen6(fs_inst *inst,
314 struct brw_reg dst,
315 struct brw_reg src0,
316 struct brw_reg src1)
317 {
318 int op = brw_math_function(inst->opcode);
319 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
320
321 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
322 gen6_math(p, dst, op, src0, src1);
323
324 if (dispatch_width == 16) {
325 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
326 gen6_math(p, sechalf(dst), op, sechalf(src0),
327 binop ? sechalf(src1) : brw_null_reg());
328 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
329 }
330 }
331
332 void
333 fs_generator::generate_math_gen4(fs_inst *inst,
334 struct brw_reg dst,
335 struct brw_reg src)
336 {
337 int op = brw_math_function(inst->opcode);
338
339 assert(inst->mlen >= 1);
340
341 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
342 gen4_math(p, dst,
343 op,
344 inst->base_mrf, src,
345 BRW_MATH_DATA_VECTOR,
346 BRW_MATH_PRECISION_FULL);
347
348 if (dispatch_width == 16) {
349 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
350 gen4_math(p, sechalf(dst),
351 op,
352 inst->base_mrf + 1, sechalf(src),
353 BRW_MATH_DATA_VECTOR,
354 BRW_MATH_PRECISION_FULL);
355
356 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
357 }
358 }
359
360 void
361 fs_generator::generate_math_g45(fs_inst *inst,
362 struct brw_reg dst,
363 struct brw_reg src)
364 {
365 if (inst->opcode == SHADER_OPCODE_POW ||
366 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
367 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
368 generate_math_gen4(inst, dst, src);
369 return;
370 }
371
372 int op = brw_math_function(inst->opcode);
373
374 assert(inst->mlen >= 1);
375
376 gen4_math(p, dst,
377 op,
378 inst->base_mrf, src,
379 BRW_MATH_DATA_VECTOR,
380 BRW_MATH_PRECISION_FULL);
381 }
382
383 void
384 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
385 struct brw_reg sampler_index)
386 {
387 int msg_type = -1;
388 int rlen = 4;
389 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
390 uint32_t return_format;
391
392 switch (dst.type) {
393 case BRW_REGISTER_TYPE_D:
394 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
395 break;
396 case BRW_REGISTER_TYPE_UD:
397 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
398 break;
399 default:
400 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
401 break;
402 }
403
404 if (dispatch_width == 16 &&
405 !inst->force_uncompressed && !inst->force_sechalf)
406 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
407
408 if (brw->gen >= 5) {
409 switch (inst->opcode) {
410 case SHADER_OPCODE_TEX:
411 if (inst->shadow_compare) {
412 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
413 } else {
414 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
415 }
416 break;
417 case FS_OPCODE_TXB:
418 if (inst->shadow_compare) {
419 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
420 } else {
421 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
422 }
423 break;
424 case SHADER_OPCODE_TXL:
425 if (inst->shadow_compare) {
426 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
427 } else {
428 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
429 }
430 break;
431 case SHADER_OPCODE_TXS:
432 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
433 break;
434 case SHADER_OPCODE_TXD:
435 if (inst->shadow_compare) {
436 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
437 assert(brw->gen >= 8 || brw->is_haswell);
438 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
439 } else {
440 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
441 }
442 break;
443 case SHADER_OPCODE_TXF:
444 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
445 break;
446 case SHADER_OPCODE_TXF_CMS:
447 if (brw->gen >= 7)
448 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
449 else
450 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
451 break;
452 case SHADER_OPCODE_TXF_UMS:
453 assert(brw->gen >= 7);
454 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
455 break;
456 case SHADER_OPCODE_TXF_MCS:
457 assert(brw->gen >= 7);
458 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
459 break;
460 case SHADER_OPCODE_LOD:
461 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
462 break;
463 case SHADER_OPCODE_TG4:
464 if (inst->shadow_compare) {
465 assert(brw->gen >= 7);
466 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
467 } else {
468 assert(brw->gen >= 6);
469 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
470 }
471 break;
472 case SHADER_OPCODE_TG4_OFFSET:
473 assert(brw->gen >= 7);
474 if (inst->shadow_compare) {
475 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
476 } else {
477 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
478 }
479 break;
480 default:
481 unreachable("not reached");
482 }
483 } else {
484 switch (inst->opcode) {
485 case SHADER_OPCODE_TEX:
486 /* Note that G45 and older determines shadow compare and dispatch width
487 * from message length for most messages.
488 */
489 assert(dispatch_width == 8);
490 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
491 if (inst->shadow_compare) {
492 assert(inst->mlen == 6);
493 } else {
494 assert(inst->mlen <= 4);
495 }
496 break;
497 case FS_OPCODE_TXB:
498 if (inst->shadow_compare) {
499 assert(inst->mlen == 6);
500 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
501 } else {
502 assert(inst->mlen == 9);
503 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
504 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
505 }
506 break;
507 case SHADER_OPCODE_TXL:
508 if (inst->shadow_compare) {
509 assert(inst->mlen == 6);
510 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
511 } else {
512 assert(inst->mlen == 9);
513 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
514 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
515 }
516 break;
517 case SHADER_OPCODE_TXD:
518 /* There is no sample_d_c message; comparisons are done manually */
519 assert(inst->mlen == 7 || inst->mlen == 10);
520 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
521 break;
522 case SHADER_OPCODE_TXF:
523 assert(inst->mlen == 9);
524 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
525 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
526 break;
527 case SHADER_OPCODE_TXS:
528 assert(inst->mlen == 3);
529 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
530 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
531 break;
532 default:
533 unreachable("not reached");
534 }
535 }
536 assert(msg_type != -1);
537
538 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
539 rlen = 8;
540 dst = vec16(dst);
541 }
542
543 if (brw->gen >= 7 && inst->header_present && dispatch_width == 16) {
544 /* The send-from-GRF for SIMD16 texturing with a header has an extra
545 * hardware register allocated to it, which we need to skip over (since
546 * our coordinates in the payload are in the even-numbered registers,
547 * and the header comes right before the first one).
548 */
549 assert(src.file == BRW_GENERAL_REGISTER_FILE);
550 src.nr++;
551 }
552
553 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
554
555 /* Load the message header if present. If there's a texture offset,
556 * we need to set it up explicitly and load the offset bitfield.
557 * Otherwise, we can use an implied move from g0 to the first message reg.
558 */
559 if (inst->header_present) {
560 if (brw->gen < 6 && !inst->texture_offset) {
561 /* Set up an implied move from g0 to the MRF. */
562 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
563 } else {
564 struct brw_reg header_reg;
565
566 if (brw->gen >= 7) {
567 header_reg = src;
568 } else {
569 assert(inst->base_mrf != -1);
570 header_reg = brw_message_reg(inst->base_mrf);
571 }
572
573 brw_push_insn_state(p);
574 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
575 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
576 /* Explicitly set up the message header by copying g0 to the MRF. */
577 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
578
579 if (inst->texture_offset) {
580 /* Set the offset bits in DWord 2. */
581 brw_MOV(p, get_element_ud(header_reg, 2),
582 brw_imm_ud(inst->texture_offset));
583 }
584
585 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index, dst);
586 brw_pop_insn_state(p);
587 }
588 }
589
590 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
591 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
592 ? prog_data->binding_table.gather_texture_start
593 : prog_data->binding_table.texture_start;
594
595 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
596 uint32_t sampler = sampler_index.dw1.ud;
597
598 brw_SAMPLE(p,
599 retype(dst, BRW_REGISTER_TYPE_UW),
600 inst->base_mrf,
601 src,
602 sampler + base_binding_table_index,
603 sampler % 16,
604 msg_type,
605 rlen,
606 inst->mlen,
607 inst->header_present,
608 simd_mode,
609 return_format);
610
611 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
612 } else {
613 /* Non-const sampler index */
614 /* Note: this clobbers `dst` as a temporary before emitting the send */
615
616 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
617 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
618
619 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
620
621 brw_push_insn_state(p);
622 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
623 brw_set_default_access_mode(p, BRW_ALIGN_1);
624
625 /* Some care required: `sampler` and `temp` may alias:
626 * addr = sampler & 0xff
627 * temp = (sampler << 8) & 0xf00
628 * addr = addr | temp
629 */
630 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
631 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
632 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
633 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
634 brw_OR(p, addr, addr, temp);
635
636 /* a0.0 |= <descriptor> */
637 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
638 brw_set_sampler_message(p, insn_or,
639 0 /* surface */,
640 0 /* sampler */,
641 msg_type,
642 rlen,
643 inst->mlen /* mlen */,
644 inst->header_present /* header */,
645 simd_mode,
646 return_format);
647 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
648 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
649 brw_set_src0(p, insn_or, addr);
650 brw_set_dest(p, insn_or, addr);
651
652
653 /* dst = send(offset, a0.0) */
654 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
655 brw_set_dest(p, insn_send, dst);
656 brw_set_src0(p, insn_send, src);
657 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
658
659 brw_pop_insn_state(p);
660
661 /* visitor knows more than we do about the surface limit required,
662 * so has already done marking.
663 */
664 }
665 }
666
667
668 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
669 * looking like:
670 *
671 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
672 *
673 * Ideally, we want to produce:
674 *
675 * DDX DDY
676 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
677 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
678 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
679 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
680 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
681 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
682 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
683 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
684 *
685 * and add another set of two more subspans if in 16-pixel dispatch mode.
686 *
687 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
688 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
689 * pair. But the ideal approximation may impose a huge performance cost on
690 * sample_d. On at least Haswell, sample_d instruction does some
691 * optimizations if the same LOD is used for all pixels in the subspan.
692 *
693 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
694 * appropriate swizzling.
695 */
696 void
697 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
698 struct brw_reg quality)
699 {
700 unsigned vstride, width;
701 assert(quality.file == BRW_IMMEDIATE_VALUE);
702 assert(quality.type == BRW_REGISTER_TYPE_D);
703
704 assert(stage == MESA_SHADER_FRAGMENT);
705 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
706
707 int quality_value = quality.dw1.d;
708
709 if (quality_value == BRW_DERIVATIVE_FINE ||
710 (key->high_quality_derivatives && quality_value != BRW_DERIVATIVE_COARSE)) {
711 /* produce accurate derivatives */
712 vstride = BRW_VERTICAL_STRIDE_2;
713 width = BRW_WIDTH_2;
714 }
715 else {
716 /* replicate the derivative at the top-left pixel to other pixels */
717 vstride = BRW_VERTICAL_STRIDE_4;
718 width = BRW_WIDTH_4;
719 }
720
721 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
722 BRW_REGISTER_TYPE_F,
723 vstride,
724 width,
725 BRW_HORIZONTAL_STRIDE_0,
726 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
727 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
728 BRW_REGISTER_TYPE_F,
729 vstride,
730 width,
731 BRW_HORIZONTAL_STRIDE_0,
732 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
733 brw_ADD(p, dst, src0, negate(src1));
734 }
735
736 /* The negate_value boolean is used to negate the derivative computation for
737 * FBOs, since they place the origin at the upper left instead of the lower
738 * left.
739 */
740 void
741 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
742 struct brw_reg quality, bool negate_value)
743 {
744 assert(quality.file == BRW_IMMEDIATE_VALUE);
745 assert(quality.type == BRW_REGISTER_TYPE_D);
746
747 assert(stage == MESA_SHADER_FRAGMENT);
748 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
749
750 int quality_value = quality.dw1.d;
751
752 if (quality_value == BRW_DERIVATIVE_FINE ||
753 (key->high_quality_derivatives && quality_value != BRW_DERIVATIVE_COARSE)) {
754 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
755 * Region Restrictions):
756 *
757 * In Align16 access mode, SIMD16 is not allowed for DW operations
758 * and SIMD8 is not allowed for DF operations.
759 *
760 * In this context, "DW operations" means "operations acting on 32-bit
761 * values", so it includes operations on floats.
762 *
763 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
764 * (Instruction Compression -> Rules and Restrictions):
765 *
766 * A compressed instruction must be in Align1 access mode. Align16
767 * mode instructions cannot be compressed.
768 *
769 * Similar text exists in the g45 PRM.
770 *
771 * On these platforms, if we're building a SIMD16 shader, we need to
772 * manually unroll to a pair of SIMD8 instructions.
773 */
774 bool unroll_to_simd8 =
775 (dispatch_width == 16 &&
776 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
777
778 /* produce accurate derivatives */
779 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
780 BRW_REGISTER_TYPE_F,
781 BRW_VERTICAL_STRIDE_4,
782 BRW_WIDTH_4,
783 BRW_HORIZONTAL_STRIDE_1,
784 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
785 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
786 BRW_REGISTER_TYPE_F,
787 BRW_VERTICAL_STRIDE_4,
788 BRW_WIDTH_4,
789 BRW_HORIZONTAL_STRIDE_1,
790 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
791 brw_push_insn_state(p);
792 brw_set_default_access_mode(p, BRW_ALIGN_16);
793 if (unroll_to_simd8)
794 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
795 if (negate_value)
796 brw_ADD(p, dst, src1, negate(src0));
797 else
798 brw_ADD(p, dst, src0, negate(src1));
799 if (unroll_to_simd8) {
800 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
801 src0 = sechalf(src0);
802 src1 = sechalf(src1);
803 dst = sechalf(dst);
804 if (negate_value)
805 brw_ADD(p, dst, src1, negate(src0));
806 else
807 brw_ADD(p, dst, src0, negate(src1));
808 }
809 brw_pop_insn_state(p);
810 } else {
811 /* replicate the derivative at the top-left pixel to other pixels */
812 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
813 BRW_REGISTER_TYPE_F,
814 BRW_VERTICAL_STRIDE_4,
815 BRW_WIDTH_4,
816 BRW_HORIZONTAL_STRIDE_0,
817 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
818 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
819 BRW_REGISTER_TYPE_F,
820 BRW_VERTICAL_STRIDE_4,
821 BRW_WIDTH_4,
822 BRW_HORIZONTAL_STRIDE_0,
823 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
824 if (negate_value)
825 brw_ADD(p, dst, src1, negate(src0));
826 else
827 brw_ADD(p, dst, src0, negate(src1));
828 }
829 }
830
831 void
832 fs_generator::generate_discard_jump(fs_inst *inst)
833 {
834 assert(brw->gen >= 6);
835
836 /* This HALT will be patched up at FB write time to point UIP at the end of
837 * the program, and at brw_uip_jip() JIP will be set to the end of the
838 * current block (or the program).
839 */
840 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
841
842 brw_push_insn_state(p);
843 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
844 gen6_HALT(p);
845 brw_pop_insn_state(p);
846 }
847
848 void
849 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
850 {
851 assert(inst->mlen != 0);
852
853 brw_MOV(p,
854 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
855 retype(src, BRW_REGISTER_TYPE_UD));
856 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
857 dispatch_width / 8, inst->offset);
858 }
859
860 void
861 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
862 {
863 assert(inst->mlen != 0);
864
865 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
866 dispatch_width / 8, inst->offset);
867 }
868
869 void
870 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
871 {
872 gen7_block_read_scratch(p, dst, dispatch_width / 8, inst->offset);
873 }
874
875 void
876 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
877 struct brw_reg dst,
878 struct brw_reg index,
879 struct brw_reg offset)
880 {
881 assert(inst->mlen != 0);
882
883 assert(index.file == BRW_IMMEDIATE_VALUE &&
884 index.type == BRW_REGISTER_TYPE_UD);
885 uint32_t surf_index = index.dw1.ud;
886
887 assert(offset.file == BRW_IMMEDIATE_VALUE &&
888 offset.type == BRW_REGISTER_TYPE_UD);
889 uint32_t read_offset = offset.dw1.ud;
890
891 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
892 read_offset, surf_index);
893
894 brw_mark_surface_used(prog_data, surf_index);
895 }
896
897 void
898 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
899 struct brw_reg dst,
900 struct brw_reg index,
901 struct brw_reg offset)
902 {
903 assert(inst->mlen == 0);
904 assert(index.type == BRW_REGISTER_TYPE_UD);
905
906 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
907 /* Reference just the dword we need, to avoid angering validate_reg(). */
908 offset = brw_vec1_grf(offset.nr, 0);
909
910 /* We use the SIMD4x2 mode because we want to end up with 4 components in
911 * the destination loaded consecutively from the same offset (which appears
912 * in the first component, and the rest are ignored).
913 */
914 dst.width = BRW_WIDTH_4;
915
916 if (index.file == BRW_IMMEDIATE_VALUE) {
917
918 uint32_t surf_index = index.dw1.ud;
919
920 brw_push_insn_state(p);
921 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
922 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
923 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
924 brw_pop_insn_state(p);
925
926 brw_set_dest(p, send, dst);
927 brw_set_src0(p, send, offset);
928 brw_set_sampler_message(p, send,
929 surf_index,
930 0, /* LD message ignores sampler unit */
931 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
932 1, /* rlen */
933 1, /* mlen */
934 false, /* no header */
935 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
936 0);
937
938 brw_mark_surface_used(prog_data, surf_index);
939
940 } else {
941
942 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
943
944 brw_push_insn_state(p);
945 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
946 brw_set_default_access_mode(p, BRW_ALIGN_1);
947
948 /* a0.0 = surf_index & 0xff */
949 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
950 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
951 brw_set_dest(p, insn_and, addr);
952 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
953 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
954
955
956 /* a0.0 |= <descriptor> */
957 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
958 brw_set_sampler_message(p, insn_or,
959 0 /* surface */,
960 0 /* sampler */,
961 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
962 1 /* rlen */,
963 1 /* mlen */,
964 false /* header */,
965 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
966 0);
967 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
968 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
969 brw_set_src0(p, insn_or, addr);
970 brw_set_dest(p, insn_or, addr);
971
972
973 /* dst = send(offset, a0.0) */
974 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
975 brw_set_dest(p, insn_send, dst);
976 brw_set_src0(p, insn_send, offset);
977 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
978
979 brw_pop_insn_state(p);
980
981 /* visitor knows more than we do about the surface limit required,
982 * so has already done marking.
983 */
984
985 }
986 }
987
988 void
989 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
990 struct brw_reg dst,
991 struct brw_reg index,
992 struct brw_reg offset)
993 {
994 assert(brw->gen < 7); /* Should use the gen7 variant. */
995 assert(inst->header_present);
996 assert(inst->mlen);
997
998 assert(index.file == BRW_IMMEDIATE_VALUE &&
999 index.type == BRW_REGISTER_TYPE_UD);
1000 uint32_t surf_index = index.dw1.ud;
1001
1002 uint32_t simd_mode, rlen, msg_type;
1003 if (dispatch_width == 16) {
1004 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1005 rlen = 8;
1006 } else {
1007 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1008 rlen = 4;
1009 }
1010
1011 if (brw->gen >= 5)
1012 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1013 else {
1014 /* We always use the SIMD16 message so that we only have to load U, and
1015 * not V or R.
1016 */
1017 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1018 assert(inst->mlen == 3);
1019 assert(inst->regs_written == 8);
1020 rlen = 8;
1021 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1022 }
1023
1024 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1025 BRW_REGISTER_TYPE_D);
1026 brw_MOV(p, offset_mrf, offset);
1027
1028 struct brw_reg header = brw_vec8_grf(0, 0);
1029 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1030
1031 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1032 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
1033 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1034 brw_set_src0(p, send, header);
1035 if (brw->gen < 6)
1036 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
1037
1038 /* Our surface is set up as floats, regardless of what actual data is
1039 * stored in it.
1040 */
1041 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1042 brw_set_sampler_message(p, send,
1043 surf_index,
1044 0, /* sampler (unused) */
1045 msg_type,
1046 rlen,
1047 inst->mlen,
1048 inst->header_present,
1049 simd_mode,
1050 return_format);
1051
1052 brw_mark_surface_used(prog_data, surf_index);
1053 }
1054
1055 void
1056 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1057 struct brw_reg dst,
1058 struct brw_reg index,
1059 struct brw_reg offset)
1060 {
1061 assert(brw->gen >= 7);
1062 /* Varying-offset pull constant loads are treated as a normal expression on
1063 * gen7, so the fact that it's a send message is hidden at the IR level.
1064 */
1065 assert(!inst->header_present);
1066 assert(!inst->mlen);
1067 assert(index.type == BRW_REGISTER_TYPE_UD);
1068
1069 uint32_t simd_mode, rlen, mlen;
1070 if (dispatch_width == 16) {
1071 mlen = 2;
1072 rlen = 8;
1073 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1074 } else {
1075 mlen = 1;
1076 rlen = 4;
1077 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1078 }
1079
1080 if (index.file == BRW_IMMEDIATE_VALUE) {
1081
1082 uint32_t surf_index = index.dw1.ud;
1083
1084 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1085 brw_set_dest(p, send, dst);
1086 brw_set_src0(p, send, offset);
1087 brw_set_sampler_message(p, send,
1088 surf_index,
1089 0, /* LD message ignores sampler unit */
1090 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1091 rlen,
1092 mlen,
1093 false, /* no header */
1094 simd_mode,
1095 0);
1096
1097 brw_mark_surface_used(prog_data, surf_index);
1098
1099 } else {
1100
1101 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1102
1103 brw_push_insn_state(p);
1104 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1105 brw_set_default_access_mode(p, BRW_ALIGN_1);
1106
1107 /* a0.0 = surf_index & 0xff */
1108 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1109 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1110 brw_set_dest(p, insn_and, addr);
1111 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1112 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1113
1114
1115 /* a0.0 |= <descriptor> */
1116 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1117 brw_set_sampler_message(p, insn_or,
1118 0 /* surface */,
1119 0 /* sampler */,
1120 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1121 rlen /* rlen */,
1122 mlen /* mlen */,
1123 false /* header */,
1124 simd_mode,
1125 0);
1126 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1127 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1128 brw_set_src0(p, insn_or, addr);
1129 brw_set_dest(p, insn_or, addr);
1130
1131
1132 /* dst = send(offset, a0.0) */
1133 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1134 brw_set_dest(p, insn_send, dst);
1135 brw_set_src0(p, insn_send, offset);
1136 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1137
1138 brw_pop_insn_state(p);
1139
1140 /* visitor knows more than we do about the surface limit required,
1141 * so has already done marking.
1142 */
1143 }
1144 }
1145
1146 /**
1147 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1148 * into the flags register (f0.0).
1149 *
1150 * Used only on Gen6 and above.
1151 */
1152 void
1153 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1154 {
1155 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1156 struct brw_reg dispatch_mask;
1157
1158 if (brw->gen >= 6)
1159 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1160 else
1161 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1162
1163 brw_push_insn_state(p);
1164 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1165 brw_MOV(p, flags, dispatch_mask);
1166 brw_pop_insn_state(p);
1167 }
1168
1169 void
1170 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1171 struct brw_reg dst,
1172 struct brw_reg src,
1173 struct brw_reg msg_data,
1174 unsigned msg_type)
1175 {
1176 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1177 msg_data.type == BRW_REGISTER_TYPE_UD);
1178
1179 brw_pixel_interpolator_query(p,
1180 retype(dst, BRW_REGISTER_TYPE_UW),
1181 src,
1182 inst->pi_noperspective,
1183 msg_type,
1184 msg_data.dw1.ud,
1185 inst->mlen,
1186 inst->regs_written);
1187 }
1188
1189
1190 static uint32_t brw_file_from_reg(fs_reg *reg)
1191 {
1192 switch (reg->file) {
1193 case GRF:
1194 return BRW_GENERAL_REGISTER_FILE;
1195 case MRF:
1196 return BRW_MESSAGE_REGISTER_FILE;
1197 case IMM:
1198 return BRW_IMMEDIATE_VALUE;
1199 default:
1200 unreachable("not reached");
1201 }
1202 }
1203
1204 struct brw_reg
1205 brw_reg_from_fs_reg(fs_reg *reg)
1206 {
1207 struct brw_reg brw_reg;
1208
1209 switch (reg->file) {
1210 case GRF:
1211 case MRF:
1212 if (reg->stride == 0) {
1213 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
1214 } else {
1215 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1216 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
1217 }
1218
1219 brw_reg = retype(brw_reg, reg->type);
1220 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
1221 break;
1222 case IMM:
1223 switch (reg->type) {
1224 case BRW_REGISTER_TYPE_F:
1225 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
1226 break;
1227 case BRW_REGISTER_TYPE_D:
1228 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
1229 break;
1230 case BRW_REGISTER_TYPE_UD:
1231 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
1232 break;
1233 default:
1234 unreachable("not reached");
1235 }
1236 break;
1237 case HW_REG:
1238 assert(reg->type == reg->fixed_hw_reg.type);
1239 brw_reg = reg->fixed_hw_reg;
1240 break;
1241 case BAD_FILE:
1242 /* Probably unused. */
1243 brw_reg = brw_null_reg();
1244 break;
1245 case UNIFORM:
1246 unreachable("not reached");
1247 default:
1248 unreachable("not reached");
1249 }
1250 if (reg->abs)
1251 brw_reg = brw_abs(brw_reg);
1252 if (reg->negate)
1253 brw_reg = negate(brw_reg);
1254
1255 return brw_reg;
1256 }
1257
1258 /**
1259 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1260 * sampler LD messages.
1261 *
1262 * We don't want to bake it into the send message's code generation because
1263 * that means we don't get a chance to schedule the instructions.
1264 */
1265 void
1266 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1267 struct brw_reg dst,
1268 struct brw_reg value)
1269 {
1270 assert(value.file == BRW_IMMEDIATE_VALUE);
1271
1272 brw_push_insn_state(p);
1273 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1274 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1275 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1276 brw_pop_insn_state(p);
1277 }
1278
1279 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1280 * (when mask is passed as a uniform) of register mask before moving it
1281 * to register dst.
1282 */
1283 void
1284 fs_generator::generate_set_omask(fs_inst *inst,
1285 struct brw_reg dst,
1286 struct brw_reg mask)
1287 {
1288 bool stride_8_8_1 =
1289 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1290 mask.width == BRW_WIDTH_8 &&
1291 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1292
1293 bool stride_0_1_0 =
1294 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1295 mask.width == BRW_WIDTH_1 &&
1296 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1297
1298 assert(stride_8_8_1 || stride_0_1_0);
1299 assert(dst.type == BRW_REGISTER_TYPE_UW);
1300
1301 if (dispatch_width == 16)
1302 dst = vec16(dst);
1303 brw_push_insn_state(p);
1304 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1305 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1306
1307 if (stride_8_8_1) {
1308 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1309 } else if (stride_0_1_0) {
1310 brw_MOV(p, dst, retype(mask, dst.type));
1311 }
1312 brw_pop_insn_state(p);
1313 }
1314
1315 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1316 * the ADD instruction.
1317 */
1318 void
1319 fs_generator::generate_set_sample_id(fs_inst *inst,
1320 struct brw_reg dst,
1321 struct brw_reg src0,
1322 struct brw_reg src1)
1323 {
1324 assert(dst.type == BRW_REGISTER_TYPE_D ||
1325 dst.type == BRW_REGISTER_TYPE_UD);
1326 assert(src0.type == BRW_REGISTER_TYPE_D ||
1327 src0.type == BRW_REGISTER_TYPE_UD);
1328
1329 brw_push_insn_state(p);
1330 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1331 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1332 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1333 brw_ADD(p, dst, src0, reg);
1334 if (dispatch_width == 16)
1335 brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
1336 brw_pop_insn_state(p);
1337 }
1338
1339 /**
1340 * Change the register's data type from UD to W, doubling the strides in order
1341 * to compensate for halving the data type width.
1342 */
1343 static struct brw_reg
1344 ud_reg_to_w(struct brw_reg r)
1345 {
1346 assert(r.type == BRW_REGISTER_TYPE_UD);
1347 r.type = BRW_REGISTER_TYPE_W;
1348
1349 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1350 * doubles the real stride.
1351 */
1352 if (r.hstride != 0)
1353 ++r.hstride;
1354 if (r.vstride != 0)
1355 ++r.vstride;
1356
1357 return r;
1358 }
1359
1360 void
1361 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1362 struct brw_reg dst,
1363 struct brw_reg x,
1364 struct brw_reg y)
1365 {
1366 assert(brw->gen >= 7);
1367 assert(dst.type == BRW_REGISTER_TYPE_UD);
1368 assert(x.type == BRW_REGISTER_TYPE_F);
1369 assert(y.type == BRW_REGISTER_TYPE_F);
1370
1371 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1372 *
1373 * Because this instruction does not have a 16-bit floating-point type,
1374 * the destination data type must be Word (W).
1375 *
1376 * The destination must be DWord-aligned and specify a horizontal stride
1377 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1378 * each destination channel and the upper word is not modified.
1379 */
1380 struct brw_reg dst_w = ud_reg_to_w(dst);
1381
1382 /* Give each 32-bit channel of dst the form below , where "." means
1383 * unchanged.
1384 * 0x....hhhh
1385 */
1386 brw_F32TO16(p, dst_w, y);
1387
1388 /* Now the form:
1389 * 0xhhhh0000
1390 */
1391 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1392
1393 /* And, finally the form of packHalf2x16's output:
1394 * 0xhhhhllll
1395 */
1396 brw_F32TO16(p, dst_w, x);
1397 }
1398
1399 void
1400 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1401 struct brw_reg dst,
1402 struct brw_reg src)
1403 {
1404 assert(brw->gen >= 7);
1405 assert(dst.type == BRW_REGISTER_TYPE_F);
1406 assert(src.type == BRW_REGISTER_TYPE_UD);
1407
1408 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1409 *
1410 * Because this instruction does not have a 16-bit floating-point type,
1411 * the source data type must be Word (W). The destination type must be
1412 * F (Float).
1413 */
1414 struct brw_reg src_w = ud_reg_to_w(src);
1415
1416 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1417 * For the Y case, we wish to access only the upper word; therefore
1418 * a 16-bit subregister offset is needed.
1419 */
1420 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1421 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1422 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1423 src_w.subnr += 2;
1424
1425 brw_F16TO32(p, dst, src_w);
1426 }
1427
1428 void
1429 fs_generator::generate_shader_time_add(fs_inst *inst,
1430 struct brw_reg payload,
1431 struct brw_reg offset,
1432 struct brw_reg value)
1433 {
1434 assert(brw->gen >= 7);
1435 brw_push_insn_state(p);
1436 brw_set_default_mask_control(p, true);
1437
1438 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1439 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1440 offset.type);
1441 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1442 value.type);
1443
1444 assert(offset.file == BRW_IMMEDIATE_VALUE);
1445 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1446 value.width = BRW_WIDTH_1;
1447 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1448 value.vstride = BRW_VERTICAL_STRIDE_0;
1449 } else {
1450 assert(value.file == BRW_IMMEDIATE_VALUE);
1451 }
1452
1453 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1454 * case, and we don't really care about squeezing every bit of performance
1455 * out of this path, so we just emit the MOVs from here.
1456 */
1457 brw_MOV(p, payload_offset, offset);
1458 brw_MOV(p, payload_value, value);
1459 brw_shader_time_add(p, payload,
1460 prog_data->binding_table.shader_time_start);
1461 brw_pop_insn_state(p);
1462
1463 brw_mark_surface_used(prog_data,
1464 prog_data->binding_table.shader_time_start);
1465 }
1466
1467 void
1468 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1469 struct brw_reg atomic_op,
1470 struct brw_reg surf_index)
1471 {
1472 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1473 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1474 surf_index.file == BRW_IMMEDIATE_VALUE &&
1475 surf_index.type == BRW_REGISTER_TYPE_UD);
1476
1477 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1478 atomic_op.dw1.ud, surf_index.dw1.ud,
1479 inst->mlen, dispatch_width / 8);
1480
1481 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1482 }
1483
1484 void
1485 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1486 struct brw_reg surf_index)
1487 {
1488 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1489 surf_index.type == BRW_REGISTER_TYPE_UD);
1490
1491 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1492 surf_index.dw1.ud,
1493 inst->mlen, dispatch_width / 8);
1494
1495 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1496 }
1497
1498 void
1499 fs_generator::generate_code(const cfg_t *cfg)
1500 {
1501 int start_offset = p->next_insn_offset;
1502 int loop_count = 0;
1503
1504 struct annotation_info annotation;
1505 memset(&annotation, 0, sizeof(annotation));
1506
1507 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1508 struct brw_reg src[3], dst;
1509 unsigned int last_insn_offset = p->next_insn_offset;
1510
1511 if (unlikely(debug_flag))
1512 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1513
1514 for (unsigned int i = 0; i < inst->sources; i++) {
1515 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1516
1517 /* The accumulator result appears to get used for the
1518 * conditional modifier generation. When negating a UD
1519 * value, there is a 33rd bit generated for the sign in the
1520 * accumulator value, so now you can't check, for example,
1521 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1522 */
1523 assert(!inst->conditional_mod ||
1524 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1525 !inst->src[i].negate);
1526 }
1527 dst = brw_reg_from_fs_reg(&inst->dst);
1528
1529 brw_set_default_predicate_control(p, inst->predicate);
1530 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1531 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1532 brw_set_default_saturate(p, inst->saturate);
1533 brw_set_default_mask_control(p, inst->force_writemask_all);
1534 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1535
1536 if (inst->force_uncompressed || dispatch_width == 8) {
1537 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1538 } else if (inst->force_sechalf) {
1539 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1540 } else {
1541 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1542 }
1543
1544 switch (inst->opcode) {
1545 case BRW_OPCODE_MOV:
1546 brw_MOV(p, dst, src[0]);
1547 break;
1548 case BRW_OPCODE_ADD:
1549 brw_ADD(p, dst, src[0], src[1]);
1550 break;
1551 case BRW_OPCODE_MUL:
1552 brw_MUL(p, dst, src[0], src[1]);
1553 break;
1554 case BRW_OPCODE_AVG:
1555 brw_AVG(p, dst, src[0], src[1]);
1556 break;
1557 case BRW_OPCODE_MACH:
1558 brw_MACH(p, dst, src[0], src[1]);
1559 break;
1560
1561 case BRW_OPCODE_MAD:
1562 assert(brw->gen >= 6);
1563 brw_set_default_access_mode(p, BRW_ALIGN_16);
1564 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1565 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1566 brw_MAD(p, dst, src[0], src[1], src[2]);
1567 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1568 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1569 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1570 } else {
1571 brw_MAD(p, dst, src[0], src[1], src[2]);
1572 }
1573 brw_set_default_access_mode(p, BRW_ALIGN_1);
1574 break;
1575
1576 case BRW_OPCODE_LRP:
1577 assert(brw->gen >= 6);
1578 brw_set_default_access_mode(p, BRW_ALIGN_16);
1579 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1580 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1581 brw_LRP(p, dst, src[0], src[1], src[2]);
1582 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1583 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1584 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1585 } else {
1586 brw_LRP(p, dst, src[0], src[1], src[2]);
1587 }
1588 brw_set_default_access_mode(p, BRW_ALIGN_1);
1589 break;
1590
1591 case BRW_OPCODE_FRC:
1592 brw_FRC(p, dst, src[0]);
1593 break;
1594 case BRW_OPCODE_RNDD:
1595 brw_RNDD(p, dst, src[0]);
1596 break;
1597 case BRW_OPCODE_RNDE:
1598 brw_RNDE(p, dst, src[0]);
1599 break;
1600 case BRW_OPCODE_RNDZ:
1601 brw_RNDZ(p, dst, src[0]);
1602 break;
1603
1604 case BRW_OPCODE_AND:
1605 brw_AND(p, dst, src[0], src[1]);
1606 break;
1607 case BRW_OPCODE_OR:
1608 brw_OR(p, dst, src[0], src[1]);
1609 break;
1610 case BRW_OPCODE_XOR:
1611 brw_XOR(p, dst, src[0], src[1]);
1612 break;
1613 case BRW_OPCODE_NOT:
1614 brw_NOT(p, dst, src[0]);
1615 break;
1616 case BRW_OPCODE_ASR:
1617 brw_ASR(p, dst, src[0], src[1]);
1618 break;
1619 case BRW_OPCODE_SHR:
1620 brw_SHR(p, dst, src[0], src[1]);
1621 break;
1622 case BRW_OPCODE_SHL:
1623 brw_SHL(p, dst, src[0], src[1]);
1624 break;
1625 case BRW_OPCODE_F32TO16:
1626 assert(brw->gen >= 7);
1627 brw_F32TO16(p, dst, src[0]);
1628 break;
1629 case BRW_OPCODE_F16TO32:
1630 assert(brw->gen >= 7);
1631 brw_F16TO32(p, dst, src[0]);
1632 break;
1633 case BRW_OPCODE_CMP:
1634 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1635 break;
1636 case BRW_OPCODE_SEL:
1637 brw_SEL(p, dst, src[0], src[1]);
1638 break;
1639 case BRW_OPCODE_BFREV:
1640 assert(brw->gen >= 7);
1641 /* BFREV only supports UD type for src and dst. */
1642 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1643 retype(src[0], BRW_REGISTER_TYPE_UD));
1644 break;
1645 case BRW_OPCODE_FBH:
1646 assert(brw->gen >= 7);
1647 /* FBH only supports UD type for dst. */
1648 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1649 break;
1650 case BRW_OPCODE_FBL:
1651 assert(brw->gen >= 7);
1652 /* FBL only supports UD type for dst. */
1653 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1654 break;
1655 case BRW_OPCODE_CBIT:
1656 assert(brw->gen >= 7);
1657 /* CBIT only supports UD type for dst. */
1658 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1659 break;
1660 case BRW_OPCODE_ADDC:
1661 assert(brw->gen >= 7);
1662 brw_ADDC(p, dst, src[0], src[1]);
1663 break;
1664 case BRW_OPCODE_SUBB:
1665 assert(brw->gen >= 7);
1666 brw_SUBB(p, dst, src[0], src[1]);
1667 break;
1668 case BRW_OPCODE_MAC:
1669 brw_MAC(p, dst, src[0], src[1]);
1670 break;
1671
1672 case BRW_OPCODE_BFE:
1673 assert(brw->gen >= 7);
1674 brw_set_default_access_mode(p, BRW_ALIGN_16);
1675 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1676 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1677 brw_BFE(p, dst, src[0], src[1], src[2]);
1678 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1679 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1680 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1681 } else {
1682 brw_BFE(p, dst, src[0], src[1], src[2]);
1683 }
1684 brw_set_default_access_mode(p, BRW_ALIGN_1);
1685 break;
1686
1687 case BRW_OPCODE_BFI1:
1688 assert(brw->gen >= 7);
1689 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1690 * should
1691 *
1692 * "Force BFI instructions to be executed always in SIMD8."
1693 */
1694 if (dispatch_width == 16 && brw->is_haswell) {
1695 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1696 brw_BFI1(p, dst, src[0], src[1]);
1697 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1698 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1699 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1700 } else {
1701 brw_BFI1(p, dst, src[0], src[1]);
1702 }
1703 break;
1704 case BRW_OPCODE_BFI2:
1705 assert(brw->gen >= 7);
1706 brw_set_default_access_mode(p, BRW_ALIGN_16);
1707 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1708 * should
1709 *
1710 * "Force BFI instructions to be executed always in SIMD8."
1711 *
1712 * Otherwise we would be able to emit compressed instructions like we
1713 * do for the other three-source instructions.
1714 */
1715 if (dispatch_width == 16) {
1716 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1717 brw_BFI2(p, dst, src[0], src[1], src[2]);
1718 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1719 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1720 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1721 } else {
1722 brw_BFI2(p, dst, src[0], src[1], src[2]);
1723 }
1724 brw_set_default_access_mode(p, BRW_ALIGN_1);
1725 break;
1726
1727 case BRW_OPCODE_IF:
1728 if (inst->src[0].file != BAD_FILE) {
1729 /* The instruction has an embedded compare (only allowed on gen6) */
1730 assert(brw->gen == 6);
1731 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1732 } else {
1733 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1734 }
1735 break;
1736
1737 case BRW_OPCODE_ELSE:
1738 brw_ELSE(p);
1739 break;
1740 case BRW_OPCODE_ENDIF:
1741 brw_ENDIF(p);
1742 break;
1743
1744 case BRW_OPCODE_DO:
1745 brw_DO(p, BRW_EXECUTE_8);
1746 break;
1747
1748 case BRW_OPCODE_BREAK:
1749 brw_BREAK(p);
1750 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1751 break;
1752 case BRW_OPCODE_CONTINUE:
1753 brw_CONT(p);
1754 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1755 break;
1756
1757 case BRW_OPCODE_WHILE:
1758 brw_WHILE(p);
1759 loop_count++;
1760 break;
1761
1762 case SHADER_OPCODE_RCP:
1763 case SHADER_OPCODE_RSQ:
1764 case SHADER_OPCODE_SQRT:
1765 case SHADER_OPCODE_EXP2:
1766 case SHADER_OPCODE_LOG2:
1767 case SHADER_OPCODE_SIN:
1768 case SHADER_OPCODE_COS:
1769 assert(brw->gen < 6 || inst->mlen == 0);
1770 if (brw->gen >= 7) {
1771 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1772 brw_null_reg());
1773 } else if (brw->gen == 6) {
1774 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1775 } else if (brw->gen == 5 || brw->is_g4x) {
1776 generate_math_g45(inst, dst, src[0]);
1777 } else {
1778 generate_math_gen4(inst, dst, src[0]);
1779 }
1780 break;
1781 case SHADER_OPCODE_INT_QUOTIENT:
1782 case SHADER_OPCODE_INT_REMAINDER:
1783 case SHADER_OPCODE_POW:
1784 assert(brw->gen < 6 || inst->mlen == 0);
1785 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1786 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1787 } else if (brw->gen >= 6) {
1788 generate_math_gen6(inst, dst, src[0], src[1]);
1789 } else {
1790 generate_math_gen4(inst, dst, src[0]);
1791 }
1792 break;
1793 case FS_OPCODE_PIXEL_X:
1794 generate_pixel_xy(dst, true);
1795 break;
1796 case FS_OPCODE_PIXEL_Y:
1797 generate_pixel_xy(dst, false);
1798 break;
1799 case FS_OPCODE_CINTERP:
1800 brw_MOV(p, dst, src[0]);
1801 break;
1802 case FS_OPCODE_LINTERP:
1803 generate_linterp(inst, dst, src);
1804 break;
1805 case SHADER_OPCODE_TEX:
1806 case FS_OPCODE_TXB:
1807 case SHADER_OPCODE_TXD:
1808 case SHADER_OPCODE_TXF:
1809 case SHADER_OPCODE_TXF_CMS:
1810 case SHADER_OPCODE_TXF_UMS:
1811 case SHADER_OPCODE_TXF_MCS:
1812 case SHADER_OPCODE_TXL:
1813 case SHADER_OPCODE_TXS:
1814 case SHADER_OPCODE_LOD:
1815 case SHADER_OPCODE_TG4:
1816 case SHADER_OPCODE_TG4_OFFSET:
1817 generate_tex(inst, dst, src[0], src[1]);
1818 break;
1819 case FS_OPCODE_DDX:
1820 generate_ddx(inst, dst, src[0], src[1]);
1821 break;
1822 case FS_OPCODE_DDY:
1823 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1824 * guarantee that key->render_to_fbo is set).
1825 */
1826 assert(stage == MESA_SHADER_FRAGMENT &&
1827 ((gl_fragment_program *) prog)->UsesDFdy);
1828 generate_ddy(inst, dst, src[0], src[1],
1829 ((brw_wm_prog_key * const) this->key)->render_to_fbo);
1830 break;
1831
1832 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1833 generate_scratch_write(inst, src[0]);
1834 break;
1835
1836 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1837 generate_scratch_read(inst, dst);
1838 break;
1839
1840 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1841 generate_scratch_read_gen7(inst, dst);
1842 break;
1843
1844 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1845 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1846 break;
1847
1848 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1849 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1850 break;
1851
1852 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1853 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1854 break;
1855
1856 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1857 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1858 break;
1859
1860 case FS_OPCODE_REP_FB_WRITE:
1861 case FS_OPCODE_FB_WRITE:
1862 generate_fb_write(inst);
1863 break;
1864
1865 case FS_OPCODE_BLORP_FB_WRITE:
1866 generate_blorp_fb_write(inst);
1867 break;
1868
1869 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1870 generate_mov_dispatch_to_flags(inst);
1871 break;
1872
1873 case FS_OPCODE_DISCARD_JUMP:
1874 generate_discard_jump(inst);
1875 break;
1876
1877 case SHADER_OPCODE_SHADER_TIME_ADD:
1878 generate_shader_time_add(inst, src[0], src[1], src[2]);
1879 break;
1880
1881 case SHADER_OPCODE_UNTYPED_ATOMIC:
1882 generate_untyped_atomic(inst, dst, src[0], src[1]);
1883 break;
1884
1885 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1886 generate_untyped_surface_read(inst, dst, src[0]);
1887 break;
1888
1889 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1890 generate_set_simd4x2_offset(inst, dst, src[0]);
1891 break;
1892
1893 case FS_OPCODE_SET_OMASK:
1894 generate_set_omask(inst, dst, src[0]);
1895 break;
1896
1897 case FS_OPCODE_SET_SAMPLE_ID:
1898 generate_set_sample_id(inst, dst, src[0], src[1]);
1899 break;
1900
1901 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1902 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1903 break;
1904
1905 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1906 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1907 generate_unpack_half_2x16_split(inst, dst, src[0]);
1908 break;
1909
1910 case FS_OPCODE_PLACEHOLDER_HALT:
1911 /* This is the place where the final HALT needs to be inserted if
1912 * we've emitted any discards. If not, this will emit no code.
1913 */
1914 if (!patch_discard_jumps_to_fb_writes()) {
1915 if (unlikely(debug_flag)) {
1916 annotation.ann_count--;
1917 }
1918 }
1919 break;
1920
1921 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
1922 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1923 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
1924 break;
1925
1926 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
1927 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1928 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
1929 break;
1930
1931 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
1932 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1933 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
1934 break;
1935
1936 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
1937 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1938 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
1939 break;
1940
1941 default:
1942 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1943 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1944 opcode_descs[inst->opcode].name);
1945 } else {
1946 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1947 }
1948 abort();
1949
1950 case SHADER_OPCODE_LOAD_PAYLOAD:
1951 unreachable("Should be lowered by lower_load_payload()");
1952 }
1953
1954 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1955 assert(p->next_insn_offset == last_insn_offset + 16 ||
1956 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1957 "emitting more than 1 instruction");
1958
1959 brw_inst *last = &p->store[last_insn_offset / 16];
1960
1961 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
1962 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
1963 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
1964 }
1965 }
1966
1967 brw_set_uip_jip(p);
1968 annotation_finalize(&annotation, p->next_insn_offset);
1969
1970 int before_size = p->next_insn_offset - start_offset;
1971 brw_compact_instructions(p, start_offset, annotation.ann_count,
1972 annotation.ann);
1973 int after_size = p->next_insn_offset - start_offset;
1974
1975 if (unlikely(debug_flag)) {
1976 if (shader_prog) {
1977 fprintf(stderr,
1978 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
1979 shader_prog->Label ? shader_prog->Label : "unnamed",
1980 shader_prog->Name, dispatch_width);
1981 } else if (prog) {
1982 fprintf(stderr,
1983 "Native code for fragment program %d (SIMD%d dispatch):\n",
1984 prog->Id, dispatch_width);
1985 } else {
1986 fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
1987 dispatch_width);
1988 }
1989 fprintf(stderr, "SIMD%d shader: %d instructions. %d loops. Compacted %d to %d"
1990 " bytes (%.0f%%)\n",
1991 dispatch_width, before_size / 16, loop_count, before_size, after_size,
1992 100.0f * (before_size - after_size) / before_size);
1993
1994 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
1995 ralloc_free(annotation.ann);
1996 }
1997 }
1998
1999 const unsigned *
2000 fs_generator::generate_assembly(const cfg_t *simd8_cfg,
2001 const cfg_t *simd16_cfg,
2002 unsigned *assembly_size)
2003 {
2004 assert(simd8_cfg || simd16_cfg);
2005
2006 if (simd8_cfg) {
2007 dispatch_width = 8;
2008 generate_code(simd8_cfg);
2009 }
2010
2011 if (simd16_cfg) {
2012 /* align to 64 byte boundary. */
2013 while (p->next_insn_offset % 64) {
2014 brw_NOP(p);
2015 }
2016
2017 assert(stage == MESA_SHADER_FRAGMENT);
2018 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
2019
2020 /* Save off the start of this SIMD16 program */
2021 prog_data->prog_offset_16 = p->next_insn_offset;
2022
2023 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
2024
2025 dispatch_width = 16;
2026 generate_code(simd16_cfg);
2027 }
2028
2029 return brw_get_program(p, assembly_size);
2030 }