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i965/fs: Add support for non-const sampler indices in generator
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 fs_generator::fs_generator(struct brw_context *brw,
40 void *mem_ctx,
41 const struct brw_wm_prog_key *key,
42 struct brw_wm_prog_data *prog_data,
43 struct gl_shader_program *prog,
44 struct gl_fragment_program *fp,
45 bool runtime_check_aads_emit,
46 bool debug_flag)
47
48 : brw(brw), key(key), prog_data(prog_data), prog(prog), fp(fp),
49 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(debug_flag),
50 mem_ctx(mem_ctx)
51 {
52 ctx = &brw->ctx;
53
54 p = rzalloc(mem_ctx, struct brw_compile);
55 brw_init_compile(brw, p, mem_ctx);
56 }
57
58 fs_generator::~fs_generator()
59 {
60 }
61
62 bool
63 fs_generator::patch_discard_jumps_to_fb_writes()
64 {
65 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
66 return false;
67
68 int scale = brw_jump_scale(brw);
69
70 /* There is a somewhat strange undocumented requirement of using
71 * HALT, according to the simulator. If some channel has HALTed to
72 * a particular UIP, then by the end of the program, every channel
73 * must have HALTed to that UIP. Furthermore, the tracking is a
74 * stack, so you can't do the final halt of a UIP after starting
75 * halting to a new UIP.
76 *
77 * Symptoms of not emitting this instruction on actual hardware
78 * included GPU hangs and sparkly rendering on the piglit discard
79 * tests.
80 */
81 brw_inst *last_halt = gen6_HALT(p);
82 brw_inst_set_uip(brw, last_halt, 1 * scale);
83 brw_inst_set_jip(brw, last_halt, 1 * scale);
84
85 int ip = p->nr_insn;
86
87 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
88 brw_inst *patch = &p->store[patch_ip->ip];
89
90 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
91 /* HALT takes a half-instruction distance from the pre-incremented IP. */
92 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
93 }
94
95 this->discard_halt_patches.make_empty();
96 return true;
97 }
98
99 void
100 fs_generator::fire_fb_write(fs_inst *inst,
101 GLuint base_reg,
102 struct brw_reg implied_header,
103 GLuint nr)
104 {
105 uint32_t msg_control;
106
107 if (brw->gen < 6) {
108 brw_push_insn_state(p);
109 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
110 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
111 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
112 brw_MOV(p,
113 brw_message_reg(base_reg + 1),
114 brw_vec8_grf(1, 0));
115 brw_pop_insn_state(p);
116 }
117
118 if (prog_data->dual_src_blend)
119 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
120 else if (dispatch_width == 16)
121 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
122 else
123 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
124
125 uint32_t surf_index =
126 prog_data->binding_table.render_target_start + inst->target;
127
128 brw_fb_WRITE(p,
129 dispatch_width,
130 base_reg,
131 implied_header,
132 msg_control,
133 surf_index,
134 nr,
135 0,
136 inst->eot,
137 inst->header_present);
138
139 brw_mark_surface_used(&prog_data->base, surf_index);
140 }
141
142 void
143 fs_generator::generate_fb_write(fs_inst *inst)
144 {
145 struct brw_reg implied_header;
146
147 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
148 * move, here's g1.
149 */
150 if (inst->header_present) {
151 brw_push_insn_state(p);
152 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
153 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
154 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
155 brw_set_default_flag_reg(p, 0, 0);
156
157 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
158 * present.
159 */
160 if ((fp && fp->UsesKill) || key->alpha_test_func) {
161 struct brw_reg pixel_mask;
162
163 if (brw->gen >= 6)
164 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
165 else
166 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
167
168 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
169 }
170
171 if (brw->gen >= 6) {
172 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
173 brw_MOV(p,
174 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
175 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
176 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
177
178 if (inst->target > 0 && key->replicate_alpha) {
179 /* Set "Source0 Alpha Present to RenderTarget" bit in message
180 * header.
181 */
182 brw_OR(p,
183 vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)),
184 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
185 brw_imm_ud(0x1 << 11));
186 }
187
188 if (inst->target > 0) {
189 /* Set the render target index for choosing BLEND_STATE. */
190 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
191 inst->base_mrf, 2),
192 BRW_REGISTER_TYPE_UD),
193 brw_imm_ud(inst->target));
194 }
195
196 implied_header = brw_null_reg();
197 } else {
198 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
199 }
200
201 brw_pop_insn_state(p);
202 } else {
203 implied_header = brw_null_reg();
204 }
205
206 if (!runtime_check_aads_emit) {
207 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
208 } else {
209 /* This can only happen in gen < 6 */
210 assert(brw->gen < 6);
211
212 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
213
214 /* Check runtime bit to detect if we have to send AA data or not */
215 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
216 brw_AND(p,
217 v1_null_ud,
218 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
219 brw_imm_ud(1<<26));
220 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
221
222 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
223 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
224 {
225 /* Don't send AA data */
226 fire_fb_write(inst, inst->base_mrf+1, implied_header, inst->mlen-1);
227 }
228 brw_land_fwd_jump(p, jmp);
229 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
230 }
231 }
232
233 void
234 fs_generator::generate_blorp_fb_write(fs_inst *inst)
235 {
236 brw_fb_WRITE(p,
237 16 /* dispatch_width */,
238 inst->base_mrf,
239 brw_reg_from_fs_reg(&inst->src[0]),
240 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
241 inst->target,
242 inst->mlen,
243 0,
244 true,
245 inst->header_present);
246 }
247
248 /* Computes the integer pixel x,y values from the origin.
249 *
250 * This is the basis of gl_FragCoord computation, but is also used
251 * pre-gen6 for computing the deltas from v0 for computing
252 * interpolation.
253 */
254 void
255 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
256 {
257 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
258 struct brw_reg src;
259 struct brw_reg deltas;
260
261 if (is_x) {
262 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
263 deltas = brw_imm_v(0x10101010);
264 } else {
265 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
266 deltas = brw_imm_v(0x11001100);
267 }
268
269 if (dispatch_width == 16) {
270 dst = vec16(dst);
271 }
272
273 /* We do this SIMD8 or SIMD16, but since the destination is UW we
274 * don't do compression in the SIMD16 case.
275 */
276 brw_push_insn_state(p);
277 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
278 brw_ADD(p, dst, src, deltas);
279 brw_pop_insn_state(p);
280 }
281
282 void
283 fs_generator::generate_linterp(fs_inst *inst,
284 struct brw_reg dst, struct brw_reg *src)
285 {
286 struct brw_reg delta_x = src[0];
287 struct brw_reg delta_y = src[1];
288 struct brw_reg interp = src[2];
289
290 if (brw->has_pln &&
291 delta_y.nr == delta_x.nr + 1 &&
292 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
293 brw_PLN(p, dst, interp, delta_x);
294 } else {
295 brw_LINE(p, brw_null_reg(), interp, delta_x);
296 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
297 }
298 }
299
300 void
301 fs_generator::generate_math_gen6(fs_inst *inst,
302 struct brw_reg dst,
303 struct brw_reg src0,
304 struct brw_reg src1)
305 {
306 int op = brw_math_function(inst->opcode);
307 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
308
309 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
310 gen6_math(p, dst, op, src0, src1);
311
312 if (dispatch_width == 16) {
313 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
314 gen6_math(p, sechalf(dst), op, sechalf(src0),
315 binop ? sechalf(src1) : brw_null_reg());
316 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
317 }
318 }
319
320 void
321 fs_generator::generate_math_gen4(fs_inst *inst,
322 struct brw_reg dst,
323 struct brw_reg src)
324 {
325 int op = brw_math_function(inst->opcode);
326
327 assert(inst->mlen >= 1);
328
329 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
330 gen4_math(p, dst,
331 op,
332 inst->base_mrf, src,
333 BRW_MATH_DATA_VECTOR,
334 BRW_MATH_PRECISION_FULL);
335
336 if (dispatch_width == 16) {
337 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
338 gen4_math(p, sechalf(dst),
339 op,
340 inst->base_mrf + 1, sechalf(src),
341 BRW_MATH_DATA_VECTOR,
342 BRW_MATH_PRECISION_FULL);
343
344 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
345 }
346 }
347
348 void
349 fs_generator::generate_math_g45(fs_inst *inst,
350 struct brw_reg dst,
351 struct brw_reg src)
352 {
353 if (inst->opcode == SHADER_OPCODE_POW ||
354 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
355 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
356 generate_math_gen4(inst, dst, src);
357 return;
358 }
359
360 int op = brw_math_function(inst->opcode);
361
362 assert(inst->mlen >= 1);
363
364 gen4_math(p, dst,
365 op,
366 inst->base_mrf, src,
367 BRW_MATH_DATA_VECTOR,
368 BRW_MATH_PRECISION_FULL);
369 }
370
371 void
372 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
373 struct brw_reg sampler_index)
374 {
375 int msg_type = -1;
376 int rlen = 4;
377 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
378 uint32_t return_format;
379
380 switch (dst.type) {
381 case BRW_REGISTER_TYPE_D:
382 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
383 break;
384 case BRW_REGISTER_TYPE_UD:
385 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
386 break;
387 default:
388 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
389 break;
390 }
391
392 if (dispatch_width == 16 &&
393 !inst->force_uncompressed && !inst->force_sechalf)
394 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
395
396 if (brw->gen >= 5) {
397 switch (inst->opcode) {
398 case SHADER_OPCODE_TEX:
399 if (inst->shadow_compare) {
400 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
401 } else {
402 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
403 }
404 break;
405 case FS_OPCODE_TXB:
406 if (inst->shadow_compare) {
407 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
408 } else {
409 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
410 }
411 break;
412 case SHADER_OPCODE_TXL:
413 if (inst->shadow_compare) {
414 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
415 } else {
416 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
417 }
418 break;
419 case SHADER_OPCODE_TXS:
420 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
421 break;
422 case SHADER_OPCODE_TXD:
423 if (inst->shadow_compare) {
424 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
425 assert(brw->gen >= 8 || brw->is_haswell);
426 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
427 } else {
428 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
429 }
430 break;
431 case SHADER_OPCODE_TXF:
432 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
433 break;
434 case SHADER_OPCODE_TXF_CMS:
435 if (brw->gen >= 7)
436 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
437 else
438 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
439 break;
440 case SHADER_OPCODE_TXF_UMS:
441 assert(brw->gen >= 7);
442 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
443 break;
444 case SHADER_OPCODE_TXF_MCS:
445 assert(brw->gen >= 7);
446 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
447 break;
448 case SHADER_OPCODE_LOD:
449 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
450 break;
451 case SHADER_OPCODE_TG4:
452 if (inst->shadow_compare) {
453 assert(brw->gen >= 7);
454 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
455 } else {
456 assert(brw->gen >= 6);
457 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
458 }
459 break;
460 case SHADER_OPCODE_TG4_OFFSET:
461 assert(brw->gen >= 7);
462 if (inst->shadow_compare) {
463 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
464 } else {
465 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
466 }
467 break;
468 default:
469 unreachable("not reached");
470 }
471 } else {
472 switch (inst->opcode) {
473 case SHADER_OPCODE_TEX:
474 /* Note that G45 and older determines shadow compare and dispatch width
475 * from message length for most messages.
476 */
477 assert(dispatch_width == 8);
478 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
479 if (inst->shadow_compare) {
480 assert(inst->mlen == 6);
481 } else {
482 assert(inst->mlen <= 4);
483 }
484 break;
485 case FS_OPCODE_TXB:
486 if (inst->shadow_compare) {
487 assert(inst->mlen == 6);
488 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
489 } else {
490 assert(inst->mlen == 9);
491 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
492 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
493 }
494 break;
495 case SHADER_OPCODE_TXL:
496 if (inst->shadow_compare) {
497 assert(inst->mlen == 6);
498 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
499 } else {
500 assert(inst->mlen == 9);
501 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
502 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
503 }
504 break;
505 case SHADER_OPCODE_TXD:
506 /* There is no sample_d_c message; comparisons are done manually */
507 assert(inst->mlen == 7 || inst->mlen == 10);
508 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
509 break;
510 case SHADER_OPCODE_TXF:
511 assert(inst->mlen == 9);
512 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
513 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
514 break;
515 case SHADER_OPCODE_TXS:
516 assert(inst->mlen == 3);
517 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
518 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
519 break;
520 default:
521 unreachable("not reached");
522 }
523 }
524 assert(msg_type != -1);
525
526 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
527 rlen = 8;
528 dst = vec16(dst);
529 }
530
531 if (brw->gen >= 7 && inst->header_present && dispatch_width == 16) {
532 /* The send-from-GRF for SIMD16 texturing with a header has an extra
533 * hardware register allocated to it, which we need to skip over (since
534 * our coordinates in the payload are in the even-numbered registers,
535 * and the header comes right before the first one).
536 */
537 assert(src.file == BRW_GENERAL_REGISTER_FILE);
538 src.nr++;
539 }
540
541 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
542
543 /* Load the message header if present. If there's a texture offset,
544 * we need to set it up explicitly and load the offset bitfield.
545 * Otherwise, we can use an implied move from g0 to the first message reg.
546 */
547 if (inst->header_present) {
548 if (brw->gen < 6 && !inst->texture_offset) {
549 /* Set up an implied move from g0 to the MRF. */
550 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
551 } else {
552 struct brw_reg header_reg;
553
554 if (brw->gen >= 7) {
555 header_reg = src;
556 } else {
557 assert(inst->base_mrf != -1);
558 header_reg = brw_message_reg(inst->base_mrf);
559 }
560
561 brw_push_insn_state(p);
562 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
563 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
564 /* Explicitly set up the message header by copying g0 to the MRF. */
565 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
566
567 if (inst->texture_offset) {
568 /* Set the offset bits in DWord 2. */
569 brw_MOV(p, get_element_ud(header_reg, 2),
570 brw_imm_ud(inst->texture_offset));
571 }
572
573 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index, dst);
574 brw_pop_insn_state(p);
575 }
576 }
577
578 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
579 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
580 ? prog_data->base.binding_table.gather_texture_start
581 : prog_data->base.binding_table.texture_start;
582
583 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
584 uint32_t sampler = sampler_index.dw1.ud;
585
586 brw_SAMPLE(p,
587 retype(dst, BRW_REGISTER_TYPE_UW),
588 inst->base_mrf,
589 src,
590 sampler + base_binding_table_index,
591 sampler % 16,
592 msg_type,
593 rlen,
594 inst->mlen,
595 inst->header_present,
596 simd_mode,
597 return_format);
598
599 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
600 } else {
601 /* Non-const sampler index */
602 /* Note: this clobbers `dst` as a temporary before emitting the send */
603
604 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
605 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
606
607 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
608
609 brw_push_insn_state(p);
610 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
611 brw_set_default_access_mode(p, BRW_ALIGN_1);
612
613 /* Some care required: `sampler` and `temp` may alias:
614 * addr = sampler & 0xff
615 * temp = (sampler << 8) & 0xf00
616 * addr = addr | temp
617 */
618 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
619 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
620 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
621 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
622 brw_OR(p, addr, addr, temp);
623
624 /* a0.0 |= <descriptor> */
625 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
626 brw_set_sampler_message(p, insn_or,
627 0 /* surface */,
628 0 /* sampler */,
629 msg_type,
630 rlen,
631 inst->mlen /* mlen */,
632 inst->header_present /* header */,
633 simd_mode,
634 return_format);
635 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
636 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
637 brw_set_src0(p, insn_or, addr);
638 brw_set_dest(p, insn_or, addr);
639
640
641 /* dst = send(offset, a0.0) */
642 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
643 brw_set_dest(p, insn_send, dst);
644 brw_set_src0(p, insn_send, src);
645 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
646
647 brw_pop_insn_state(p);
648
649 /* visitor knows more than we do about the surface limit required,
650 * so has already done marking.
651 */
652 }
653 }
654
655
656 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
657 * looking like:
658 *
659 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
660 *
661 * Ideally, we want to produce:
662 *
663 * DDX DDY
664 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
665 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
666 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
667 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
668 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
669 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
670 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
671 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
672 *
673 * and add another set of two more subspans if in 16-pixel dispatch mode.
674 *
675 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
676 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
677 * pair. But the ideal approximation may impose a huge performance cost on
678 * sample_d. On at least Haswell, sample_d instruction does some
679 * optimizations if the same LOD is used for all pixels in the subspan.
680 *
681 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
682 * appropriate swizzling.
683 */
684 void
685 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
686 struct brw_reg quality)
687 {
688 unsigned vstride, width;
689 assert(quality.file == BRW_IMMEDIATE_VALUE);
690 assert(quality.type == BRW_REGISTER_TYPE_D);
691
692 int quality_value = quality.dw1.d;
693
694 if (quality_value == BRW_DERIVATIVE_FINE ||
695 (key->high_quality_derivatives && quality_value != BRW_DERIVATIVE_COARSE)) {
696 /* produce accurate derivatives */
697 vstride = BRW_VERTICAL_STRIDE_2;
698 width = BRW_WIDTH_2;
699 }
700 else {
701 /* replicate the derivative at the top-left pixel to other pixels */
702 vstride = BRW_VERTICAL_STRIDE_4;
703 width = BRW_WIDTH_4;
704 }
705
706 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
707 BRW_REGISTER_TYPE_F,
708 vstride,
709 width,
710 BRW_HORIZONTAL_STRIDE_0,
711 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
712 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
713 BRW_REGISTER_TYPE_F,
714 vstride,
715 width,
716 BRW_HORIZONTAL_STRIDE_0,
717 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
718 brw_ADD(p, dst, src0, negate(src1));
719 }
720
721 /* The negate_value boolean is used to negate the derivative computation for
722 * FBOs, since they place the origin at the upper left instead of the lower
723 * left.
724 */
725 void
726 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
727 struct brw_reg quality, bool negate_value)
728 {
729 assert(quality.file == BRW_IMMEDIATE_VALUE);
730 assert(quality.type == BRW_REGISTER_TYPE_D);
731
732 int quality_value = quality.dw1.d;
733
734 if (quality_value == BRW_DERIVATIVE_FINE ||
735 (key->high_quality_derivatives && quality_value != BRW_DERIVATIVE_COARSE)) {
736 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
737 * Region Restrictions):
738 *
739 * In Align16 access mode, SIMD16 is not allowed for DW operations
740 * and SIMD8 is not allowed for DF operations.
741 *
742 * In this context, "DW operations" means "operations acting on 32-bit
743 * values", so it includes operations on floats.
744 *
745 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
746 * (Instruction Compression -> Rules and Restrictions):
747 *
748 * A compressed instruction must be in Align1 access mode. Align16
749 * mode instructions cannot be compressed.
750 *
751 * Similar text exists in the g45 PRM.
752 *
753 * On these platforms, if we're building a SIMD16 shader, we need to
754 * manually unroll to a pair of SIMD8 instructions.
755 */
756 bool unroll_to_simd8 =
757 (dispatch_width == 16 &&
758 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
759
760 /* produce accurate derivatives */
761 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
762 BRW_REGISTER_TYPE_F,
763 BRW_VERTICAL_STRIDE_4,
764 BRW_WIDTH_4,
765 BRW_HORIZONTAL_STRIDE_1,
766 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
767 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
768 BRW_REGISTER_TYPE_F,
769 BRW_VERTICAL_STRIDE_4,
770 BRW_WIDTH_4,
771 BRW_HORIZONTAL_STRIDE_1,
772 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
773 brw_push_insn_state(p);
774 brw_set_default_access_mode(p, BRW_ALIGN_16);
775 if (unroll_to_simd8)
776 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
777 if (negate_value)
778 brw_ADD(p, dst, src1, negate(src0));
779 else
780 brw_ADD(p, dst, src0, negate(src1));
781 if (unroll_to_simd8) {
782 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
783 src0 = sechalf(src0);
784 src1 = sechalf(src1);
785 dst = sechalf(dst);
786 if (negate_value)
787 brw_ADD(p, dst, src1, negate(src0));
788 else
789 brw_ADD(p, dst, src0, negate(src1));
790 }
791 brw_pop_insn_state(p);
792 } else {
793 /* replicate the derivative at the top-left pixel to other pixels */
794 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
795 BRW_REGISTER_TYPE_F,
796 BRW_VERTICAL_STRIDE_4,
797 BRW_WIDTH_4,
798 BRW_HORIZONTAL_STRIDE_0,
799 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
800 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
801 BRW_REGISTER_TYPE_F,
802 BRW_VERTICAL_STRIDE_4,
803 BRW_WIDTH_4,
804 BRW_HORIZONTAL_STRIDE_0,
805 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
806 if (negate_value)
807 brw_ADD(p, dst, src1, negate(src0));
808 else
809 brw_ADD(p, dst, src0, negate(src1));
810 }
811 }
812
813 void
814 fs_generator::generate_discard_jump(fs_inst *inst)
815 {
816 assert(brw->gen >= 6);
817
818 /* This HALT will be patched up at FB write time to point UIP at the end of
819 * the program, and at brw_uip_jip() JIP will be set to the end of the
820 * current block (or the program).
821 */
822 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
823
824 brw_push_insn_state(p);
825 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
826 gen6_HALT(p);
827 brw_pop_insn_state(p);
828 }
829
830 void
831 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
832 {
833 assert(inst->mlen != 0);
834
835 brw_MOV(p,
836 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
837 retype(src, BRW_REGISTER_TYPE_UD));
838 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
839 dispatch_width / 8, inst->offset);
840 }
841
842 void
843 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
844 {
845 assert(inst->mlen != 0);
846
847 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
848 dispatch_width / 8, inst->offset);
849 }
850
851 void
852 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
853 {
854 gen7_block_read_scratch(p, dst, dispatch_width / 8, inst->offset);
855 }
856
857 void
858 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
859 struct brw_reg dst,
860 struct brw_reg index,
861 struct brw_reg offset)
862 {
863 assert(inst->mlen != 0);
864
865 assert(index.file == BRW_IMMEDIATE_VALUE &&
866 index.type == BRW_REGISTER_TYPE_UD);
867 uint32_t surf_index = index.dw1.ud;
868
869 assert(offset.file == BRW_IMMEDIATE_VALUE &&
870 offset.type == BRW_REGISTER_TYPE_UD);
871 uint32_t read_offset = offset.dw1.ud;
872
873 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
874 read_offset, surf_index);
875
876 brw_mark_surface_used(&prog_data->base, surf_index);
877 }
878
879 void
880 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
881 struct brw_reg dst,
882 struct brw_reg index,
883 struct brw_reg offset)
884 {
885 assert(inst->mlen == 0);
886 assert(index.type == BRW_REGISTER_TYPE_UD);
887
888 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
889 /* Reference just the dword we need, to avoid angering validate_reg(). */
890 offset = brw_vec1_grf(offset.nr, 0);
891
892 /* We use the SIMD4x2 mode because we want to end up with 4 components in
893 * the destination loaded consecutively from the same offset (which appears
894 * in the first component, and the rest are ignored).
895 */
896 dst.width = BRW_WIDTH_4;
897
898 if (index.file == BRW_IMMEDIATE_VALUE) {
899
900 uint32_t surf_index = index.dw1.ud;
901
902 brw_push_insn_state(p);
903 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
904 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
905 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
906 brw_pop_insn_state(p);
907
908 brw_set_dest(p, send, dst);
909 brw_set_src0(p, send, offset);
910 brw_set_sampler_message(p, send,
911 surf_index,
912 0, /* LD message ignores sampler unit */
913 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
914 1, /* rlen */
915 1, /* mlen */
916 false, /* no header */
917 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
918 0);
919
920 brw_mark_surface_used(&prog_data->base, surf_index);
921
922 } else {
923
924 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
925
926 brw_push_insn_state(p);
927 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
928 brw_set_default_access_mode(p, BRW_ALIGN_1);
929
930 /* a0.0 = surf_index & 0xff */
931 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
932 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
933 brw_set_dest(p, insn_and, addr);
934 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
935 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
936
937
938 /* a0.0 |= <descriptor> */
939 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
940 brw_set_sampler_message(p, insn_or,
941 0 /* surface */,
942 0 /* sampler */,
943 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
944 1 /* rlen */,
945 1 /* mlen */,
946 false /* header */,
947 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
948 0);
949 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
950 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
951 brw_set_src0(p, insn_or, addr);
952 brw_set_dest(p, insn_or, addr);
953
954
955 /* dst = send(offset, a0.0) */
956 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
957 brw_set_dest(p, insn_send, dst);
958 brw_set_src0(p, insn_send, offset);
959 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
960
961 brw_pop_insn_state(p);
962
963 /* visitor knows more than we do about the surface limit required,
964 * so has already done marking.
965 */
966
967 }
968 }
969
970 void
971 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
972 struct brw_reg dst,
973 struct brw_reg index,
974 struct brw_reg offset)
975 {
976 assert(brw->gen < 7); /* Should use the gen7 variant. */
977 assert(inst->header_present);
978 assert(inst->mlen);
979
980 assert(index.file == BRW_IMMEDIATE_VALUE &&
981 index.type == BRW_REGISTER_TYPE_UD);
982 uint32_t surf_index = index.dw1.ud;
983
984 uint32_t simd_mode, rlen, msg_type;
985 if (dispatch_width == 16) {
986 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
987 rlen = 8;
988 } else {
989 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
990 rlen = 4;
991 }
992
993 if (brw->gen >= 5)
994 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
995 else {
996 /* We always use the SIMD16 message so that we only have to load U, and
997 * not V or R.
998 */
999 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1000 assert(inst->mlen == 3);
1001 assert(inst->regs_written == 8);
1002 rlen = 8;
1003 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1004 }
1005
1006 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1007 BRW_REGISTER_TYPE_D);
1008 brw_MOV(p, offset_mrf, offset);
1009
1010 struct brw_reg header = brw_vec8_grf(0, 0);
1011 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1012
1013 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1014 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
1015 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1016 brw_set_src0(p, send, header);
1017 if (brw->gen < 6)
1018 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
1019
1020 /* Our surface is set up as floats, regardless of what actual data is
1021 * stored in it.
1022 */
1023 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1024 brw_set_sampler_message(p, send,
1025 surf_index,
1026 0, /* sampler (unused) */
1027 msg_type,
1028 rlen,
1029 inst->mlen,
1030 inst->header_present,
1031 simd_mode,
1032 return_format);
1033
1034 brw_mark_surface_used(&prog_data->base, surf_index);
1035 }
1036
1037 void
1038 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1039 struct brw_reg dst,
1040 struct brw_reg index,
1041 struct brw_reg offset)
1042 {
1043 assert(brw->gen >= 7);
1044 /* Varying-offset pull constant loads are treated as a normal expression on
1045 * gen7, so the fact that it's a send message is hidden at the IR level.
1046 */
1047 assert(!inst->header_present);
1048 assert(!inst->mlen);
1049 assert(index.type == BRW_REGISTER_TYPE_UD);
1050
1051 uint32_t simd_mode, rlen, mlen;
1052 if (dispatch_width == 16) {
1053 mlen = 2;
1054 rlen = 8;
1055 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1056 } else {
1057 mlen = 1;
1058 rlen = 4;
1059 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1060 }
1061
1062 if (index.file == BRW_IMMEDIATE_VALUE) {
1063
1064 uint32_t surf_index = index.dw1.ud;
1065
1066 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1067 brw_set_dest(p, send, dst);
1068 brw_set_src0(p, send, offset);
1069 brw_set_sampler_message(p, send,
1070 surf_index,
1071 0, /* LD message ignores sampler unit */
1072 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1073 rlen,
1074 mlen,
1075 false, /* no header */
1076 simd_mode,
1077 0);
1078
1079 brw_mark_surface_used(&prog_data->base, surf_index);
1080
1081 } else {
1082
1083 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1084
1085 brw_push_insn_state(p);
1086 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1087 brw_set_default_access_mode(p, BRW_ALIGN_1);
1088
1089 /* a0.0 = surf_index & 0xff */
1090 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1091 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1092 brw_set_dest(p, insn_and, addr);
1093 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1094 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1095
1096
1097 /* a0.0 |= <descriptor> */
1098 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1099 brw_set_sampler_message(p, insn_or,
1100 0 /* surface */,
1101 0 /* sampler */,
1102 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1103 rlen /* rlen */,
1104 mlen /* mlen */,
1105 false /* header */,
1106 simd_mode,
1107 0);
1108 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1109 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1110 brw_set_src0(p, insn_or, addr);
1111 brw_set_dest(p, insn_or, addr);
1112
1113
1114 /* dst = send(offset, a0.0) */
1115 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1116 brw_set_dest(p, insn_send, dst);
1117 brw_set_src0(p, insn_send, offset);
1118 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1119
1120 brw_pop_insn_state(p);
1121
1122 /* visitor knows more than we do about the surface limit required,
1123 * so has already done marking.
1124 */
1125 }
1126 }
1127
1128 /**
1129 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1130 * into the flags register (f0.0).
1131 *
1132 * Used only on Gen6 and above.
1133 */
1134 void
1135 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1136 {
1137 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1138 struct brw_reg dispatch_mask;
1139
1140 if (brw->gen >= 6)
1141 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1142 else
1143 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1144
1145 brw_push_insn_state(p);
1146 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1147 brw_MOV(p, flags, dispatch_mask);
1148 brw_pop_insn_state(p);
1149 }
1150
1151 void
1152 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1153 struct brw_reg dst,
1154 struct brw_reg src,
1155 struct brw_reg msg_data,
1156 unsigned msg_type)
1157 {
1158 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1159 msg_data.type == BRW_REGISTER_TYPE_UD);
1160
1161 brw_pixel_interpolator_query(p,
1162 retype(dst, BRW_REGISTER_TYPE_UW),
1163 src,
1164 inst->pi_noperspective,
1165 msg_type,
1166 msg_data.dw1.ud,
1167 inst->mlen,
1168 inst->regs_written);
1169 }
1170
1171
1172 static uint32_t brw_file_from_reg(fs_reg *reg)
1173 {
1174 switch (reg->file) {
1175 case GRF:
1176 return BRW_GENERAL_REGISTER_FILE;
1177 case MRF:
1178 return BRW_MESSAGE_REGISTER_FILE;
1179 case IMM:
1180 return BRW_IMMEDIATE_VALUE;
1181 default:
1182 unreachable("not reached");
1183 }
1184 }
1185
1186 struct brw_reg
1187 brw_reg_from_fs_reg(fs_reg *reg)
1188 {
1189 struct brw_reg brw_reg;
1190
1191 switch (reg->file) {
1192 case GRF:
1193 case MRF:
1194 if (reg->stride == 0) {
1195 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
1196 } else {
1197 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1198 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
1199 }
1200
1201 brw_reg = retype(brw_reg, reg->type);
1202 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
1203 break;
1204 case IMM:
1205 switch (reg->type) {
1206 case BRW_REGISTER_TYPE_F:
1207 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
1208 break;
1209 case BRW_REGISTER_TYPE_D:
1210 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
1211 break;
1212 case BRW_REGISTER_TYPE_UD:
1213 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
1214 break;
1215 default:
1216 unreachable("not reached");
1217 }
1218 break;
1219 case HW_REG:
1220 assert(reg->type == reg->fixed_hw_reg.type);
1221 brw_reg = reg->fixed_hw_reg;
1222 break;
1223 case BAD_FILE:
1224 /* Probably unused. */
1225 brw_reg = brw_null_reg();
1226 break;
1227 case UNIFORM:
1228 unreachable("not reached");
1229 default:
1230 unreachable("not reached");
1231 }
1232 if (reg->abs)
1233 brw_reg = brw_abs(brw_reg);
1234 if (reg->negate)
1235 brw_reg = negate(brw_reg);
1236
1237 return brw_reg;
1238 }
1239
1240 /**
1241 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1242 * sampler LD messages.
1243 *
1244 * We don't want to bake it into the send message's code generation because
1245 * that means we don't get a chance to schedule the instructions.
1246 */
1247 void
1248 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1249 struct brw_reg dst,
1250 struct brw_reg value)
1251 {
1252 assert(value.file == BRW_IMMEDIATE_VALUE);
1253
1254 brw_push_insn_state(p);
1255 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1256 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1257 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1258 brw_pop_insn_state(p);
1259 }
1260
1261 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1262 * (when mask is passed as a uniform) of register mask before moving it
1263 * to register dst.
1264 */
1265 void
1266 fs_generator::generate_set_omask(fs_inst *inst,
1267 struct brw_reg dst,
1268 struct brw_reg mask)
1269 {
1270 bool stride_8_8_1 =
1271 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1272 mask.width == BRW_WIDTH_8 &&
1273 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1274
1275 bool stride_0_1_0 =
1276 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1277 mask.width == BRW_WIDTH_1 &&
1278 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1279
1280 assert(stride_8_8_1 || stride_0_1_0);
1281 assert(dst.type == BRW_REGISTER_TYPE_UW);
1282
1283 if (dispatch_width == 16)
1284 dst = vec16(dst);
1285 brw_push_insn_state(p);
1286 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1287 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1288
1289 if (stride_8_8_1) {
1290 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1291 } else if (stride_0_1_0) {
1292 brw_MOV(p, dst, retype(mask, dst.type));
1293 }
1294 brw_pop_insn_state(p);
1295 }
1296
1297 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1298 * the ADD instruction.
1299 */
1300 void
1301 fs_generator::generate_set_sample_id(fs_inst *inst,
1302 struct brw_reg dst,
1303 struct brw_reg src0,
1304 struct brw_reg src1)
1305 {
1306 assert(dst.type == BRW_REGISTER_TYPE_D ||
1307 dst.type == BRW_REGISTER_TYPE_UD);
1308 assert(src0.type == BRW_REGISTER_TYPE_D ||
1309 src0.type == BRW_REGISTER_TYPE_UD);
1310
1311 brw_push_insn_state(p);
1312 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1313 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1314 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1315 brw_ADD(p, dst, src0, reg);
1316 if (dispatch_width == 16)
1317 brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
1318 brw_pop_insn_state(p);
1319 }
1320
1321 /**
1322 * Change the register's data type from UD to W, doubling the strides in order
1323 * to compensate for halving the data type width.
1324 */
1325 static struct brw_reg
1326 ud_reg_to_w(struct brw_reg r)
1327 {
1328 assert(r.type == BRW_REGISTER_TYPE_UD);
1329 r.type = BRW_REGISTER_TYPE_W;
1330
1331 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1332 * doubles the real stride.
1333 */
1334 if (r.hstride != 0)
1335 ++r.hstride;
1336 if (r.vstride != 0)
1337 ++r.vstride;
1338
1339 return r;
1340 }
1341
1342 void
1343 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1344 struct brw_reg dst,
1345 struct brw_reg x,
1346 struct brw_reg y)
1347 {
1348 assert(brw->gen >= 7);
1349 assert(dst.type == BRW_REGISTER_TYPE_UD);
1350 assert(x.type == BRW_REGISTER_TYPE_F);
1351 assert(y.type == BRW_REGISTER_TYPE_F);
1352
1353 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1354 *
1355 * Because this instruction does not have a 16-bit floating-point type,
1356 * the destination data type must be Word (W).
1357 *
1358 * The destination must be DWord-aligned and specify a horizontal stride
1359 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1360 * each destination channel and the upper word is not modified.
1361 */
1362 struct brw_reg dst_w = ud_reg_to_w(dst);
1363
1364 /* Give each 32-bit channel of dst the form below , where "." means
1365 * unchanged.
1366 * 0x....hhhh
1367 */
1368 brw_F32TO16(p, dst_w, y);
1369
1370 /* Now the form:
1371 * 0xhhhh0000
1372 */
1373 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1374
1375 /* And, finally the form of packHalf2x16's output:
1376 * 0xhhhhllll
1377 */
1378 brw_F32TO16(p, dst_w, x);
1379 }
1380
1381 void
1382 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1383 struct brw_reg dst,
1384 struct brw_reg src)
1385 {
1386 assert(brw->gen >= 7);
1387 assert(dst.type == BRW_REGISTER_TYPE_F);
1388 assert(src.type == BRW_REGISTER_TYPE_UD);
1389
1390 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1391 *
1392 * Because this instruction does not have a 16-bit floating-point type,
1393 * the source data type must be Word (W). The destination type must be
1394 * F (Float).
1395 */
1396 struct brw_reg src_w = ud_reg_to_w(src);
1397
1398 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1399 * For the Y case, we wish to access only the upper word; therefore
1400 * a 16-bit subregister offset is needed.
1401 */
1402 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1403 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1404 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1405 src_w.subnr += 2;
1406
1407 brw_F16TO32(p, dst, src_w);
1408 }
1409
1410 void
1411 fs_generator::generate_shader_time_add(fs_inst *inst,
1412 struct brw_reg payload,
1413 struct brw_reg offset,
1414 struct brw_reg value)
1415 {
1416 assert(brw->gen >= 7);
1417 brw_push_insn_state(p);
1418 brw_set_default_mask_control(p, true);
1419
1420 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1421 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1422 offset.type);
1423 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1424 value.type);
1425
1426 assert(offset.file == BRW_IMMEDIATE_VALUE);
1427 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1428 value.width = BRW_WIDTH_1;
1429 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1430 value.vstride = BRW_VERTICAL_STRIDE_0;
1431 } else {
1432 assert(value.file == BRW_IMMEDIATE_VALUE);
1433 }
1434
1435 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1436 * case, and we don't really care about squeezing every bit of performance
1437 * out of this path, so we just emit the MOVs from here.
1438 */
1439 brw_MOV(p, payload_offset, offset);
1440 brw_MOV(p, payload_value, value);
1441 brw_shader_time_add(p, payload,
1442 prog_data->base.binding_table.shader_time_start);
1443 brw_pop_insn_state(p);
1444
1445 brw_mark_surface_used(&prog_data->base,
1446 prog_data->base.binding_table.shader_time_start);
1447 }
1448
1449 void
1450 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1451 struct brw_reg atomic_op,
1452 struct brw_reg surf_index)
1453 {
1454 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1455 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1456 surf_index.file == BRW_IMMEDIATE_VALUE &&
1457 surf_index.type == BRW_REGISTER_TYPE_UD);
1458
1459 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1460 atomic_op.dw1.ud, surf_index.dw1.ud,
1461 inst->mlen, dispatch_width / 8);
1462
1463 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1464 }
1465
1466 void
1467 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1468 struct brw_reg surf_index)
1469 {
1470 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1471 surf_index.type == BRW_REGISTER_TYPE_UD);
1472
1473 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1474 surf_index.dw1.ud,
1475 inst->mlen, dispatch_width / 8);
1476
1477 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1478 }
1479
1480 void
1481 fs_generator::generate_code(exec_list *instructions)
1482 {
1483 int start_offset = p->next_insn_offset;
1484
1485 struct annotation_info annotation;
1486 memset(&annotation, 0, sizeof(annotation));
1487
1488 cfg_t *cfg = NULL;
1489 if (unlikely(debug_flag))
1490 cfg = new(mem_ctx) cfg_t(instructions);
1491
1492 foreach_in_list(fs_inst, inst, instructions) {
1493 struct brw_reg src[3], dst;
1494 unsigned int last_insn_offset = p->next_insn_offset;
1495
1496 if (unlikely(debug_flag))
1497 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1498
1499 for (unsigned int i = 0; i < inst->sources; i++) {
1500 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1501
1502 /* The accumulator result appears to get used for the
1503 * conditional modifier generation. When negating a UD
1504 * value, there is a 33rd bit generated for the sign in the
1505 * accumulator value, so now you can't check, for example,
1506 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1507 */
1508 assert(!inst->conditional_mod ||
1509 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1510 !inst->src[i].negate);
1511 }
1512 dst = brw_reg_from_fs_reg(&inst->dst);
1513
1514 brw_set_default_predicate_control(p, inst->predicate);
1515 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1516 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1517 brw_set_default_saturate(p, inst->saturate);
1518 brw_set_default_mask_control(p, inst->force_writemask_all);
1519 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1520
1521 if (inst->force_uncompressed || dispatch_width == 8) {
1522 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1523 } else if (inst->force_sechalf) {
1524 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1525 } else {
1526 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1527 }
1528
1529 switch (inst->opcode) {
1530 case BRW_OPCODE_MOV:
1531 brw_MOV(p, dst, src[0]);
1532 break;
1533 case BRW_OPCODE_ADD:
1534 brw_ADD(p, dst, src[0], src[1]);
1535 break;
1536 case BRW_OPCODE_MUL:
1537 brw_MUL(p, dst, src[0], src[1]);
1538 break;
1539 case BRW_OPCODE_AVG:
1540 brw_AVG(p, dst, src[0], src[1]);
1541 break;
1542 case BRW_OPCODE_MACH:
1543 brw_MACH(p, dst, src[0], src[1]);
1544 break;
1545
1546 case BRW_OPCODE_MAD:
1547 assert(brw->gen >= 6);
1548 brw_set_default_access_mode(p, BRW_ALIGN_16);
1549 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1550 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1551 brw_MAD(p, dst, src[0], src[1], src[2]);
1552 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1553 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1554 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1555 } else {
1556 brw_MAD(p, dst, src[0], src[1], src[2]);
1557 }
1558 brw_set_default_access_mode(p, BRW_ALIGN_1);
1559 break;
1560
1561 case BRW_OPCODE_LRP:
1562 assert(brw->gen >= 6);
1563 brw_set_default_access_mode(p, BRW_ALIGN_16);
1564 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1565 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1566 brw_LRP(p, dst, src[0], src[1], src[2]);
1567 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1568 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1569 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1570 } else {
1571 brw_LRP(p, dst, src[0], src[1], src[2]);
1572 }
1573 brw_set_default_access_mode(p, BRW_ALIGN_1);
1574 break;
1575
1576 case BRW_OPCODE_FRC:
1577 brw_FRC(p, dst, src[0]);
1578 break;
1579 case BRW_OPCODE_RNDD:
1580 brw_RNDD(p, dst, src[0]);
1581 break;
1582 case BRW_OPCODE_RNDE:
1583 brw_RNDE(p, dst, src[0]);
1584 break;
1585 case BRW_OPCODE_RNDZ:
1586 brw_RNDZ(p, dst, src[0]);
1587 break;
1588
1589 case BRW_OPCODE_AND:
1590 brw_AND(p, dst, src[0], src[1]);
1591 break;
1592 case BRW_OPCODE_OR:
1593 brw_OR(p, dst, src[0], src[1]);
1594 break;
1595 case BRW_OPCODE_XOR:
1596 brw_XOR(p, dst, src[0], src[1]);
1597 break;
1598 case BRW_OPCODE_NOT:
1599 brw_NOT(p, dst, src[0]);
1600 break;
1601 case BRW_OPCODE_ASR:
1602 brw_ASR(p, dst, src[0], src[1]);
1603 break;
1604 case BRW_OPCODE_SHR:
1605 brw_SHR(p, dst, src[0], src[1]);
1606 break;
1607 case BRW_OPCODE_SHL:
1608 brw_SHL(p, dst, src[0], src[1]);
1609 break;
1610 case BRW_OPCODE_F32TO16:
1611 assert(brw->gen >= 7);
1612 brw_F32TO16(p, dst, src[0]);
1613 break;
1614 case BRW_OPCODE_F16TO32:
1615 assert(brw->gen >= 7);
1616 brw_F16TO32(p, dst, src[0]);
1617 break;
1618 case BRW_OPCODE_CMP:
1619 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1620 break;
1621 case BRW_OPCODE_SEL:
1622 brw_SEL(p, dst, src[0], src[1]);
1623 break;
1624 case BRW_OPCODE_BFREV:
1625 assert(brw->gen >= 7);
1626 /* BFREV only supports UD type for src and dst. */
1627 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1628 retype(src[0], BRW_REGISTER_TYPE_UD));
1629 break;
1630 case BRW_OPCODE_FBH:
1631 assert(brw->gen >= 7);
1632 /* FBH only supports UD type for dst. */
1633 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1634 break;
1635 case BRW_OPCODE_FBL:
1636 assert(brw->gen >= 7);
1637 /* FBL only supports UD type for dst. */
1638 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1639 break;
1640 case BRW_OPCODE_CBIT:
1641 assert(brw->gen >= 7);
1642 /* CBIT only supports UD type for dst. */
1643 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1644 break;
1645 case BRW_OPCODE_ADDC:
1646 assert(brw->gen >= 7);
1647 brw_ADDC(p, dst, src[0], src[1]);
1648 break;
1649 case BRW_OPCODE_SUBB:
1650 assert(brw->gen >= 7);
1651 brw_SUBB(p, dst, src[0], src[1]);
1652 break;
1653 case BRW_OPCODE_MAC:
1654 brw_MAC(p, dst, src[0], src[1]);
1655 break;
1656
1657 case BRW_OPCODE_BFE:
1658 assert(brw->gen >= 7);
1659 brw_set_default_access_mode(p, BRW_ALIGN_16);
1660 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1661 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1662 brw_BFE(p, dst, src[0], src[1], src[2]);
1663 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1664 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1665 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1666 } else {
1667 brw_BFE(p, dst, src[0], src[1], src[2]);
1668 }
1669 brw_set_default_access_mode(p, BRW_ALIGN_1);
1670 break;
1671
1672 case BRW_OPCODE_BFI1:
1673 assert(brw->gen >= 7);
1674 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1675 * should
1676 *
1677 * "Force BFI instructions to be executed always in SIMD8."
1678 */
1679 if (dispatch_width == 16 && brw->is_haswell) {
1680 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1681 brw_BFI1(p, dst, src[0], src[1]);
1682 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1683 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1684 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1685 } else {
1686 brw_BFI1(p, dst, src[0], src[1]);
1687 }
1688 break;
1689 case BRW_OPCODE_BFI2:
1690 assert(brw->gen >= 7);
1691 brw_set_default_access_mode(p, BRW_ALIGN_16);
1692 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1693 * should
1694 *
1695 * "Force BFI instructions to be executed always in SIMD8."
1696 *
1697 * Otherwise we would be able to emit compressed instructions like we
1698 * do for the other three-source instructions.
1699 */
1700 if (dispatch_width == 16) {
1701 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1702 brw_BFI2(p, dst, src[0], src[1], src[2]);
1703 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1704 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1705 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1706 } else {
1707 brw_BFI2(p, dst, src[0], src[1], src[2]);
1708 }
1709 brw_set_default_access_mode(p, BRW_ALIGN_1);
1710 break;
1711
1712 case BRW_OPCODE_IF:
1713 if (inst->src[0].file != BAD_FILE) {
1714 /* The instruction has an embedded compare (only allowed on gen6) */
1715 assert(brw->gen == 6);
1716 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1717 } else {
1718 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1719 }
1720 break;
1721
1722 case BRW_OPCODE_ELSE:
1723 brw_ELSE(p);
1724 break;
1725 case BRW_OPCODE_ENDIF:
1726 brw_ENDIF(p);
1727 break;
1728
1729 case BRW_OPCODE_DO:
1730 brw_DO(p, BRW_EXECUTE_8);
1731 break;
1732
1733 case BRW_OPCODE_BREAK:
1734 brw_BREAK(p);
1735 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1736 break;
1737 case BRW_OPCODE_CONTINUE:
1738 brw_CONT(p);
1739 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1740 break;
1741
1742 case BRW_OPCODE_WHILE:
1743 brw_WHILE(p);
1744 break;
1745
1746 case SHADER_OPCODE_RCP:
1747 case SHADER_OPCODE_RSQ:
1748 case SHADER_OPCODE_SQRT:
1749 case SHADER_OPCODE_EXP2:
1750 case SHADER_OPCODE_LOG2:
1751 case SHADER_OPCODE_SIN:
1752 case SHADER_OPCODE_COS:
1753 assert(brw->gen < 6 || inst->mlen == 0);
1754 if (brw->gen >= 7) {
1755 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1756 brw_null_reg());
1757 } else if (brw->gen == 6) {
1758 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1759 } else if (brw->gen == 5 || brw->is_g4x) {
1760 generate_math_g45(inst, dst, src[0]);
1761 } else {
1762 generate_math_gen4(inst, dst, src[0]);
1763 }
1764 break;
1765 case SHADER_OPCODE_INT_QUOTIENT:
1766 case SHADER_OPCODE_INT_REMAINDER:
1767 case SHADER_OPCODE_POW:
1768 assert(brw->gen < 6 || inst->mlen == 0);
1769 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1770 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1771 } else if (brw->gen >= 6) {
1772 generate_math_gen6(inst, dst, src[0], src[1]);
1773 } else {
1774 generate_math_gen4(inst, dst, src[0]);
1775 }
1776 break;
1777 case FS_OPCODE_PIXEL_X:
1778 generate_pixel_xy(dst, true);
1779 break;
1780 case FS_OPCODE_PIXEL_Y:
1781 generate_pixel_xy(dst, false);
1782 break;
1783 case FS_OPCODE_CINTERP:
1784 brw_MOV(p, dst, src[0]);
1785 break;
1786 case FS_OPCODE_LINTERP:
1787 generate_linterp(inst, dst, src);
1788 break;
1789 case SHADER_OPCODE_TEX:
1790 case FS_OPCODE_TXB:
1791 case SHADER_OPCODE_TXD:
1792 case SHADER_OPCODE_TXF:
1793 case SHADER_OPCODE_TXF_CMS:
1794 case SHADER_OPCODE_TXF_UMS:
1795 case SHADER_OPCODE_TXF_MCS:
1796 case SHADER_OPCODE_TXL:
1797 case SHADER_OPCODE_TXS:
1798 case SHADER_OPCODE_LOD:
1799 case SHADER_OPCODE_TG4:
1800 case SHADER_OPCODE_TG4_OFFSET:
1801 generate_tex(inst, dst, src[0], src[1]);
1802 break;
1803 case FS_OPCODE_DDX:
1804 generate_ddx(inst, dst, src[0], src[1]);
1805 break;
1806 case FS_OPCODE_DDY:
1807 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1808 * guarantee that key->render_to_fbo is set).
1809 */
1810 assert(fp->UsesDFdy);
1811 generate_ddy(inst, dst, src[0], src[1], key->render_to_fbo);
1812 break;
1813
1814 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1815 generate_scratch_write(inst, src[0]);
1816 break;
1817
1818 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1819 generate_scratch_read(inst, dst);
1820 break;
1821
1822 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1823 generate_scratch_read_gen7(inst, dst);
1824 break;
1825
1826 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1827 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1828 break;
1829
1830 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1831 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1832 break;
1833
1834 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1835 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1836 break;
1837
1838 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1839 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1840 break;
1841
1842 case FS_OPCODE_FB_WRITE:
1843 generate_fb_write(inst);
1844 break;
1845
1846 case FS_OPCODE_BLORP_FB_WRITE:
1847 generate_blorp_fb_write(inst);
1848 break;
1849
1850 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1851 generate_mov_dispatch_to_flags(inst);
1852 break;
1853
1854 case FS_OPCODE_DISCARD_JUMP:
1855 generate_discard_jump(inst);
1856 break;
1857
1858 case SHADER_OPCODE_SHADER_TIME_ADD:
1859 generate_shader_time_add(inst, src[0], src[1], src[2]);
1860 break;
1861
1862 case SHADER_OPCODE_UNTYPED_ATOMIC:
1863 generate_untyped_atomic(inst, dst, src[0], src[1]);
1864 break;
1865
1866 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1867 generate_untyped_surface_read(inst, dst, src[0]);
1868 break;
1869
1870 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1871 generate_set_simd4x2_offset(inst, dst, src[0]);
1872 break;
1873
1874 case FS_OPCODE_SET_OMASK:
1875 generate_set_omask(inst, dst, src[0]);
1876 break;
1877
1878 case FS_OPCODE_SET_SAMPLE_ID:
1879 generate_set_sample_id(inst, dst, src[0], src[1]);
1880 break;
1881
1882 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1883 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1884 break;
1885
1886 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1887 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1888 generate_unpack_half_2x16_split(inst, dst, src[0]);
1889 break;
1890
1891 case FS_OPCODE_PLACEHOLDER_HALT:
1892 /* This is the place where the final HALT needs to be inserted if
1893 * we've emitted any discards. If not, this will emit no code.
1894 */
1895 if (!patch_discard_jumps_to_fb_writes()) {
1896 if (unlikely(debug_flag)) {
1897 annotation.ann_count--;
1898 }
1899 }
1900 break;
1901
1902 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
1903 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1904 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
1905 break;
1906
1907 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
1908 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1909 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
1910 break;
1911
1912 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
1913 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1914 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
1915 break;
1916
1917 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
1918 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1919 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
1920 break;
1921
1922 default:
1923 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1924 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1925 opcode_descs[inst->opcode].name);
1926 } else {
1927 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1928 }
1929 abort();
1930
1931 case SHADER_OPCODE_LOAD_PAYLOAD:
1932 unreachable("Should be lowered by lower_load_payload()");
1933 }
1934
1935 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1936 assert(p->next_insn_offset == last_insn_offset + 16 ||
1937 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1938 "emitting more than 1 instruction");
1939
1940 brw_inst *last = &p->store[last_insn_offset / 16];
1941
1942 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
1943 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
1944 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
1945 }
1946 }
1947
1948 brw_set_uip_jip(p);
1949 annotation_finalize(&annotation, p->next_insn_offset);
1950
1951 int before_size = p->next_insn_offset - start_offset;
1952 brw_compact_instructions(p, start_offset, annotation.ann_count,
1953 annotation.ann);
1954 int after_size = p->next_insn_offset - start_offset;
1955
1956 if (unlikely(debug_flag)) {
1957 if (prog) {
1958 fprintf(stderr,
1959 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
1960 prog->Label ? prog->Label : "unnamed",
1961 prog->Name, dispatch_width);
1962 } else if (fp) {
1963 fprintf(stderr,
1964 "Native code for fragment program %d (SIMD%d dispatch):\n",
1965 fp->Base.Id, dispatch_width);
1966 } else {
1967 fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
1968 dispatch_width);
1969 }
1970 fprintf(stderr, "SIMD%d shader: %d instructions. Compacted %d to %d"
1971 " bytes (%.0f%%)\n",
1972 dispatch_width, before_size / 16, before_size, after_size,
1973 100.0f * (before_size - after_size) / before_size);
1974
1975 const struct gl_program *prog = fp ? &fp->Base : NULL;
1976
1977 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
1978 ralloc_free(annotation.ann);
1979 }
1980 }
1981
1982 const unsigned *
1983 fs_generator::generate_assembly(exec_list *simd8_instructions,
1984 exec_list *simd16_instructions,
1985 unsigned *assembly_size)
1986 {
1987 assert(simd8_instructions || simd16_instructions);
1988
1989 if (simd8_instructions) {
1990 dispatch_width = 8;
1991 generate_code(simd8_instructions);
1992 }
1993
1994 if (simd16_instructions) {
1995 /* align to 64 byte boundary. */
1996 while (p->next_insn_offset % 64) {
1997 brw_NOP(p);
1998 }
1999
2000 /* Save off the start of this SIMD16 program */
2001 prog_data->prog_offset_16 = p->next_insn_offset;
2002
2003 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
2004
2005 dispatch_width = 16;
2006 generate_code(simd16_instructions);
2007 }
2008
2009 return brw_get_program(p, assembly_size);
2010 }