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[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 fs_generator::fs_generator(struct brw_context *brw,
40 void *mem_ctx,
41 const struct brw_wm_prog_key *key,
42 struct brw_wm_prog_data *prog_data,
43 struct gl_shader_program *prog,
44 struct gl_fragment_program *fp,
45 bool dual_source_output,
46 bool runtime_check_aads_emit,
47 bool debug_flag)
48
49 : brw(brw), key(key), prog_data(prog_data), prog(prog), fp(fp),
50 dual_source_output(dual_source_output),
51 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(debug_flag),
52 mem_ctx(mem_ctx)
53 {
54 ctx = &brw->ctx;
55
56 p = rzalloc(mem_ctx, struct brw_compile);
57 brw_init_compile(brw, p, mem_ctx);
58 }
59
60 fs_generator::~fs_generator()
61 {
62 }
63
64 bool
65 fs_generator::patch_discard_jumps_to_fb_writes()
66 {
67 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
68 return false;
69
70 int scale = brw_jump_scale(brw);
71
72 /* There is a somewhat strange undocumented requirement of using
73 * HALT, according to the simulator. If some channel has HALTed to
74 * a particular UIP, then by the end of the program, every channel
75 * must have HALTed to that UIP. Furthermore, the tracking is a
76 * stack, so you can't do the final halt of a UIP after starting
77 * halting to a new UIP.
78 *
79 * Symptoms of not emitting this instruction on actual hardware
80 * included GPU hangs and sparkly rendering on the piglit discard
81 * tests.
82 */
83 brw_inst *last_halt = gen6_HALT(p);
84 brw_inst_set_uip(brw, last_halt, 1 * scale);
85 brw_inst_set_jip(brw, last_halt, 1 * scale);
86
87 int ip = p->nr_insn;
88
89 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
90 brw_inst *patch = &p->store[patch_ip->ip];
91
92 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
93 /* HALT takes a half-instruction distance from the pre-incremented IP. */
94 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
95 }
96
97 this->discard_halt_patches.make_empty();
98 return true;
99 }
100
101 void
102 fs_generator::fire_fb_write(fs_inst *inst,
103 GLuint base_reg,
104 struct brw_reg implied_header,
105 GLuint nr)
106 {
107 uint32_t msg_control;
108
109 if (brw->gen < 6) {
110 brw_push_insn_state(p);
111 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
112 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
113 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
114 brw_MOV(p,
115 brw_message_reg(base_reg + 1),
116 brw_vec8_grf(1, 0));
117 brw_pop_insn_state(p);
118 }
119
120 if (this->dual_source_output)
121 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
122 else if (dispatch_width == 16)
123 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
124 else
125 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
126
127 uint32_t surf_index =
128 prog_data->binding_table.render_target_start + inst->target;
129
130 brw_fb_WRITE(p,
131 dispatch_width,
132 base_reg,
133 implied_header,
134 msg_control,
135 surf_index,
136 nr,
137 0,
138 inst->eot,
139 inst->header_present);
140
141 brw_mark_surface_used(&prog_data->base, surf_index);
142 }
143
144 void
145 fs_generator::generate_fb_write(fs_inst *inst)
146 {
147 struct brw_reg implied_header;
148
149 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
150 * move, here's g1.
151 */
152 if (inst->header_present) {
153 brw_push_insn_state(p);
154 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
155 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
156 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
157 brw_set_default_flag_reg(p, 0, 0);
158
159 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
160 * present.
161 */
162 if ((fp && fp->UsesKill) || key->alpha_test_func) {
163 struct brw_reg pixel_mask;
164
165 if (brw->gen >= 6)
166 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
167 else
168 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
169
170 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
171 }
172
173 if (brw->gen >= 6) {
174 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
175 brw_MOV(p,
176 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
177 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
178 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
179
180 if (inst->target > 0 && key->replicate_alpha) {
181 /* Set "Source0 Alpha Present to RenderTarget" bit in message
182 * header.
183 */
184 brw_OR(p,
185 vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)),
186 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
187 brw_imm_ud(0x1 << 11));
188 }
189
190 if (inst->target > 0) {
191 /* Set the render target index for choosing BLEND_STATE. */
192 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
193 inst->base_mrf, 2),
194 BRW_REGISTER_TYPE_UD),
195 brw_imm_ud(inst->target));
196 }
197
198 implied_header = brw_null_reg();
199 } else {
200 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
201 }
202
203 brw_pop_insn_state(p);
204 } else {
205 implied_header = brw_null_reg();
206 }
207
208 if (!runtime_check_aads_emit) {
209 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
210 } else {
211 /* This can only happen in gen < 6 */
212 assert(brw->gen < 6);
213
214 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
215
216 /* Check runtime bit to detect if we have to send AA data or not */
217 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
218 brw_AND(p,
219 v1_null_ud,
220 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
221 brw_imm_ud(1<<26));
222 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
223
224 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
225 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
226 {
227 /* Don't send AA data */
228 fire_fb_write(inst, inst->base_mrf+1, implied_header, inst->mlen-1);
229 }
230 brw_land_fwd_jump(p, jmp);
231 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
232 }
233 }
234
235 void
236 fs_generator::generate_blorp_fb_write(fs_inst *inst)
237 {
238 brw_fb_WRITE(p,
239 16 /* dispatch_width */,
240 inst->base_mrf,
241 brw_reg_from_fs_reg(&inst->src[0]),
242 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
243 inst->target,
244 inst->mlen,
245 0,
246 true,
247 inst->header_present);
248 }
249
250 /* Computes the integer pixel x,y values from the origin.
251 *
252 * This is the basis of gl_FragCoord computation, but is also used
253 * pre-gen6 for computing the deltas from v0 for computing
254 * interpolation.
255 */
256 void
257 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
258 {
259 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
260 struct brw_reg src;
261 struct brw_reg deltas;
262
263 if (is_x) {
264 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
265 deltas = brw_imm_v(0x10101010);
266 } else {
267 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
268 deltas = brw_imm_v(0x11001100);
269 }
270
271 if (dispatch_width == 16) {
272 dst = vec16(dst);
273 }
274
275 /* We do this SIMD8 or SIMD16, but since the destination is UW we
276 * don't do compression in the SIMD16 case.
277 */
278 brw_push_insn_state(p);
279 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
280 brw_ADD(p, dst, src, deltas);
281 brw_pop_insn_state(p);
282 }
283
284 void
285 fs_generator::generate_linterp(fs_inst *inst,
286 struct brw_reg dst, struct brw_reg *src)
287 {
288 struct brw_reg delta_x = src[0];
289 struct brw_reg delta_y = src[1];
290 struct brw_reg interp = src[2];
291
292 if (brw->has_pln &&
293 delta_y.nr == delta_x.nr + 1 &&
294 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
295 brw_PLN(p, dst, interp, delta_x);
296 } else {
297 brw_LINE(p, brw_null_reg(), interp, delta_x);
298 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
299 }
300 }
301
302 void
303 fs_generator::generate_math_gen6(fs_inst *inst,
304 struct brw_reg dst,
305 struct brw_reg src0,
306 struct brw_reg src1)
307 {
308 int op = brw_math_function(inst->opcode);
309 bool binop = src1.file == BRW_GENERAL_REGISTER_FILE;
310
311 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
312 gen6_math(p, dst, op, src0, src1);
313
314 if (dispatch_width == 16) {
315 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
316 gen6_math(p, sechalf(dst), op, sechalf(src0),
317 binop ? sechalf(src1) : brw_null_reg());
318 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
319 }
320 }
321
322 void
323 fs_generator::generate_math_gen4(fs_inst *inst,
324 struct brw_reg dst,
325 struct brw_reg src)
326 {
327 int op = brw_math_function(inst->opcode);
328
329 assert(inst->mlen >= 1);
330
331 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
332 gen4_math(p, dst,
333 op,
334 inst->base_mrf, src,
335 BRW_MATH_DATA_VECTOR,
336 BRW_MATH_PRECISION_FULL);
337
338 if (dispatch_width == 16) {
339 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
340 gen4_math(p, sechalf(dst),
341 op,
342 inst->base_mrf + 1, sechalf(src),
343 BRW_MATH_DATA_VECTOR,
344 BRW_MATH_PRECISION_FULL);
345
346 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
347 }
348 }
349
350 void
351 fs_generator::generate_math_g45(fs_inst *inst,
352 struct brw_reg dst,
353 struct brw_reg src)
354 {
355 if (inst->opcode == SHADER_OPCODE_POW ||
356 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
357 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
358 generate_math_gen4(inst, dst, src);
359 return;
360 }
361
362 int op = brw_math_function(inst->opcode);
363
364 assert(inst->mlen >= 1);
365
366 gen4_math(p, dst,
367 op,
368 inst->base_mrf, src,
369 BRW_MATH_DATA_VECTOR,
370 BRW_MATH_PRECISION_FULL);
371 }
372
373 void
374 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
375 struct brw_reg sampler_index)
376 {
377 int msg_type = -1;
378 int rlen = 4;
379 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
380 uint32_t return_format;
381
382 switch (dst.type) {
383 case BRW_REGISTER_TYPE_D:
384 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
385 break;
386 case BRW_REGISTER_TYPE_UD:
387 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
388 break;
389 default:
390 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
391 break;
392 }
393
394 if (dispatch_width == 16 &&
395 !inst->force_uncompressed && !inst->force_sechalf)
396 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
397
398 if (brw->gen >= 5) {
399 switch (inst->opcode) {
400 case SHADER_OPCODE_TEX:
401 if (inst->shadow_compare) {
402 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
403 } else {
404 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
405 }
406 break;
407 case FS_OPCODE_TXB:
408 if (inst->shadow_compare) {
409 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
410 } else {
411 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
412 }
413 break;
414 case SHADER_OPCODE_TXL:
415 if (inst->shadow_compare) {
416 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
417 } else {
418 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
419 }
420 break;
421 case SHADER_OPCODE_TXS:
422 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
423 break;
424 case SHADER_OPCODE_TXD:
425 if (inst->shadow_compare) {
426 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
427 assert(brw->gen >= 8 || brw->is_haswell);
428 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
429 } else {
430 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
431 }
432 break;
433 case SHADER_OPCODE_TXF:
434 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
435 break;
436 case SHADER_OPCODE_TXF_CMS:
437 if (brw->gen >= 7)
438 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
439 else
440 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
441 break;
442 case SHADER_OPCODE_TXF_UMS:
443 assert(brw->gen >= 7);
444 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
445 break;
446 case SHADER_OPCODE_TXF_MCS:
447 assert(brw->gen >= 7);
448 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
449 break;
450 case SHADER_OPCODE_LOD:
451 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
452 break;
453 case SHADER_OPCODE_TG4:
454 if (inst->shadow_compare) {
455 assert(brw->gen >= 7);
456 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
457 } else {
458 assert(brw->gen >= 6);
459 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
460 }
461 break;
462 case SHADER_OPCODE_TG4_OFFSET:
463 assert(brw->gen >= 7);
464 if (inst->shadow_compare) {
465 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
466 } else {
467 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
468 }
469 break;
470 default:
471 unreachable("not reached");
472 }
473 } else {
474 switch (inst->opcode) {
475 case SHADER_OPCODE_TEX:
476 /* Note that G45 and older determines shadow compare and dispatch width
477 * from message length for most messages.
478 */
479 assert(dispatch_width == 8);
480 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
481 if (inst->shadow_compare) {
482 assert(inst->mlen == 6);
483 } else {
484 assert(inst->mlen <= 4);
485 }
486 break;
487 case FS_OPCODE_TXB:
488 if (inst->shadow_compare) {
489 assert(inst->mlen == 6);
490 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
491 } else {
492 assert(inst->mlen == 9);
493 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
494 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
495 }
496 break;
497 case SHADER_OPCODE_TXL:
498 if (inst->shadow_compare) {
499 assert(inst->mlen == 6);
500 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
501 } else {
502 assert(inst->mlen == 9);
503 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
504 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
505 }
506 break;
507 case SHADER_OPCODE_TXD:
508 /* There is no sample_d_c message; comparisons are done manually */
509 assert(inst->mlen == 7 || inst->mlen == 10);
510 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
511 break;
512 case SHADER_OPCODE_TXF:
513 assert(inst->mlen == 9);
514 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
515 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
516 break;
517 case SHADER_OPCODE_TXS:
518 assert(inst->mlen == 3);
519 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
520 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
521 break;
522 default:
523 unreachable("not reached");
524 }
525 }
526 assert(msg_type != -1);
527
528 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
529 rlen = 8;
530 dst = vec16(dst);
531 }
532
533 if (brw->gen >= 7 && inst->header_present && dispatch_width == 16) {
534 /* The send-from-GRF for SIMD16 texturing with a header has an extra
535 * hardware register allocated to it, which we need to skip over (since
536 * our coordinates in the payload are in the even-numbered registers,
537 * and the header comes right before the first one).
538 */
539 assert(src.file == BRW_GENERAL_REGISTER_FILE);
540 src.nr++;
541 }
542
543 assert(sampler_index.file == BRW_IMMEDIATE_VALUE);
544 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
545
546 uint32_t sampler = sampler_index.dw1.ud;
547
548 /* Load the message header if present. If there's a texture offset,
549 * we need to set it up explicitly and load the offset bitfield.
550 * Otherwise, we can use an implied move from g0 to the first message reg.
551 */
552 if (inst->header_present) {
553 if (brw->gen < 6 && !inst->texture_offset) {
554 /* Set up an implied move from g0 to the MRF. */
555 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
556 } else {
557 struct brw_reg header_reg;
558
559 if (brw->gen >= 7) {
560 header_reg = src;
561 } else {
562 assert(inst->base_mrf != -1);
563 header_reg = brw_message_reg(inst->base_mrf);
564 }
565
566 brw_push_insn_state(p);
567 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
568 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
569 /* Explicitly set up the message header by copying g0 to the MRF. */
570 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
571
572 if (inst->texture_offset) {
573 /* Set the offset bits in DWord 2. */
574 brw_MOV(p, get_element_ud(header_reg, 2),
575 brw_imm_ud(inst->texture_offset));
576 }
577
578 if (sampler >= 16) {
579 /* The "Sampler Index" field can only store values between 0 and 15.
580 * However, we can add an offset to the "Sampler State Pointer"
581 * field, effectively selecting a different set of 16 samplers.
582 *
583 * The "Sampler State Pointer" needs to be aligned to a 32-byte
584 * offset, and each sampler state is only 16-bytes, so we can't
585 * exclusively use the offset - we have to use both.
586 */
587 assert(brw->gen >= 8 || brw->is_haswell);
588 const int sampler_state_size = 16; /* 16 bytes */
589 brw_ADD(p,
590 get_element_ud(header_reg, 3),
591 get_element_ud(brw_vec8_grf(0, 0), 3),
592 brw_imm_ud(16 * (sampler / 16) * sampler_state_size));
593 }
594 brw_pop_insn_state(p);
595 }
596 }
597
598 uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
599 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
600 ? prog_data->base.binding_table.gather_texture_start
601 : prog_data->base.binding_table.texture_start) + sampler;
602
603 brw_SAMPLE(p,
604 retype(dst, BRW_REGISTER_TYPE_UW),
605 inst->base_mrf,
606 src,
607 surface_index,
608 sampler % 16,
609 msg_type,
610 rlen,
611 inst->mlen,
612 inst->header_present,
613 simd_mode,
614 return_format);
615
616 brw_mark_surface_used(&prog_data->base, surface_index);
617 }
618
619
620 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
621 * looking like:
622 *
623 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
624 *
625 * Ideally, we want to produce:
626 *
627 * DDX DDY
628 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
629 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
630 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
631 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
632 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
633 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
634 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
635 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
636 *
637 * and add another set of two more subspans if in 16-pixel dispatch mode.
638 *
639 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
640 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
641 * pair. But the ideal approximation may impose a huge performance cost on
642 * sample_d. On at least Haswell, sample_d instruction does some
643 * optimizations if the same LOD is used for all pixels in the subspan.
644 *
645 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
646 * appropriate swizzling.
647 */
648 void
649 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
650 {
651 unsigned vstride, width;
652
653 if (key->high_quality_derivatives) {
654 /* produce accurate derivatives */
655 vstride = BRW_VERTICAL_STRIDE_2;
656 width = BRW_WIDTH_2;
657 }
658 else {
659 /* replicate the derivative at the top-left pixel to other pixels */
660 vstride = BRW_VERTICAL_STRIDE_4;
661 width = BRW_WIDTH_4;
662 }
663
664 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
665 BRW_REGISTER_TYPE_F,
666 vstride,
667 width,
668 BRW_HORIZONTAL_STRIDE_0,
669 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
670 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
671 BRW_REGISTER_TYPE_F,
672 vstride,
673 width,
674 BRW_HORIZONTAL_STRIDE_0,
675 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
676 brw_ADD(p, dst, src0, negate(src1));
677 }
678
679 /* The negate_value boolean is used to negate the derivative computation for
680 * FBOs, since they place the origin at the upper left instead of the lower
681 * left.
682 */
683 void
684 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
685 bool negate_value)
686 {
687 if (key->high_quality_derivatives) {
688 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
689 * Region Restrictions):
690 *
691 * In Align16 access mode, SIMD16 is not allowed for DW operations
692 * and SIMD8 is not allowed for DF operations.
693 *
694 * In this context, "DW operations" means "operations acting on 32-bit
695 * values", so it includes operations on floats.
696 *
697 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
698 * (Instruction Compression -> Rules and Restrictions):
699 *
700 * A compressed instruction must be in Align1 access mode. Align16
701 * mode instructions cannot be compressed.
702 *
703 * Similar text exists in the g45 PRM.
704 *
705 * On these platforms, if we're building a SIMD16 shader, we need to
706 * manually unroll to a pair of SIMD8 instructions.
707 */
708 bool unroll_to_simd8 =
709 (dispatch_width == 16 &&
710 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
711
712 /* produce accurate derivatives */
713 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
714 BRW_REGISTER_TYPE_F,
715 BRW_VERTICAL_STRIDE_4,
716 BRW_WIDTH_4,
717 BRW_HORIZONTAL_STRIDE_1,
718 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
719 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
720 BRW_REGISTER_TYPE_F,
721 BRW_VERTICAL_STRIDE_4,
722 BRW_WIDTH_4,
723 BRW_HORIZONTAL_STRIDE_1,
724 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
725 brw_push_insn_state(p);
726 brw_set_default_access_mode(p, BRW_ALIGN_16);
727 if (unroll_to_simd8)
728 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
729 if (negate_value)
730 brw_ADD(p, dst, src1, negate(src0));
731 else
732 brw_ADD(p, dst, src0, negate(src1));
733 if (unroll_to_simd8) {
734 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
735 src0 = sechalf(src0);
736 src1 = sechalf(src1);
737 dst = sechalf(dst);
738 if (negate_value)
739 brw_ADD(p, dst, src1, negate(src0));
740 else
741 brw_ADD(p, dst, src0, negate(src1));
742 }
743 brw_pop_insn_state(p);
744 } else {
745 /* replicate the derivative at the top-left pixel to other pixels */
746 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
747 BRW_REGISTER_TYPE_F,
748 BRW_VERTICAL_STRIDE_4,
749 BRW_WIDTH_4,
750 BRW_HORIZONTAL_STRIDE_0,
751 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
752 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
753 BRW_REGISTER_TYPE_F,
754 BRW_VERTICAL_STRIDE_4,
755 BRW_WIDTH_4,
756 BRW_HORIZONTAL_STRIDE_0,
757 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
758 if (negate_value)
759 brw_ADD(p, dst, src1, negate(src0));
760 else
761 brw_ADD(p, dst, src0, negate(src1));
762 }
763 }
764
765 void
766 fs_generator::generate_discard_jump(fs_inst *inst)
767 {
768 assert(brw->gen >= 6);
769
770 /* This HALT will be patched up at FB write time to point UIP at the end of
771 * the program, and at brw_uip_jip() JIP will be set to the end of the
772 * current block (or the program).
773 */
774 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
775
776 brw_push_insn_state(p);
777 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
778 gen6_HALT(p);
779 brw_pop_insn_state(p);
780 }
781
782 void
783 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
784 {
785 assert(inst->mlen != 0);
786
787 brw_MOV(p,
788 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
789 retype(src, BRW_REGISTER_TYPE_UD));
790 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
791 dispatch_width / 8, inst->offset);
792 }
793
794 void
795 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
796 {
797 assert(inst->mlen != 0);
798
799 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
800 dispatch_width / 8, inst->offset);
801 }
802
803 void
804 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
805 {
806 gen7_block_read_scratch(p, dst, dispatch_width / 8, inst->offset);
807 }
808
809 void
810 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
811 struct brw_reg dst,
812 struct brw_reg index,
813 struct brw_reg offset)
814 {
815 assert(inst->mlen != 0);
816
817 assert(index.file == BRW_IMMEDIATE_VALUE &&
818 index.type == BRW_REGISTER_TYPE_UD);
819 uint32_t surf_index = index.dw1.ud;
820
821 assert(offset.file == BRW_IMMEDIATE_VALUE &&
822 offset.type == BRW_REGISTER_TYPE_UD);
823 uint32_t read_offset = offset.dw1.ud;
824
825 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
826 read_offset, surf_index);
827
828 brw_mark_surface_used(&prog_data->base, surf_index);
829 }
830
831 void
832 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
833 struct brw_reg dst,
834 struct brw_reg index,
835 struct brw_reg offset)
836 {
837 assert(inst->mlen == 0);
838
839 assert(index.file == BRW_IMMEDIATE_VALUE &&
840 index.type == BRW_REGISTER_TYPE_UD);
841 uint32_t surf_index = index.dw1.ud;
842
843 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
844 /* Reference just the dword we need, to avoid angering validate_reg(). */
845 offset = brw_vec1_grf(offset.nr, 0);
846
847 brw_push_insn_state(p);
848 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
849 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
850 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
851 brw_pop_insn_state(p);
852
853 /* We use the SIMD4x2 mode because we want to end up with 4 components in
854 * the destination loaded consecutively from the same offset (which appears
855 * in the first component, and the rest are ignored).
856 */
857 dst.width = BRW_WIDTH_4;
858 brw_set_dest(p, send, dst);
859 brw_set_src0(p, send, offset);
860 brw_set_sampler_message(p, send,
861 surf_index,
862 0, /* LD message ignores sampler unit */
863 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
864 1, /* rlen */
865 1, /* mlen */
866 false, /* no header */
867 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
868 0);
869
870 brw_mark_surface_used(&prog_data->base, surf_index);
871 }
872
873 void
874 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
875 struct brw_reg dst,
876 struct brw_reg index,
877 struct brw_reg offset)
878 {
879 assert(brw->gen < 7); /* Should use the gen7 variant. */
880 assert(inst->header_present);
881 assert(inst->mlen);
882
883 assert(index.file == BRW_IMMEDIATE_VALUE &&
884 index.type == BRW_REGISTER_TYPE_UD);
885 uint32_t surf_index = index.dw1.ud;
886
887 uint32_t simd_mode, rlen, msg_type;
888 if (dispatch_width == 16) {
889 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
890 rlen = 8;
891 } else {
892 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
893 rlen = 4;
894 }
895
896 if (brw->gen >= 5)
897 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
898 else {
899 /* We always use the SIMD16 message so that we only have to load U, and
900 * not V or R.
901 */
902 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
903 assert(inst->mlen == 3);
904 assert(inst->regs_written == 8);
905 rlen = 8;
906 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
907 }
908
909 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
910 BRW_REGISTER_TYPE_D);
911 brw_MOV(p, offset_mrf, offset);
912
913 struct brw_reg header = brw_vec8_grf(0, 0);
914 gen6_resolve_implied_move(p, &header, inst->base_mrf);
915
916 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
917 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
918 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
919 brw_set_src0(p, send, header);
920 if (brw->gen < 6)
921 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
922
923 /* Our surface is set up as floats, regardless of what actual data is
924 * stored in it.
925 */
926 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
927 brw_set_sampler_message(p, send,
928 surf_index,
929 0, /* sampler (unused) */
930 msg_type,
931 rlen,
932 inst->mlen,
933 inst->header_present,
934 simd_mode,
935 return_format);
936
937 brw_mark_surface_used(&prog_data->base, surf_index);
938 }
939
940 void
941 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
942 struct brw_reg dst,
943 struct brw_reg index,
944 struct brw_reg offset)
945 {
946 assert(brw->gen >= 7);
947 /* Varying-offset pull constant loads are treated as a normal expression on
948 * gen7, so the fact that it's a send message is hidden at the IR level.
949 */
950 assert(!inst->header_present);
951 assert(!inst->mlen);
952
953 assert(index.file == BRW_IMMEDIATE_VALUE &&
954 index.type == BRW_REGISTER_TYPE_UD);
955 uint32_t surf_index = index.dw1.ud;
956
957 uint32_t simd_mode, rlen, mlen;
958 if (dispatch_width == 16) {
959 mlen = 2;
960 rlen = 8;
961 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
962 } else {
963 mlen = 1;
964 rlen = 4;
965 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
966 }
967
968 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
969 brw_set_dest(p, send, dst);
970 brw_set_src0(p, send, offset);
971 brw_set_sampler_message(p, send,
972 surf_index,
973 0, /* LD message ignores sampler unit */
974 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
975 rlen,
976 mlen,
977 false, /* no header */
978 simd_mode,
979 0);
980
981 brw_mark_surface_used(&prog_data->base, surf_index);
982 }
983
984 /**
985 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
986 * into the flags register (f0.0).
987 *
988 * Used only on Gen6 and above.
989 */
990 void
991 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
992 {
993 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
994 struct brw_reg dispatch_mask;
995
996 if (brw->gen >= 6)
997 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
998 else
999 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1000
1001 brw_push_insn_state(p);
1002 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1003 brw_MOV(p, flags, dispatch_mask);
1004 brw_pop_insn_state(p);
1005 }
1006
1007 void
1008 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1009 struct brw_reg dst,
1010 struct brw_reg src,
1011 struct brw_reg msg_data,
1012 unsigned msg_type)
1013 {
1014 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1015 msg_data.type == BRW_REGISTER_TYPE_UD);
1016
1017 brw_pixel_interpolator_query(p,
1018 retype(dst, BRW_REGISTER_TYPE_UW),
1019 src,
1020 inst->pi_noperspective,
1021 msg_type,
1022 msg_data.dw1.ud,
1023 inst->mlen,
1024 inst->regs_written);
1025 }
1026
1027
1028 static uint32_t brw_file_from_reg(fs_reg *reg)
1029 {
1030 switch (reg->file) {
1031 case GRF:
1032 return BRW_GENERAL_REGISTER_FILE;
1033 case MRF:
1034 return BRW_MESSAGE_REGISTER_FILE;
1035 case IMM:
1036 return BRW_IMMEDIATE_VALUE;
1037 default:
1038 unreachable("not reached");
1039 }
1040 }
1041
1042 struct brw_reg
1043 brw_reg_from_fs_reg(fs_reg *reg)
1044 {
1045 struct brw_reg brw_reg;
1046
1047 switch (reg->file) {
1048 case GRF:
1049 case MRF:
1050 if (reg->stride == 0) {
1051 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
1052 } else {
1053 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1054 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
1055 }
1056
1057 brw_reg = retype(brw_reg, reg->type);
1058 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
1059 break;
1060 case IMM:
1061 switch (reg->type) {
1062 case BRW_REGISTER_TYPE_F:
1063 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
1064 break;
1065 case BRW_REGISTER_TYPE_D:
1066 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
1067 break;
1068 case BRW_REGISTER_TYPE_UD:
1069 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
1070 break;
1071 default:
1072 unreachable("not reached");
1073 }
1074 break;
1075 case HW_REG:
1076 assert(reg->type == reg->fixed_hw_reg.type);
1077 brw_reg = reg->fixed_hw_reg;
1078 break;
1079 case BAD_FILE:
1080 /* Probably unused. */
1081 brw_reg = brw_null_reg();
1082 break;
1083 case UNIFORM:
1084 unreachable("not reached");
1085 default:
1086 unreachable("not reached");
1087 }
1088 if (reg->abs)
1089 brw_reg = brw_abs(brw_reg);
1090 if (reg->negate)
1091 brw_reg = negate(brw_reg);
1092
1093 return brw_reg;
1094 }
1095
1096 /**
1097 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1098 * sampler LD messages.
1099 *
1100 * We don't want to bake it into the send message's code generation because
1101 * that means we don't get a chance to schedule the instructions.
1102 */
1103 void
1104 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1105 struct brw_reg dst,
1106 struct brw_reg value)
1107 {
1108 assert(value.file == BRW_IMMEDIATE_VALUE);
1109
1110 brw_push_insn_state(p);
1111 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1112 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1113 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1114 brw_pop_insn_state(p);
1115 }
1116
1117 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1118 * (when mask is passed as a uniform) of register mask before moving it
1119 * to register dst.
1120 */
1121 void
1122 fs_generator::generate_set_omask(fs_inst *inst,
1123 struct brw_reg dst,
1124 struct brw_reg mask)
1125 {
1126 bool stride_8_8_1 =
1127 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1128 mask.width == BRW_WIDTH_8 &&
1129 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1130
1131 bool stride_0_1_0 =
1132 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1133 mask.width == BRW_WIDTH_1 &&
1134 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1135
1136 assert(stride_8_8_1 || stride_0_1_0);
1137 assert(dst.type == BRW_REGISTER_TYPE_UW);
1138
1139 if (dispatch_width == 16)
1140 dst = vec16(dst);
1141 brw_push_insn_state(p);
1142 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1143 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1144
1145 if (stride_8_8_1) {
1146 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1147 } else if (stride_0_1_0) {
1148 brw_MOV(p, dst, retype(mask, dst.type));
1149 }
1150 brw_pop_insn_state(p);
1151 }
1152
1153 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1154 * the ADD instruction.
1155 */
1156 void
1157 fs_generator::generate_set_sample_id(fs_inst *inst,
1158 struct brw_reg dst,
1159 struct brw_reg src0,
1160 struct brw_reg src1)
1161 {
1162 assert(dst.type == BRW_REGISTER_TYPE_D ||
1163 dst.type == BRW_REGISTER_TYPE_UD);
1164 assert(src0.type == BRW_REGISTER_TYPE_D ||
1165 src0.type == BRW_REGISTER_TYPE_UD);
1166
1167 brw_push_insn_state(p);
1168 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1169 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1170 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1171 brw_ADD(p, dst, src0, reg);
1172 if (dispatch_width == 16)
1173 brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
1174 brw_pop_insn_state(p);
1175 }
1176
1177 /**
1178 * Change the register's data type from UD to W, doubling the strides in order
1179 * to compensate for halving the data type width.
1180 */
1181 static struct brw_reg
1182 ud_reg_to_w(struct brw_reg r)
1183 {
1184 assert(r.type == BRW_REGISTER_TYPE_UD);
1185 r.type = BRW_REGISTER_TYPE_W;
1186
1187 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1188 * doubles the real stride.
1189 */
1190 if (r.hstride != 0)
1191 ++r.hstride;
1192 if (r.vstride != 0)
1193 ++r.vstride;
1194
1195 return r;
1196 }
1197
1198 void
1199 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1200 struct brw_reg dst,
1201 struct brw_reg x,
1202 struct brw_reg y)
1203 {
1204 assert(brw->gen >= 7);
1205 assert(dst.type == BRW_REGISTER_TYPE_UD);
1206 assert(x.type == BRW_REGISTER_TYPE_F);
1207 assert(y.type == BRW_REGISTER_TYPE_F);
1208
1209 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1210 *
1211 * Because this instruction does not have a 16-bit floating-point type,
1212 * the destination data type must be Word (W).
1213 *
1214 * The destination must be DWord-aligned and specify a horizontal stride
1215 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1216 * each destination channel and the upper word is not modified.
1217 */
1218 struct brw_reg dst_w = ud_reg_to_w(dst);
1219
1220 /* Give each 32-bit channel of dst the form below , where "." means
1221 * unchanged.
1222 * 0x....hhhh
1223 */
1224 brw_F32TO16(p, dst_w, y);
1225
1226 /* Now the form:
1227 * 0xhhhh0000
1228 */
1229 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1230
1231 /* And, finally the form of packHalf2x16's output:
1232 * 0xhhhhllll
1233 */
1234 brw_F32TO16(p, dst_w, x);
1235 }
1236
1237 void
1238 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1239 struct brw_reg dst,
1240 struct brw_reg src)
1241 {
1242 assert(brw->gen >= 7);
1243 assert(dst.type == BRW_REGISTER_TYPE_F);
1244 assert(src.type == BRW_REGISTER_TYPE_UD);
1245
1246 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1247 *
1248 * Because this instruction does not have a 16-bit floating-point type,
1249 * the source data type must be Word (W). The destination type must be
1250 * F (Float).
1251 */
1252 struct brw_reg src_w = ud_reg_to_w(src);
1253
1254 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1255 * For the Y case, we wish to access only the upper word; therefore
1256 * a 16-bit subregister offset is needed.
1257 */
1258 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1259 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1260 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1261 src_w.subnr += 2;
1262
1263 brw_F16TO32(p, dst, src_w);
1264 }
1265
1266 void
1267 fs_generator::generate_shader_time_add(fs_inst *inst,
1268 struct brw_reg payload,
1269 struct brw_reg offset,
1270 struct brw_reg value)
1271 {
1272 assert(brw->gen >= 7);
1273 brw_push_insn_state(p);
1274 brw_set_default_mask_control(p, true);
1275
1276 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1277 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1278 offset.type);
1279 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1280 value.type);
1281
1282 assert(offset.file == BRW_IMMEDIATE_VALUE);
1283 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1284 value.width = BRW_WIDTH_1;
1285 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1286 value.vstride = BRW_VERTICAL_STRIDE_0;
1287 } else {
1288 assert(value.file == BRW_IMMEDIATE_VALUE);
1289 }
1290
1291 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1292 * case, and we don't really care about squeezing every bit of performance
1293 * out of this path, so we just emit the MOVs from here.
1294 */
1295 brw_MOV(p, payload_offset, offset);
1296 brw_MOV(p, payload_value, value);
1297 brw_shader_time_add(p, payload,
1298 prog_data->base.binding_table.shader_time_start);
1299 brw_pop_insn_state(p);
1300
1301 brw_mark_surface_used(&prog_data->base,
1302 prog_data->base.binding_table.shader_time_start);
1303 }
1304
1305 void
1306 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1307 struct brw_reg atomic_op,
1308 struct brw_reg surf_index)
1309 {
1310 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1311 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1312 surf_index.file == BRW_IMMEDIATE_VALUE &&
1313 surf_index.type == BRW_REGISTER_TYPE_UD);
1314
1315 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1316 atomic_op.dw1.ud, surf_index.dw1.ud,
1317 inst->mlen, dispatch_width / 8);
1318
1319 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1320 }
1321
1322 void
1323 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1324 struct brw_reg surf_index)
1325 {
1326 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1327 surf_index.type == BRW_REGISTER_TYPE_UD);
1328
1329 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1330 surf_index.dw1.ud,
1331 inst->mlen, dispatch_width / 8);
1332
1333 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1334 }
1335
1336 void
1337 fs_generator::generate_code(exec_list *instructions)
1338 {
1339 int start_offset = p->next_insn_offset;
1340
1341 struct annotation_info annotation;
1342 memset(&annotation, 0, sizeof(annotation));
1343
1344 cfg_t *cfg = NULL;
1345 if (unlikely(debug_flag))
1346 cfg = new(mem_ctx) cfg_t(instructions);
1347
1348 foreach_in_list(fs_inst, inst, instructions) {
1349 struct brw_reg src[3], dst;
1350 unsigned int last_insn_offset = p->next_insn_offset;
1351
1352 if (unlikely(debug_flag))
1353 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1354
1355 for (unsigned int i = 0; i < inst->sources; i++) {
1356 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1357
1358 /* The accumulator result appears to get used for the
1359 * conditional modifier generation. When negating a UD
1360 * value, there is a 33rd bit generated for the sign in the
1361 * accumulator value, so now you can't check, for example,
1362 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1363 */
1364 assert(!inst->conditional_mod ||
1365 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1366 !inst->src[i].negate);
1367 }
1368 dst = brw_reg_from_fs_reg(&inst->dst);
1369
1370 brw_set_default_predicate_control(p, inst->predicate);
1371 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1372 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1373 brw_set_default_saturate(p, inst->saturate);
1374 brw_set_default_mask_control(p, inst->force_writemask_all);
1375 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1376
1377 if (inst->force_uncompressed || dispatch_width == 8) {
1378 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1379 } else if (inst->force_sechalf) {
1380 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1381 } else {
1382 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1383 }
1384
1385 switch (inst->opcode) {
1386 case BRW_OPCODE_MOV:
1387 brw_MOV(p, dst, src[0]);
1388 break;
1389 case BRW_OPCODE_ADD:
1390 brw_ADD(p, dst, src[0], src[1]);
1391 break;
1392 case BRW_OPCODE_MUL:
1393 brw_MUL(p, dst, src[0], src[1]);
1394 break;
1395 case BRW_OPCODE_AVG:
1396 brw_AVG(p, dst, src[0], src[1]);
1397 break;
1398 case BRW_OPCODE_MACH:
1399 brw_MACH(p, dst, src[0], src[1]);
1400 break;
1401
1402 case BRW_OPCODE_MAD:
1403 assert(brw->gen >= 6);
1404 brw_set_default_access_mode(p, BRW_ALIGN_16);
1405 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1406 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1407 brw_MAD(p, dst, src[0], src[1], src[2]);
1408 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1409 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1410 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1411 } else {
1412 brw_MAD(p, dst, src[0], src[1], src[2]);
1413 }
1414 brw_set_default_access_mode(p, BRW_ALIGN_1);
1415 break;
1416
1417 case BRW_OPCODE_LRP:
1418 assert(brw->gen >= 6);
1419 brw_set_default_access_mode(p, BRW_ALIGN_16);
1420 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1421 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1422 brw_LRP(p, dst, src[0], src[1], src[2]);
1423 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1424 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1425 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1426 } else {
1427 brw_LRP(p, dst, src[0], src[1], src[2]);
1428 }
1429 brw_set_default_access_mode(p, BRW_ALIGN_1);
1430 break;
1431
1432 case BRW_OPCODE_FRC:
1433 brw_FRC(p, dst, src[0]);
1434 break;
1435 case BRW_OPCODE_RNDD:
1436 brw_RNDD(p, dst, src[0]);
1437 break;
1438 case BRW_OPCODE_RNDE:
1439 brw_RNDE(p, dst, src[0]);
1440 break;
1441 case BRW_OPCODE_RNDZ:
1442 brw_RNDZ(p, dst, src[0]);
1443 break;
1444
1445 case BRW_OPCODE_AND:
1446 brw_AND(p, dst, src[0], src[1]);
1447 break;
1448 case BRW_OPCODE_OR:
1449 brw_OR(p, dst, src[0], src[1]);
1450 break;
1451 case BRW_OPCODE_XOR:
1452 brw_XOR(p, dst, src[0], src[1]);
1453 break;
1454 case BRW_OPCODE_NOT:
1455 brw_NOT(p, dst, src[0]);
1456 break;
1457 case BRW_OPCODE_ASR:
1458 brw_ASR(p, dst, src[0], src[1]);
1459 break;
1460 case BRW_OPCODE_SHR:
1461 brw_SHR(p, dst, src[0], src[1]);
1462 break;
1463 case BRW_OPCODE_SHL:
1464 brw_SHL(p, dst, src[0], src[1]);
1465 break;
1466 case BRW_OPCODE_F32TO16:
1467 assert(brw->gen >= 7);
1468 brw_F32TO16(p, dst, src[0]);
1469 break;
1470 case BRW_OPCODE_F16TO32:
1471 assert(brw->gen >= 7);
1472 brw_F16TO32(p, dst, src[0]);
1473 break;
1474 case BRW_OPCODE_CMP:
1475 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1476 break;
1477 case BRW_OPCODE_SEL:
1478 brw_SEL(p, dst, src[0], src[1]);
1479 break;
1480 case BRW_OPCODE_BFREV:
1481 assert(brw->gen >= 7);
1482 /* BFREV only supports UD type for src and dst. */
1483 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1484 retype(src[0], BRW_REGISTER_TYPE_UD));
1485 break;
1486 case BRW_OPCODE_FBH:
1487 assert(brw->gen >= 7);
1488 /* FBH only supports UD type for dst. */
1489 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1490 break;
1491 case BRW_OPCODE_FBL:
1492 assert(brw->gen >= 7);
1493 /* FBL only supports UD type for dst. */
1494 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1495 break;
1496 case BRW_OPCODE_CBIT:
1497 assert(brw->gen >= 7);
1498 /* CBIT only supports UD type for dst. */
1499 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1500 break;
1501 case BRW_OPCODE_ADDC:
1502 assert(brw->gen >= 7);
1503 brw_ADDC(p, dst, src[0], src[1]);
1504 break;
1505 case BRW_OPCODE_SUBB:
1506 assert(brw->gen >= 7);
1507 brw_SUBB(p, dst, src[0], src[1]);
1508 break;
1509 case BRW_OPCODE_MAC:
1510 brw_MAC(p, dst, src[0], src[1]);
1511 break;
1512
1513 case BRW_OPCODE_BFE:
1514 assert(brw->gen >= 7);
1515 brw_set_default_access_mode(p, BRW_ALIGN_16);
1516 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1517 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1518 brw_BFE(p, dst, src[0], src[1], src[2]);
1519 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1520 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1521 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1522 } else {
1523 brw_BFE(p, dst, src[0], src[1], src[2]);
1524 }
1525 brw_set_default_access_mode(p, BRW_ALIGN_1);
1526 break;
1527
1528 case BRW_OPCODE_BFI1:
1529 assert(brw->gen >= 7);
1530 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1531 * should
1532 *
1533 * "Force BFI instructions to be executed always in SIMD8."
1534 */
1535 if (dispatch_width == 16 && brw->is_haswell) {
1536 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1537 brw_BFI1(p, dst, src[0], src[1]);
1538 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1539 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1540 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1541 } else {
1542 brw_BFI1(p, dst, src[0], src[1]);
1543 }
1544 break;
1545 case BRW_OPCODE_BFI2:
1546 assert(brw->gen >= 7);
1547 brw_set_default_access_mode(p, BRW_ALIGN_16);
1548 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1549 * should
1550 *
1551 * "Force BFI instructions to be executed always in SIMD8."
1552 *
1553 * Otherwise we would be able to emit compressed instructions like we
1554 * do for the other three-source instructions.
1555 */
1556 if (dispatch_width == 16) {
1557 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1558 brw_BFI2(p, dst, src[0], src[1], src[2]);
1559 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1560 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1561 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1562 } else {
1563 brw_BFI2(p, dst, src[0], src[1], src[2]);
1564 }
1565 brw_set_default_access_mode(p, BRW_ALIGN_1);
1566 break;
1567
1568 case BRW_OPCODE_IF:
1569 if (inst->src[0].file != BAD_FILE) {
1570 /* The instruction has an embedded compare (only allowed on gen6) */
1571 assert(brw->gen == 6);
1572 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1573 } else {
1574 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1575 }
1576 break;
1577
1578 case BRW_OPCODE_ELSE:
1579 brw_ELSE(p);
1580 break;
1581 case BRW_OPCODE_ENDIF:
1582 brw_ENDIF(p);
1583 break;
1584
1585 case BRW_OPCODE_DO:
1586 brw_DO(p, BRW_EXECUTE_8);
1587 break;
1588
1589 case BRW_OPCODE_BREAK:
1590 brw_BREAK(p);
1591 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1592 break;
1593 case BRW_OPCODE_CONTINUE:
1594 brw_CONT(p);
1595 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1596 break;
1597
1598 case BRW_OPCODE_WHILE:
1599 brw_WHILE(p);
1600 break;
1601
1602 case SHADER_OPCODE_RCP:
1603 case SHADER_OPCODE_RSQ:
1604 case SHADER_OPCODE_SQRT:
1605 case SHADER_OPCODE_EXP2:
1606 case SHADER_OPCODE_LOG2:
1607 case SHADER_OPCODE_SIN:
1608 case SHADER_OPCODE_COS:
1609 assert(brw->gen < 6 || inst->mlen == 0);
1610 if (brw->gen >= 7) {
1611 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1612 brw_null_reg());
1613 } else if (brw->gen == 6) {
1614 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1615 } else if (brw->gen == 5 || brw->is_g4x) {
1616 generate_math_g45(inst, dst, src[0]);
1617 } else {
1618 generate_math_gen4(inst, dst, src[0]);
1619 }
1620 break;
1621 case SHADER_OPCODE_INT_QUOTIENT:
1622 case SHADER_OPCODE_INT_REMAINDER:
1623 case SHADER_OPCODE_POW:
1624 assert(brw->gen < 6 || inst->mlen == 0);
1625 if (brw->gen >= 7) {
1626 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1627 } else if (brw->gen == 6) {
1628 generate_math_gen6(inst, dst, src[0], src[1]);
1629 } else {
1630 generate_math_gen4(inst, dst, src[0]);
1631 }
1632 break;
1633 case FS_OPCODE_PIXEL_X:
1634 generate_pixel_xy(dst, true);
1635 break;
1636 case FS_OPCODE_PIXEL_Y:
1637 generate_pixel_xy(dst, false);
1638 break;
1639 case FS_OPCODE_CINTERP:
1640 brw_MOV(p, dst, src[0]);
1641 break;
1642 case FS_OPCODE_LINTERP:
1643 generate_linterp(inst, dst, src);
1644 break;
1645 case SHADER_OPCODE_TEX:
1646 case FS_OPCODE_TXB:
1647 case SHADER_OPCODE_TXD:
1648 case SHADER_OPCODE_TXF:
1649 case SHADER_OPCODE_TXF_CMS:
1650 case SHADER_OPCODE_TXF_UMS:
1651 case SHADER_OPCODE_TXF_MCS:
1652 case SHADER_OPCODE_TXL:
1653 case SHADER_OPCODE_TXS:
1654 case SHADER_OPCODE_LOD:
1655 case SHADER_OPCODE_TG4:
1656 case SHADER_OPCODE_TG4_OFFSET:
1657 generate_tex(inst, dst, src[0], src[1]);
1658 break;
1659 case FS_OPCODE_DDX:
1660 generate_ddx(inst, dst, src[0]);
1661 break;
1662 case FS_OPCODE_DDY:
1663 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1664 * guarantee that key->render_to_fbo is set).
1665 */
1666 assert(fp->UsesDFdy);
1667 generate_ddy(inst, dst, src[0], key->render_to_fbo);
1668 break;
1669
1670 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1671 generate_scratch_write(inst, src[0]);
1672 break;
1673
1674 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1675 generate_scratch_read(inst, dst);
1676 break;
1677
1678 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1679 generate_scratch_read_gen7(inst, dst);
1680 break;
1681
1682 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1683 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1684 break;
1685
1686 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1687 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1688 break;
1689
1690 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1691 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1692 break;
1693
1694 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1695 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1696 break;
1697
1698 case FS_OPCODE_FB_WRITE:
1699 generate_fb_write(inst);
1700 break;
1701
1702 case FS_OPCODE_BLORP_FB_WRITE:
1703 generate_blorp_fb_write(inst);
1704 break;
1705
1706 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1707 generate_mov_dispatch_to_flags(inst);
1708 break;
1709
1710 case FS_OPCODE_DISCARD_JUMP:
1711 generate_discard_jump(inst);
1712 break;
1713
1714 case SHADER_OPCODE_SHADER_TIME_ADD:
1715 generate_shader_time_add(inst, src[0], src[1], src[2]);
1716 break;
1717
1718 case SHADER_OPCODE_UNTYPED_ATOMIC:
1719 generate_untyped_atomic(inst, dst, src[0], src[1]);
1720 break;
1721
1722 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1723 generate_untyped_surface_read(inst, dst, src[0]);
1724 break;
1725
1726 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1727 generate_set_simd4x2_offset(inst, dst, src[0]);
1728 break;
1729
1730 case FS_OPCODE_SET_OMASK:
1731 generate_set_omask(inst, dst, src[0]);
1732 break;
1733
1734 case FS_OPCODE_SET_SAMPLE_ID:
1735 generate_set_sample_id(inst, dst, src[0], src[1]);
1736 break;
1737
1738 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1739 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1740 break;
1741
1742 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1743 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1744 generate_unpack_half_2x16_split(inst, dst, src[0]);
1745 break;
1746
1747 case FS_OPCODE_PLACEHOLDER_HALT:
1748 /* This is the place where the final HALT needs to be inserted if
1749 * we've emitted any discards. If not, this will emit no code.
1750 */
1751 if (!patch_discard_jumps_to_fb_writes()) {
1752 if (unlikely(debug_flag)) {
1753 annotation.ann_count--;
1754 }
1755 }
1756 break;
1757
1758 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
1759 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1760 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
1761 break;
1762
1763 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
1764 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1765 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
1766 break;
1767
1768 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
1769 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1770 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
1771 break;
1772
1773 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
1774 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1775 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
1776 break;
1777
1778 default:
1779 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1780 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1781 opcode_descs[inst->opcode].name);
1782 } else {
1783 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1784 }
1785 abort();
1786
1787 case SHADER_OPCODE_LOAD_PAYLOAD:
1788 unreachable("Should be lowered by lower_load_payload()");
1789 }
1790
1791 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1792 assert(p->next_insn_offset == last_insn_offset + 16 ||
1793 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1794 "emitting more than 1 instruction");
1795
1796 brw_inst *last = &p->store[last_insn_offset / 16];
1797
1798 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
1799 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
1800 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
1801 }
1802 }
1803
1804 brw_set_uip_jip(p);
1805 annotation_finalize(&annotation, p->next_insn_offset);
1806
1807 int before_size = p->next_insn_offset - start_offset;
1808 brw_compact_instructions(p, start_offset, annotation.ann_count,
1809 annotation.ann);
1810 int after_size = p->next_insn_offset - start_offset;
1811
1812 if (unlikely(debug_flag)) {
1813 if (prog) {
1814 fprintf(stderr,
1815 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
1816 prog->Label ? prog->Label : "unnamed",
1817 prog->Name, dispatch_width);
1818 } else if (fp) {
1819 fprintf(stderr,
1820 "Native code for fragment program %d (SIMD%d dispatch):\n",
1821 fp->Base.Id, dispatch_width);
1822 } else {
1823 fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
1824 dispatch_width);
1825 }
1826 fprintf(stderr, "SIMD%d shader: %d instructions. Compacted %d to %d"
1827 " bytes (%.0f%%)\n",
1828 dispatch_width, before_size / 16, before_size, after_size,
1829 100.0f * (before_size - after_size) / before_size);
1830
1831 const struct gl_program *prog = fp ? &fp->Base : NULL;
1832
1833 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
1834 ralloc_free(annotation.ann);
1835 }
1836 }
1837
1838 const unsigned *
1839 fs_generator::generate_assembly(exec_list *simd8_instructions,
1840 exec_list *simd16_instructions,
1841 unsigned *assembly_size)
1842 {
1843 assert(simd8_instructions || simd16_instructions);
1844
1845 if (simd8_instructions) {
1846 dispatch_width = 8;
1847 generate_code(simd8_instructions);
1848 }
1849
1850 if (simd16_instructions) {
1851 /* align to 64 byte boundary. */
1852 while (p->next_insn_offset % 64) {
1853 brw_NOP(p);
1854 }
1855
1856 /* Save off the start of this SIMD16 program */
1857 prog_data->prog_offset_16 = p->next_insn_offset;
1858
1859 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1860
1861 dispatch_width = 16;
1862 generate_code(simd16_instructions);
1863 }
1864
1865 return brw_get_program(p, assembly_size);
1866 }