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i965/fs: Add support for specifying register horizontal strides.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 fs_generator::fs_generator(struct brw_context *brw,
40 struct brw_wm_compile *c,
41 struct gl_shader_program *prog,
42 struct gl_fragment_program *fp,
43 bool dual_source_output)
44
45 : brw(brw), c(c), prog(prog), fp(fp), dual_source_output(dual_source_output)
46 {
47 ctx = &brw->ctx;
48
49 mem_ctx = c;
50
51 p = rzalloc(mem_ctx, struct brw_compile);
52 brw_init_compile(brw, p, mem_ctx);
53 }
54
55 fs_generator::~fs_generator()
56 {
57 }
58
59 void
60 fs_generator::mark_surface_used(unsigned surf_index)
61 {
62 assert(surf_index < BRW_MAX_SURFACES);
63
64 c->prog_data.base.binding_table.size_bytes =
65 MAX2(c->prog_data.base.binding_table.size_bytes, (surf_index + 1) * 4);
66 }
67
68 void
69 fs_generator::patch_discard_jumps_to_fb_writes()
70 {
71 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
72 return;
73
74 /* There is a somewhat strange undocumented requirement of using
75 * HALT, according to the simulator. If some channel has HALTed to
76 * a particular UIP, then by the end of the program, every channel
77 * must have HALTed to that UIP. Furthermore, the tracking is a
78 * stack, so you can't do the final halt of a UIP after starting
79 * halting to a new UIP.
80 *
81 * Symptoms of not emitting this instruction on actual hardware
82 * included GPU hangs and sparkly rendering on the piglit discard
83 * tests.
84 */
85 struct brw_instruction *last_halt = gen6_HALT(p);
86 last_halt->bits3.break_cont.uip = 2;
87 last_halt->bits3.break_cont.jip = 2;
88
89 int ip = p->nr_insn;
90
91 foreach_list(node, &this->discard_halt_patches) {
92 ip_record *patch_ip = (ip_record *)node;
93 struct brw_instruction *patch = &p->store[patch_ip->ip];
94
95 assert(patch->header.opcode == BRW_OPCODE_HALT);
96 /* HALT takes a half-instruction distance from the pre-incremented IP. */
97 patch->bits3.break_cont.uip = (ip - patch_ip->ip) * 2;
98 }
99
100 this->discard_halt_patches.make_empty();
101 }
102
103 void
104 fs_generator::generate_fb_write(fs_inst *inst)
105 {
106 bool eot = inst->eot;
107 struct brw_reg implied_header;
108 uint32_t msg_control;
109
110 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
111 * move, here's g1.
112 */
113 brw_push_insn_state(p);
114 brw_set_mask_control(p, BRW_MASK_DISABLE);
115 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
116
117 if ((fp && fp->UsesKill) || c->key.alpha_test_func) {
118 struct brw_reg pixel_mask;
119
120 if (brw->gen >= 6)
121 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
122 else
123 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
124
125 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
126 }
127
128 if (inst->header_present) {
129 if (brw->gen >= 6) {
130 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
131 brw_MOV(p,
132 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
133 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
134 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
135
136 if (inst->target > 0 && c->key.replicate_alpha) {
137 /* Set "Source0 Alpha Present to RenderTarget" bit in message
138 * header.
139 */
140 brw_OR(p,
141 vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)),
142 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
143 brw_imm_ud(0x1 << 11));
144 }
145
146 if (inst->target > 0) {
147 /* Set the render target index for choosing BLEND_STATE. */
148 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
149 inst->base_mrf, 2),
150 BRW_REGISTER_TYPE_UD),
151 brw_imm_ud(inst->target));
152 }
153
154 implied_header = brw_null_reg();
155 } else {
156 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
157
158 brw_MOV(p,
159 brw_message_reg(inst->base_mrf + 1),
160 brw_vec8_grf(1, 0));
161 }
162 } else {
163 implied_header = brw_null_reg();
164 }
165
166 if (this->dual_source_output)
167 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
168 else if (dispatch_width == 16)
169 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
170 else
171 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
172
173 brw_pop_insn_state(p);
174
175 uint32_t surf_index =
176 c->prog_data.binding_table.render_target_start + inst->target;
177 brw_fb_WRITE(p,
178 dispatch_width,
179 inst->base_mrf,
180 implied_header,
181 msg_control,
182 surf_index,
183 inst->mlen,
184 0,
185 eot,
186 inst->header_present);
187
188 mark_surface_used(surf_index);
189 }
190
191 void
192 fs_generator::generate_blorp_fb_write(fs_inst *inst)
193 {
194 brw_fb_WRITE(p,
195 16 /* dispatch_width */,
196 inst->base_mrf,
197 brw_reg_from_fs_reg(&inst->src[0]),
198 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
199 inst->target,
200 inst->mlen,
201 0,
202 true,
203 inst->header_present);
204 }
205
206 /* Computes the integer pixel x,y values from the origin.
207 *
208 * This is the basis of gl_FragCoord computation, but is also used
209 * pre-gen6 for computing the deltas from v0 for computing
210 * interpolation.
211 */
212 void
213 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
214 {
215 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
216 struct brw_reg src;
217 struct brw_reg deltas;
218
219 if (is_x) {
220 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
221 deltas = brw_imm_v(0x10101010);
222 } else {
223 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
224 deltas = brw_imm_v(0x11001100);
225 }
226
227 if (dispatch_width == 16) {
228 dst = vec16(dst);
229 }
230
231 /* We do this SIMD8 or SIMD16, but since the destination is UW we
232 * don't do compression in the SIMD16 case.
233 */
234 brw_push_insn_state(p);
235 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
236 brw_ADD(p, dst, src, deltas);
237 brw_pop_insn_state(p);
238 }
239
240 void
241 fs_generator::generate_linterp(fs_inst *inst,
242 struct brw_reg dst, struct brw_reg *src)
243 {
244 struct brw_reg delta_x = src[0];
245 struct brw_reg delta_y = src[1];
246 struct brw_reg interp = src[2];
247
248 if (brw->has_pln &&
249 delta_y.nr == delta_x.nr + 1 &&
250 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
251 brw_PLN(p, dst, interp, delta_x);
252 } else {
253 brw_LINE(p, brw_null_reg(), interp, delta_x);
254 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
255 }
256 }
257
258 void
259 fs_generator::generate_math1_gen7(fs_inst *inst,
260 struct brw_reg dst,
261 struct brw_reg src0)
262 {
263 assert(inst->mlen == 0);
264 brw_math(p, dst,
265 brw_math_function(inst->opcode),
266 0, src0,
267 BRW_MATH_DATA_VECTOR,
268 BRW_MATH_PRECISION_FULL);
269 }
270
271 void
272 fs_generator::generate_math2_gen7(fs_inst *inst,
273 struct brw_reg dst,
274 struct brw_reg src0,
275 struct brw_reg src1)
276 {
277 assert(inst->mlen == 0);
278 brw_math2(p, dst, brw_math_function(inst->opcode), src0, src1);
279 }
280
281 void
282 fs_generator::generate_math1_gen6(fs_inst *inst,
283 struct brw_reg dst,
284 struct brw_reg src0)
285 {
286 int op = brw_math_function(inst->opcode);
287
288 assert(inst->mlen == 0);
289
290 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
291 brw_math(p, dst,
292 op,
293 0, src0,
294 BRW_MATH_DATA_VECTOR,
295 BRW_MATH_PRECISION_FULL);
296
297 if (dispatch_width == 16) {
298 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
299 brw_math(p, sechalf(dst),
300 op,
301 0, sechalf(src0),
302 BRW_MATH_DATA_VECTOR,
303 BRW_MATH_PRECISION_FULL);
304 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
305 }
306 }
307
308 void
309 fs_generator::generate_math2_gen6(fs_inst *inst,
310 struct brw_reg dst,
311 struct brw_reg src0,
312 struct brw_reg src1)
313 {
314 int op = brw_math_function(inst->opcode);
315
316 assert(inst->mlen == 0);
317
318 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
319 brw_math2(p, dst, op, src0, src1);
320
321 if (dispatch_width == 16) {
322 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
323 brw_math2(p, sechalf(dst), op, sechalf(src0), sechalf(src1));
324 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
325 }
326 }
327
328 void
329 fs_generator::generate_math_gen4(fs_inst *inst,
330 struct brw_reg dst,
331 struct brw_reg src)
332 {
333 int op = brw_math_function(inst->opcode);
334
335 assert(inst->mlen >= 1);
336
337 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
338 brw_math(p, dst,
339 op,
340 inst->base_mrf, src,
341 BRW_MATH_DATA_VECTOR,
342 BRW_MATH_PRECISION_FULL);
343
344 if (dispatch_width == 16) {
345 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
346 brw_math(p, sechalf(dst),
347 op,
348 inst->base_mrf + 1, sechalf(src),
349 BRW_MATH_DATA_VECTOR,
350 BRW_MATH_PRECISION_FULL);
351
352 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
353 }
354 }
355
356 void
357 fs_generator::generate_math_g45(fs_inst *inst,
358 struct brw_reg dst,
359 struct brw_reg src)
360 {
361 if (inst->opcode == SHADER_OPCODE_POW ||
362 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
363 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
364 generate_math_gen4(inst, dst, src);
365 return;
366 }
367
368 int op = brw_math_function(inst->opcode);
369
370 assert(inst->mlen >= 1);
371
372 brw_math(p, dst,
373 op,
374 inst->base_mrf, src,
375 BRW_MATH_DATA_VECTOR,
376 BRW_MATH_PRECISION_FULL);
377 }
378
379 void
380 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
381 {
382 int msg_type = -1;
383 int rlen = 4;
384 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
385 uint32_t return_format;
386
387 switch (dst.type) {
388 case BRW_REGISTER_TYPE_D:
389 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
390 break;
391 case BRW_REGISTER_TYPE_UD:
392 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
393 break;
394 default:
395 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
396 break;
397 }
398
399 if (dispatch_width == 16 &&
400 !inst->force_uncompressed && !inst->force_sechalf)
401 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
402
403 if (brw->gen >= 5) {
404 switch (inst->opcode) {
405 case SHADER_OPCODE_TEX:
406 if (inst->shadow_compare) {
407 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
408 } else {
409 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
410 }
411 break;
412 case FS_OPCODE_TXB:
413 if (inst->shadow_compare) {
414 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
415 } else {
416 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
417 }
418 break;
419 case SHADER_OPCODE_TXL:
420 if (inst->shadow_compare) {
421 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
422 } else {
423 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
424 }
425 break;
426 case SHADER_OPCODE_TXS:
427 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
428 break;
429 case SHADER_OPCODE_TXD:
430 if (inst->shadow_compare) {
431 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
432 assert(brw->is_haswell);
433 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
434 } else {
435 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
436 }
437 break;
438 case SHADER_OPCODE_TXF:
439 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
440 break;
441 case SHADER_OPCODE_TXF_CMS:
442 if (brw->gen >= 7)
443 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
444 else
445 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
446 break;
447 case SHADER_OPCODE_TXF_UMS:
448 assert(brw->gen >= 7);
449 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
450 break;
451 case SHADER_OPCODE_TXF_MCS:
452 assert(brw->gen >= 7);
453 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
454 break;
455 case SHADER_OPCODE_LOD:
456 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
457 break;
458 case SHADER_OPCODE_TG4:
459 if (inst->shadow_compare) {
460 assert(brw->gen >= 7);
461 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
462 } else {
463 assert(brw->gen >= 6);
464 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
465 }
466 break;
467 case SHADER_OPCODE_TG4_OFFSET:
468 assert(brw->gen >= 7);
469 if (inst->shadow_compare) {
470 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
471 } else {
472 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
473 }
474 break;
475 default:
476 assert(!"not reached");
477 break;
478 }
479 } else {
480 switch (inst->opcode) {
481 case SHADER_OPCODE_TEX:
482 /* Note that G45 and older determines shadow compare and dispatch width
483 * from message length for most messages.
484 */
485 assert(dispatch_width == 8);
486 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
487 if (inst->shadow_compare) {
488 assert(inst->mlen == 6);
489 } else {
490 assert(inst->mlen <= 4);
491 }
492 break;
493 case FS_OPCODE_TXB:
494 if (inst->shadow_compare) {
495 assert(inst->mlen == 6);
496 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
497 } else {
498 assert(inst->mlen == 9);
499 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
500 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
501 }
502 break;
503 case SHADER_OPCODE_TXL:
504 if (inst->shadow_compare) {
505 assert(inst->mlen == 6);
506 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
507 } else {
508 assert(inst->mlen == 9);
509 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
510 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
511 }
512 break;
513 case SHADER_OPCODE_TXD:
514 /* There is no sample_d_c message; comparisons are done manually */
515 assert(inst->mlen == 7 || inst->mlen == 10);
516 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
517 break;
518 case SHADER_OPCODE_TXF:
519 assert(inst->mlen == 9);
520 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
521 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
522 break;
523 case SHADER_OPCODE_TXS:
524 assert(inst->mlen == 3);
525 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
526 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
527 break;
528 default:
529 assert(!"not reached");
530 break;
531 }
532 }
533 assert(msg_type != -1);
534
535 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
536 rlen = 8;
537 dst = vec16(dst);
538 }
539
540 if (brw->gen >= 7 && inst->header_present && dispatch_width == 16) {
541 /* The send-from-GRF for SIMD16 texturing with a header has an extra
542 * hardware register allocated to it, which we need to skip over (since
543 * our coordinates in the payload are in the even-numbered registers,
544 * and the header comes right before the first one).
545 */
546 assert(src.file == BRW_GENERAL_REGISTER_FILE);
547 src.nr++;
548 }
549
550 /* Load the message header if present. If there's a texture offset,
551 * we need to set it up explicitly and load the offset bitfield.
552 * Otherwise, we can use an implied move from g0 to the first message reg.
553 */
554 if (inst->header_present) {
555 if (brw->gen < 6 && !inst->texture_offset) {
556 /* Set up an implied move from g0 to the MRF. */
557 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
558 } else {
559 struct brw_reg header_reg;
560
561 if (brw->gen >= 7) {
562 header_reg = src;
563 } else {
564 assert(inst->base_mrf != -1);
565 header_reg = brw_message_reg(inst->base_mrf);
566 }
567
568 brw_push_insn_state(p);
569 brw_set_mask_control(p, BRW_MASK_DISABLE);
570 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
571 /* Explicitly set up the message header by copying g0 to the MRF. */
572 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
573
574 if (inst->texture_offset) {
575 /* Set the offset bits in DWord 2. */
576 brw_MOV(p, get_element_ud(header_reg, 2),
577 brw_imm_ud(inst->texture_offset));
578 }
579
580 if (inst->sampler >= 16) {
581 /* The "Sampler Index" field can only store values between 0 and 15.
582 * However, we can add an offset to the "Sampler State Pointer"
583 * field, effectively selecting a different set of 16 samplers.
584 *
585 * The "Sampler State Pointer" needs to be aligned to a 32-byte
586 * offset, and each sampler state is only 16-bytes, so we can't
587 * exclusively use the offset - we have to use both.
588 */
589 assert(brw->is_haswell); /* field only exists on Haswell */
590 brw_ADD(p,
591 get_element_ud(header_reg, 3),
592 get_element_ud(brw_vec8_grf(0, 0), 3),
593 brw_imm_ud(16 * (inst->sampler / 16) *
594 sizeof(gen7_sampler_state)));
595 }
596 brw_pop_insn_state(p);
597 }
598 }
599
600 uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
601 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
602 ? c->prog_data.base.binding_table.gather_texture_start
603 : c->prog_data.base.binding_table.texture_start) + inst->sampler;
604
605 brw_SAMPLE(p,
606 retype(dst, BRW_REGISTER_TYPE_UW),
607 inst->base_mrf,
608 src,
609 surface_index,
610 inst->sampler % 16,
611 msg_type,
612 rlen,
613 inst->mlen,
614 inst->header_present,
615 simd_mode,
616 return_format);
617
618 mark_surface_used(surface_index);
619 }
620
621
622 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
623 * looking like:
624 *
625 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
626 *
627 * Ideally, we want to produce:
628 *
629 * DDX DDY
630 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
631 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
632 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
633 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
634 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
635 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
636 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
637 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
638 *
639 * and add another set of two more subspans if in 16-pixel dispatch mode.
640 *
641 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
642 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
643 * pair. But the ideal approximation may impose a huge performance cost on
644 * sample_d. On at least Haswell, sample_d instruction does some
645 * optimizations if the same LOD is used for all pixels in the subspan.
646 *
647 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
648 * appropriate swizzling.
649 */
650 void
651 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
652 {
653 unsigned vstride, width;
654
655 if (c->key.high_quality_derivatives) {
656 /* produce accurate derivatives */
657 vstride = BRW_VERTICAL_STRIDE_2;
658 width = BRW_WIDTH_2;
659 }
660 else {
661 /* replicate the derivative at the top-left pixel to other pixels */
662 vstride = BRW_VERTICAL_STRIDE_4;
663 width = BRW_WIDTH_4;
664 }
665
666 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
667 BRW_REGISTER_TYPE_F,
668 vstride,
669 width,
670 BRW_HORIZONTAL_STRIDE_0,
671 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
672 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
673 BRW_REGISTER_TYPE_F,
674 vstride,
675 width,
676 BRW_HORIZONTAL_STRIDE_0,
677 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
678 brw_ADD(p, dst, src0, negate(src1));
679 }
680
681 /* The negate_value boolean is used to negate the derivative computation for
682 * FBOs, since they place the origin at the upper left instead of the lower
683 * left.
684 */
685 void
686 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
687 bool negate_value)
688 {
689 if (c->key.high_quality_derivatives) {
690 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
691 * Region Restrictions):
692 *
693 * In Align16 access mode, SIMD16 is not allowed for DW operations
694 * and SIMD8 is not allowed for DF operations.
695 *
696 * In this context, "DW operations" means "operations acting on 32-bit
697 * values", so it includes operations on floats.
698 *
699 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
700 * (Instruction Compression -> Rules and Restrictions):
701 *
702 * A compressed instruction must be in Align1 access mode. Align16
703 * mode instructions cannot be compressed.
704 *
705 * Similar text exists in the g45 PRM.
706 *
707 * On these platforms, if we're building a SIMD16 shader, we need to
708 * manually unroll to a pair of SIMD8 instructions.
709 */
710 bool unroll_to_simd8 =
711 (dispatch_width == 16 &&
712 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
713
714 /* produce accurate derivatives */
715 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
716 BRW_REGISTER_TYPE_F,
717 BRW_VERTICAL_STRIDE_4,
718 BRW_WIDTH_4,
719 BRW_HORIZONTAL_STRIDE_1,
720 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
721 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
722 BRW_REGISTER_TYPE_F,
723 BRW_VERTICAL_STRIDE_4,
724 BRW_WIDTH_4,
725 BRW_HORIZONTAL_STRIDE_1,
726 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
727 brw_push_insn_state(p);
728 brw_set_access_mode(p, BRW_ALIGN_16);
729 if (unroll_to_simd8)
730 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
731 if (negate_value)
732 brw_ADD(p, dst, src1, negate(src0));
733 else
734 brw_ADD(p, dst, src0, negate(src1));
735 if (unroll_to_simd8) {
736 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
737 src0 = sechalf(src0);
738 src1 = sechalf(src1);
739 dst = sechalf(dst);
740 if (negate_value)
741 brw_ADD(p, dst, src1, negate(src0));
742 else
743 brw_ADD(p, dst, src0, negate(src1));
744 }
745 brw_pop_insn_state(p);
746 } else {
747 /* replicate the derivative at the top-left pixel to other pixels */
748 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
749 BRW_REGISTER_TYPE_F,
750 BRW_VERTICAL_STRIDE_4,
751 BRW_WIDTH_4,
752 BRW_HORIZONTAL_STRIDE_0,
753 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
754 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
755 BRW_REGISTER_TYPE_F,
756 BRW_VERTICAL_STRIDE_4,
757 BRW_WIDTH_4,
758 BRW_HORIZONTAL_STRIDE_0,
759 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
760 if (negate_value)
761 brw_ADD(p, dst, src1, negate(src0));
762 else
763 brw_ADD(p, dst, src0, negate(src1));
764 }
765 }
766
767 void
768 fs_generator::generate_discard_jump(fs_inst *inst)
769 {
770 assert(brw->gen >= 6);
771
772 /* This HALT will be patched up at FB write time to point UIP at the end of
773 * the program, and at brw_uip_jip() JIP will be set to the end of the
774 * current block (or the program).
775 */
776 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
777
778 brw_push_insn_state(p);
779 brw_set_mask_control(p, BRW_MASK_DISABLE);
780 gen6_HALT(p);
781 brw_pop_insn_state(p);
782 }
783
784 void
785 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
786 {
787 assert(inst->mlen != 0);
788
789 brw_MOV(p,
790 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
791 retype(src, BRW_REGISTER_TYPE_UD));
792 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
793 dispatch_width / 8, inst->offset);
794 }
795
796 void
797 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
798 {
799 assert(inst->mlen != 0);
800
801 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
802 dispatch_width / 8, inst->offset);
803 }
804
805 void
806 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
807 {
808 gen7_block_read_scratch(p, dst, dispatch_width / 8, inst->offset);
809 }
810
811 void
812 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
813 struct brw_reg dst,
814 struct brw_reg index,
815 struct brw_reg offset)
816 {
817 assert(inst->mlen != 0);
818
819 assert(index.file == BRW_IMMEDIATE_VALUE &&
820 index.type == BRW_REGISTER_TYPE_UD);
821 uint32_t surf_index = index.dw1.ud;
822
823 assert(offset.file == BRW_IMMEDIATE_VALUE &&
824 offset.type == BRW_REGISTER_TYPE_UD);
825 uint32_t read_offset = offset.dw1.ud;
826
827 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
828 read_offset, surf_index);
829
830 mark_surface_used(surf_index);
831 }
832
833 void
834 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
835 struct brw_reg dst,
836 struct brw_reg index,
837 struct brw_reg offset)
838 {
839 assert(inst->mlen == 0);
840
841 assert(index.file == BRW_IMMEDIATE_VALUE &&
842 index.type == BRW_REGISTER_TYPE_UD);
843 uint32_t surf_index = index.dw1.ud;
844
845 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
846 /* Reference just the dword we need, to avoid angering validate_reg(). */
847 offset = brw_vec1_grf(offset.nr, 0);
848
849 brw_push_insn_state(p);
850 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
851 brw_set_mask_control(p, BRW_MASK_DISABLE);
852 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
853 brw_pop_insn_state(p);
854
855 /* We use the SIMD4x2 mode because we want to end up with 4 components in
856 * the destination loaded consecutively from the same offset (which appears
857 * in the first component, and the rest are ignored).
858 */
859 dst.width = BRW_WIDTH_4;
860 brw_set_dest(p, send, dst);
861 brw_set_src0(p, send, offset);
862 brw_set_sampler_message(p, send,
863 surf_index,
864 0, /* LD message ignores sampler unit */
865 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
866 1, /* rlen */
867 1, /* mlen */
868 false, /* no header */
869 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
870 0);
871
872 mark_surface_used(surf_index);
873 }
874
875 void
876 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
877 struct brw_reg dst,
878 struct brw_reg index,
879 struct brw_reg offset)
880 {
881 assert(brw->gen < 7); /* Should use the gen7 variant. */
882 assert(inst->header_present);
883 assert(inst->mlen);
884
885 assert(index.file == BRW_IMMEDIATE_VALUE &&
886 index.type == BRW_REGISTER_TYPE_UD);
887 uint32_t surf_index = index.dw1.ud;
888
889 uint32_t simd_mode, rlen, msg_type;
890 if (dispatch_width == 16) {
891 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
892 rlen = 8;
893 } else {
894 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
895 rlen = 4;
896 }
897
898 if (brw->gen >= 5)
899 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
900 else {
901 /* We always use the SIMD16 message so that we only have to load U, and
902 * not V or R.
903 */
904 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
905 assert(inst->mlen == 3);
906 assert(inst->regs_written == 8);
907 rlen = 8;
908 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
909 }
910
911 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
912 BRW_REGISTER_TYPE_D);
913 brw_MOV(p, offset_mrf, offset);
914
915 struct brw_reg header = brw_vec8_grf(0, 0);
916 gen6_resolve_implied_move(p, &header, inst->base_mrf);
917
918 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
919 send->header.compression_control = BRW_COMPRESSION_NONE;
920 brw_set_dest(p, send, dst);
921 brw_set_src0(p, send, header);
922 if (brw->gen < 6)
923 send->header.destreg__conditionalmod = inst->base_mrf;
924
925 /* Our surface is set up as floats, regardless of what actual data is
926 * stored in it.
927 */
928 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
929 brw_set_sampler_message(p, send,
930 surf_index,
931 0, /* sampler (unused) */
932 msg_type,
933 rlen,
934 inst->mlen,
935 inst->header_present,
936 simd_mode,
937 return_format);
938
939 mark_surface_used(surf_index);
940 }
941
942 void
943 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
944 struct brw_reg dst,
945 struct brw_reg index,
946 struct brw_reg offset)
947 {
948 assert(brw->gen >= 7);
949 /* Varying-offset pull constant loads are treated as a normal expression on
950 * gen7, so the fact that it's a send message is hidden at the IR level.
951 */
952 assert(!inst->header_present);
953 assert(!inst->mlen);
954
955 assert(index.file == BRW_IMMEDIATE_VALUE &&
956 index.type == BRW_REGISTER_TYPE_UD);
957 uint32_t surf_index = index.dw1.ud;
958
959 uint32_t simd_mode, rlen, mlen;
960 if (dispatch_width == 16) {
961 mlen = 2;
962 rlen = 8;
963 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
964 } else {
965 mlen = 1;
966 rlen = 4;
967 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
968 }
969
970 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
971 brw_set_dest(p, send, dst);
972 brw_set_src0(p, send, offset);
973 brw_set_sampler_message(p, send,
974 surf_index,
975 0, /* LD message ignores sampler unit */
976 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
977 rlen,
978 mlen,
979 false, /* no header */
980 simd_mode,
981 0);
982
983 mark_surface_used(surf_index);
984 }
985
986 /**
987 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
988 * into the flags register (f0.0).
989 *
990 * Used only on Gen6 and above.
991 */
992 void
993 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
994 {
995 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
996 struct brw_reg dispatch_mask;
997
998 if (brw->gen >= 6)
999 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1000 else
1001 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1002
1003 brw_push_insn_state(p);
1004 brw_set_mask_control(p, BRW_MASK_DISABLE);
1005 brw_MOV(p, flags, dispatch_mask);
1006 brw_pop_insn_state(p);
1007 }
1008
1009
1010 static uint32_t brw_file_from_reg(fs_reg *reg)
1011 {
1012 switch (reg->file) {
1013 case GRF:
1014 return BRW_GENERAL_REGISTER_FILE;
1015 case MRF:
1016 return BRW_MESSAGE_REGISTER_FILE;
1017 case IMM:
1018 return BRW_IMMEDIATE_VALUE;
1019 default:
1020 assert(!"not reached");
1021 return BRW_GENERAL_REGISTER_FILE;
1022 }
1023 }
1024
1025 struct brw_reg
1026 brw_reg_from_fs_reg(fs_reg *reg)
1027 {
1028 struct brw_reg brw_reg;
1029
1030 switch (reg->file) {
1031 case GRF:
1032 case MRF:
1033 if (reg->stride == 0 || reg->smear >= 0) {
1034 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, reg->smear);
1035 } else {
1036 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1037 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
1038 }
1039
1040 brw_reg = retype(brw_reg, reg->type);
1041 if (reg->sechalf)
1042 brw_reg = sechalf(brw_reg);
1043 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
1044 break;
1045 case IMM:
1046 switch (reg->type) {
1047 case BRW_REGISTER_TYPE_F:
1048 brw_reg = brw_imm_f(reg->imm.f);
1049 break;
1050 case BRW_REGISTER_TYPE_D:
1051 brw_reg = brw_imm_d(reg->imm.i);
1052 break;
1053 case BRW_REGISTER_TYPE_UD:
1054 brw_reg = brw_imm_ud(reg->imm.u);
1055 break;
1056 default:
1057 assert(!"not reached");
1058 brw_reg = brw_null_reg();
1059 break;
1060 }
1061 break;
1062 case HW_REG:
1063 brw_reg = reg->fixed_hw_reg;
1064 break;
1065 case BAD_FILE:
1066 /* Probably unused. */
1067 brw_reg = brw_null_reg();
1068 break;
1069 case UNIFORM:
1070 assert(!"not reached");
1071 brw_reg = brw_null_reg();
1072 break;
1073 default:
1074 assert(!"not reached");
1075 brw_reg = brw_null_reg();
1076 break;
1077 }
1078 if (reg->abs)
1079 brw_reg = brw_abs(brw_reg);
1080 if (reg->negate)
1081 brw_reg = negate(brw_reg);
1082
1083 return brw_reg;
1084 }
1085
1086 /**
1087 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1088 * sampler LD messages.
1089 *
1090 * We don't want to bake it into the send message's code generation because
1091 * that means we don't get a chance to schedule the instructions.
1092 */
1093 void
1094 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1095 struct brw_reg dst,
1096 struct brw_reg value)
1097 {
1098 assert(value.file == BRW_IMMEDIATE_VALUE);
1099
1100 brw_push_insn_state(p);
1101 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1102 brw_set_mask_control(p, BRW_MASK_DISABLE);
1103 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1104 brw_pop_insn_state(p);
1105 }
1106
1107 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1108 * (when mask is passed as a uniform) of register mask before moving it
1109 * to register dst.
1110 */
1111 void
1112 fs_generator::generate_set_omask(fs_inst *inst,
1113 struct brw_reg dst,
1114 struct brw_reg mask)
1115 {
1116 bool stride_8_8_1 =
1117 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1118 mask.width == BRW_WIDTH_8 &&
1119 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1120
1121 bool stride_0_1_0 =
1122 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1123 mask.width == BRW_WIDTH_1 &&
1124 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1125
1126 assert(stride_8_8_1 || stride_0_1_0);
1127 assert(dst.type == BRW_REGISTER_TYPE_UW);
1128
1129 if (dispatch_width == 16)
1130 dst = vec16(dst);
1131 brw_push_insn_state(p);
1132 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1133 brw_set_mask_control(p, BRW_MASK_DISABLE);
1134
1135 if (stride_8_8_1) {
1136 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1137 } else if (stride_0_1_0) {
1138 brw_MOV(p, dst, retype(mask, dst.type));
1139 }
1140 brw_pop_insn_state(p);
1141 }
1142
1143 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1144 * the ADD instruction.
1145 */
1146 void
1147 fs_generator::generate_set_sample_id(fs_inst *inst,
1148 struct brw_reg dst,
1149 struct brw_reg src0,
1150 struct brw_reg src1)
1151 {
1152 assert(dst.type == BRW_REGISTER_TYPE_D ||
1153 dst.type == BRW_REGISTER_TYPE_UD);
1154 assert(src0.type == BRW_REGISTER_TYPE_D ||
1155 src0.type == BRW_REGISTER_TYPE_UD);
1156
1157 brw_push_insn_state(p);
1158 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1159 brw_set_mask_control(p, BRW_MASK_DISABLE);
1160 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1161 brw_ADD(p, dst, src0, reg);
1162 if (dispatch_width == 16)
1163 brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
1164 brw_pop_insn_state(p);
1165 }
1166
1167 /**
1168 * Change the register's data type from UD to W, doubling the strides in order
1169 * to compensate for halving the data type width.
1170 */
1171 static struct brw_reg
1172 ud_reg_to_w(struct brw_reg r)
1173 {
1174 assert(r.type == BRW_REGISTER_TYPE_UD);
1175 r.type = BRW_REGISTER_TYPE_W;
1176
1177 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1178 * doubles the real stride.
1179 */
1180 if (r.hstride != 0)
1181 ++r.hstride;
1182 if (r.vstride != 0)
1183 ++r.vstride;
1184
1185 return r;
1186 }
1187
1188 void
1189 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1190 struct brw_reg dst,
1191 struct brw_reg x,
1192 struct brw_reg y)
1193 {
1194 assert(brw->gen >= 7);
1195 assert(dst.type == BRW_REGISTER_TYPE_UD);
1196 assert(x.type == BRW_REGISTER_TYPE_F);
1197 assert(y.type == BRW_REGISTER_TYPE_F);
1198
1199 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1200 *
1201 * Because this instruction does not have a 16-bit floating-point type,
1202 * the destination data type must be Word (W).
1203 *
1204 * The destination must be DWord-aligned and specify a horizontal stride
1205 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1206 * each destination channel and the upper word is not modified.
1207 */
1208 struct brw_reg dst_w = ud_reg_to_w(dst);
1209
1210 /* Give each 32-bit channel of dst the form below , where "." means
1211 * unchanged.
1212 * 0x....hhhh
1213 */
1214 brw_F32TO16(p, dst_w, y);
1215
1216 /* Now the form:
1217 * 0xhhhh0000
1218 */
1219 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1220
1221 /* And, finally the form of packHalf2x16's output:
1222 * 0xhhhhllll
1223 */
1224 brw_F32TO16(p, dst_w, x);
1225 }
1226
1227 void
1228 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1229 struct brw_reg dst,
1230 struct brw_reg src)
1231 {
1232 assert(brw->gen >= 7);
1233 assert(dst.type == BRW_REGISTER_TYPE_F);
1234 assert(src.type == BRW_REGISTER_TYPE_UD);
1235
1236 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1237 *
1238 * Because this instruction does not have a 16-bit floating-point type,
1239 * the source data type must be Word (W). The destination type must be
1240 * F (Float).
1241 */
1242 struct brw_reg src_w = ud_reg_to_w(src);
1243
1244 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1245 * For the Y case, we wish to access only the upper word; therefore
1246 * a 16-bit subregister offset is needed.
1247 */
1248 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1249 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1250 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1251 src_w.subnr += 2;
1252
1253 brw_F16TO32(p, dst, src_w);
1254 }
1255
1256 void
1257 fs_generator::generate_shader_time_add(fs_inst *inst,
1258 struct brw_reg payload,
1259 struct brw_reg offset,
1260 struct brw_reg value)
1261 {
1262 assert(brw->gen >= 7);
1263 brw_push_insn_state(p);
1264 brw_set_mask_control(p, true);
1265
1266 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1267 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1268 offset.type);
1269 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1270 value.type);
1271
1272 assert(offset.file == BRW_IMMEDIATE_VALUE);
1273 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1274 value.width = BRW_WIDTH_1;
1275 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1276 value.vstride = BRW_VERTICAL_STRIDE_0;
1277 } else {
1278 assert(value.file == BRW_IMMEDIATE_VALUE);
1279 }
1280
1281 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1282 * case, and we don't really care about squeezing every bit of performance
1283 * out of this path, so we just emit the MOVs from here.
1284 */
1285 brw_MOV(p, payload_offset, offset);
1286 brw_MOV(p, payload_value, value);
1287 brw_shader_time_add(p, payload,
1288 c->prog_data.base.binding_table.shader_time_start);
1289 brw_pop_insn_state(p);
1290
1291 mark_surface_used(c->prog_data.base.binding_table.shader_time_start);
1292 }
1293
1294 void
1295 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1296 struct brw_reg atomic_op,
1297 struct brw_reg surf_index)
1298 {
1299 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1300 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1301 surf_index.file == BRW_IMMEDIATE_VALUE &&
1302 surf_index.type == BRW_REGISTER_TYPE_UD);
1303
1304 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1305 atomic_op.dw1.ud, surf_index.dw1.ud,
1306 inst->mlen, dispatch_width / 8);
1307
1308 mark_surface_used(surf_index.dw1.ud);
1309 }
1310
1311 void
1312 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1313 struct brw_reg surf_index)
1314 {
1315 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1316 surf_index.type == BRW_REGISTER_TYPE_UD);
1317
1318 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1319 surf_index.dw1.ud,
1320 inst->mlen, dispatch_width / 8);
1321
1322 mark_surface_used(surf_index.dw1.ud);
1323 }
1324
1325 void
1326 fs_generator::generate_code(exec_list *instructions, FILE *dump_file)
1327 {
1328 int last_native_insn_offset = p->next_insn_offset;
1329 const char *last_annotation_string = NULL;
1330 const void *last_annotation_ir = NULL;
1331
1332 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1333 if (prog) {
1334 printf("Native code for fragment shader %d (SIMD%d dispatch):\n",
1335 prog->Name, dispatch_width);
1336 } else if (fp) {
1337 printf("Native code for fragment program %d (SIMD%d dispatch):\n",
1338 fp->Base.Id, dispatch_width);
1339 } else {
1340 printf("Native code for blorp program (SIMD%d dispatch):\n",
1341 dispatch_width);
1342 }
1343 }
1344
1345 cfg_t *cfg = NULL;
1346 if (unlikely(INTEL_DEBUG & DEBUG_WM))
1347 cfg = new(mem_ctx) cfg_t(instructions);
1348
1349 foreach_list(node, instructions) {
1350 fs_inst *inst = (fs_inst *)node;
1351 struct brw_reg src[3], dst;
1352
1353 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1354 foreach_list(node, &cfg->block_list) {
1355 bblock_link *link = (bblock_link *)node;
1356 bblock_t *block = link->block;
1357
1358 if (block->start == inst) {
1359 printf(" START B%d", block->block_num);
1360 foreach_list(predecessor_node, &block->parents) {
1361 bblock_link *predecessor_link =
1362 (bblock_link *)predecessor_node;
1363 bblock_t *predecessor_block = predecessor_link->block;
1364 printf(" <-B%d", predecessor_block->block_num);
1365 }
1366 printf("\n");
1367 }
1368 }
1369
1370 if (last_annotation_ir != inst->ir) {
1371 last_annotation_ir = inst->ir;
1372 if (last_annotation_ir) {
1373 printf(" ");
1374 if (prog)
1375 ((ir_instruction *)inst->ir)->print();
1376 else {
1377 const prog_instruction *fpi;
1378 fpi = (const prog_instruction *)inst->ir;
1379 printf("%d: ", (int)(fpi - (fp ? fp->Base.Instructions : 0)));
1380 _mesa_fprint_instruction_opt(stdout,
1381 fpi,
1382 0, PROG_PRINT_DEBUG, NULL);
1383 }
1384 printf("\n");
1385 }
1386 }
1387 if (last_annotation_string != inst->annotation) {
1388 last_annotation_string = inst->annotation;
1389 if (last_annotation_string)
1390 printf(" %s\n", last_annotation_string);
1391 }
1392 }
1393
1394 for (unsigned int i = 0; i < 3; i++) {
1395 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1396
1397 /* The accumulator result appears to get used for the
1398 * conditional modifier generation. When negating a UD
1399 * value, there is a 33rd bit generated for the sign in the
1400 * accumulator value, so now you can't check, for example,
1401 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1402 */
1403 assert(!inst->conditional_mod ||
1404 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1405 !inst->src[i].negate);
1406 }
1407 dst = brw_reg_from_fs_reg(&inst->dst);
1408
1409 brw_set_conditionalmod(p, inst->conditional_mod);
1410 brw_set_predicate_control(p, inst->predicate);
1411 brw_set_predicate_inverse(p, inst->predicate_inverse);
1412 brw_set_flag_reg(p, 0, inst->flag_subreg);
1413 brw_set_saturate(p, inst->saturate);
1414 brw_set_mask_control(p, inst->force_writemask_all);
1415
1416 if (inst->force_uncompressed || dispatch_width == 8) {
1417 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1418 } else if (inst->force_sechalf) {
1419 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1420 } else {
1421 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1422 }
1423
1424 switch (inst->opcode) {
1425 case BRW_OPCODE_MOV:
1426 brw_MOV(p, dst, src[0]);
1427 break;
1428 case BRW_OPCODE_ADD:
1429 brw_ADD(p, dst, src[0], src[1]);
1430 break;
1431 case BRW_OPCODE_MUL:
1432 brw_MUL(p, dst, src[0], src[1]);
1433 break;
1434 case BRW_OPCODE_AVG:
1435 brw_AVG(p, dst, src[0], src[1]);
1436 break;
1437 case BRW_OPCODE_MACH:
1438 brw_set_acc_write_control(p, 1);
1439 brw_MACH(p, dst, src[0], src[1]);
1440 brw_set_acc_write_control(p, 0);
1441 break;
1442
1443 case BRW_OPCODE_MAD:
1444 assert(brw->gen >= 6);
1445 brw_set_access_mode(p, BRW_ALIGN_16);
1446 if (dispatch_width == 16 && !brw->is_haswell) {
1447 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1448 brw_MAD(p, dst, src[0], src[1], src[2]);
1449 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1450 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1451 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1452 } else {
1453 brw_MAD(p, dst, src[0], src[1], src[2]);
1454 }
1455 brw_set_access_mode(p, BRW_ALIGN_1);
1456 break;
1457
1458 case BRW_OPCODE_LRP:
1459 assert(brw->gen >= 6);
1460 brw_set_access_mode(p, BRW_ALIGN_16);
1461 if (dispatch_width == 16 && !brw->is_haswell) {
1462 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1463 brw_LRP(p, dst, src[0], src[1], src[2]);
1464 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1465 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1466 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1467 } else {
1468 brw_LRP(p, dst, src[0], src[1], src[2]);
1469 }
1470 brw_set_access_mode(p, BRW_ALIGN_1);
1471 break;
1472
1473 case BRW_OPCODE_FRC:
1474 brw_FRC(p, dst, src[0]);
1475 break;
1476 case BRW_OPCODE_RNDD:
1477 brw_RNDD(p, dst, src[0]);
1478 break;
1479 case BRW_OPCODE_RNDE:
1480 brw_RNDE(p, dst, src[0]);
1481 break;
1482 case BRW_OPCODE_RNDZ:
1483 brw_RNDZ(p, dst, src[0]);
1484 break;
1485
1486 case BRW_OPCODE_AND:
1487 brw_AND(p, dst, src[0], src[1]);
1488 break;
1489 case BRW_OPCODE_OR:
1490 brw_OR(p, dst, src[0], src[1]);
1491 break;
1492 case BRW_OPCODE_XOR:
1493 brw_XOR(p, dst, src[0], src[1]);
1494 break;
1495 case BRW_OPCODE_NOT:
1496 brw_NOT(p, dst, src[0]);
1497 break;
1498 case BRW_OPCODE_ASR:
1499 brw_ASR(p, dst, src[0], src[1]);
1500 break;
1501 case BRW_OPCODE_SHR:
1502 brw_SHR(p, dst, src[0], src[1]);
1503 break;
1504 case BRW_OPCODE_SHL:
1505 brw_SHL(p, dst, src[0], src[1]);
1506 break;
1507 case BRW_OPCODE_F32TO16:
1508 assert(brw->gen >= 7);
1509 brw_F32TO16(p, dst, src[0]);
1510 break;
1511 case BRW_OPCODE_F16TO32:
1512 assert(brw->gen >= 7);
1513 brw_F16TO32(p, dst, src[0]);
1514 break;
1515 case BRW_OPCODE_CMP:
1516 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1517 break;
1518 case BRW_OPCODE_SEL:
1519 brw_SEL(p, dst, src[0], src[1]);
1520 break;
1521 case BRW_OPCODE_BFREV:
1522 assert(brw->gen >= 7);
1523 /* BFREV only supports UD type for src and dst. */
1524 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1525 retype(src[0], BRW_REGISTER_TYPE_UD));
1526 break;
1527 case BRW_OPCODE_FBH:
1528 assert(brw->gen >= 7);
1529 /* FBH only supports UD type for dst. */
1530 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1531 break;
1532 case BRW_OPCODE_FBL:
1533 assert(brw->gen >= 7);
1534 /* FBL only supports UD type for dst. */
1535 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1536 break;
1537 case BRW_OPCODE_CBIT:
1538 assert(brw->gen >= 7);
1539 /* CBIT only supports UD type for dst. */
1540 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1541 break;
1542 case BRW_OPCODE_ADDC:
1543 assert(brw->gen >= 7);
1544 brw_set_acc_write_control(p, 1);
1545 brw_ADDC(p, dst, src[0], src[1]);
1546 brw_set_acc_write_control(p, 0);
1547 break;
1548 case BRW_OPCODE_SUBB:
1549 assert(brw->gen >= 7);
1550 brw_set_acc_write_control(p, 1);
1551 brw_SUBB(p, dst, src[0], src[1]);
1552 brw_set_acc_write_control(p, 0);
1553 break;
1554
1555 case BRW_OPCODE_BFE:
1556 assert(brw->gen >= 7);
1557 brw_set_access_mode(p, BRW_ALIGN_16);
1558 if (dispatch_width == 16 && !brw->is_haswell) {
1559 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1560 brw_BFE(p, dst, src[0], src[1], src[2]);
1561 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1562 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1563 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1564 } else {
1565 brw_BFE(p, dst, src[0], src[1], src[2]);
1566 }
1567 brw_set_access_mode(p, BRW_ALIGN_1);
1568 break;
1569
1570 case BRW_OPCODE_BFI1:
1571 assert(brw->gen >= 7);
1572 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1573 * should
1574 *
1575 * "Force BFI instructions to be executed always in SIMD8."
1576 */
1577 if (dispatch_width == 16 && brw->is_haswell) {
1578 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1579 brw_BFI1(p, dst, src[0], src[1]);
1580 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1581 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1582 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1583 } else {
1584 brw_BFI1(p, dst, src[0], src[1]);
1585 }
1586 break;
1587 case BRW_OPCODE_BFI2:
1588 assert(brw->gen >= 7);
1589 brw_set_access_mode(p, BRW_ALIGN_16);
1590 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1591 * should
1592 *
1593 * "Force BFI instructions to be executed always in SIMD8."
1594 *
1595 * Otherwise we would be able to emit compressed instructions like we
1596 * do for the other three-source instructions.
1597 */
1598 if (dispatch_width == 16) {
1599 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1600 brw_BFI2(p, dst, src[0], src[1], src[2]);
1601 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1602 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1603 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1604 } else {
1605 brw_BFI2(p, dst, src[0], src[1], src[2]);
1606 }
1607 brw_set_access_mode(p, BRW_ALIGN_1);
1608 break;
1609
1610 case BRW_OPCODE_IF:
1611 if (inst->src[0].file != BAD_FILE) {
1612 /* The instruction has an embedded compare (only allowed on gen6) */
1613 assert(brw->gen == 6);
1614 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1615 } else {
1616 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1617 }
1618 break;
1619
1620 case BRW_OPCODE_ELSE:
1621 brw_ELSE(p);
1622 break;
1623 case BRW_OPCODE_ENDIF:
1624 brw_ENDIF(p);
1625 break;
1626
1627 case BRW_OPCODE_DO:
1628 brw_DO(p, BRW_EXECUTE_8);
1629 break;
1630
1631 case BRW_OPCODE_BREAK:
1632 brw_BREAK(p);
1633 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1634 break;
1635 case BRW_OPCODE_CONTINUE:
1636 /* FINISHME: We need to write the loop instruction support still. */
1637 if (brw->gen >= 6)
1638 gen6_CONT(p);
1639 else
1640 brw_CONT(p);
1641 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1642 break;
1643
1644 case BRW_OPCODE_WHILE:
1645 brw_WHILE(p);
1646 break;
1647
1648 case SHADER_OPCODE_RCP:
1649 case SHADER_OPCODE_RSQ:
1650 case SHADER_OPCODE_SQRT:
1651 case SHADER_OPCODE_EXP2:
1652 case SHADER_OPCODE_LOG2:
1653 case SHADER_OPCODE_SIN:
1654 case SHADER_OPCODE_COS:
1655 if (brw->gen >= 7) {
1656 generate_math1_gen7(inst, dst, src[0]);
1657 } else if (brw->gen == 6) {
1658 generate_math1_gen6(inst, dst, src[0]);
1659 } else if (brw->gen == 5 || brw->is_g4x) {
1660 generate_math_g45(inst, dst, src[0]);
1661 } else {
1662 generate_math_gen4(inst, dst, src[0]);
1663 }
1664 break;
1665 case SHADER_OPCODE_INT_QUOTIENT:
1666 case SHADER_OPCODE_INT_REMAINDER:
1667 case SHADER_OPCODE_POW:
1668 if (brw->gen >= 7) {
1669 generate_math2_gen7(inst, dst, src[0], src[1]);
1670 } else if (brw->gen == 6) {
1671 generate_math2_gen6(inst, dst, src[0], src[1]);
1672 } else {
1673 generate_math_gen4(inst, dst, src[0]);
1674 }
1675 break;
1676 case FS_OPCODE_PIXEL_X:
1677 generate_pixel_xy(dst, true);
1678 break;
1679 case FS_OPCODE_PIXEL_Y:
1680 generate_pixel_xy(dst, false);
1681 break;
1682 case FS_OPCODE_CINTERP:
1683 brw_MOV(p, dst, src[0]);
1684 break;
1685 case FS_OPCODE_LINTERP:
1686 generate_linterp(inst, dst, src);
1687 break;
1688 case SHADER_OPCODE_TEX:
1689 case FS_OPCODE_TXB:
1690 case SHADER_OPCODE_TXD:
1691 case SHADER_OPCODE_TXF:
1692 case SHADER_OPCODE_TXF_CMS:
1693 case SHADER_OPCODE_TXF_UMS:
1694 case SHADER_OPCODE_TXF_MCS:
1695 case SHADER_OPCODE_TXL:
1696 case SHADER_OPCODE_TXS:
1697 case SHADER_OPCODE_LOD:
1698 case SHADER_OPCODE_TG4:
1699 case SHADER_OPCODE_TG4_OFFSET:
1700 generate_tex(inst, dst, src[0]);
1701 break;
1702 case FS_OPCODE_DDX:
1703 generate_ddx(inst, dst, src[0]);
1704 break;
1705 case FS_OPCODE_DDY:
1706 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1707 * guarantee that c->key.render_to_fbo is set).
1708 */
1709 assert(fp->UsesDFdy);
1710 generate_ddy(inst, dst, src[0], c->key.render_to_fbo);
1711 break;
1712
1713 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1714 generate_scratch_write(inst, src[0]);
1715 break;
1716
1717 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1718 generate_scratch_read(inst, dst);
1719 break;
1720
1721 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1722 generate_scratch_read_gen7(inst, dst);
1723 break;
1724
1725 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1726 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1727 break;
1728
1729 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1730 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1731 break;
1732
1733 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1734 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1735 break;
1736
1737 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1738 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1739 break;
1740
1741 case FS_OPCODE_FB_WRITE:
1742 generate_fb_write(inst);
1743 break;
1744
1745 case FS_OPCODE_BLORP_FB_WRITE:
1746 generate_blorp_fb_write(inst);
1747 break;
1748
1749 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1750 generate_mov_dispatch_to_flags(inst);
1751 break;
1752
1753 case FS_OPCODE_DISCARD_JUMP:
1754 generate_discard_jump(inst);
1755 break;
1756
1757 case SHADER_OPCODE_SHADER_TIME_ADD:
1758 generate_shader_time_add(inst, src[0], src[1], src[2]);
1759 break;
1760
1761 case SHADER_OPCODE_UNTYPED_ATOMIC:
1762 generate_untyped_atomic(inst, dst, src[0], src[1]);
1763 break;
1764
1765 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1766 generate_untyped_surface_read(inst, dst, src[0]);
1767 break;
1768
1769 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1770 generate_set_simd4x2_offset(inst, dst, src[0]);
1771 break;
1772
1773 case FS_OPCODE_SET_OMASK:
1774 generate_set_omask(inst, dst, src[0]);
1775 break;
1776
1777 case FS_OPCODE_SET_SAMPLE_ID:
1778 generate_set_sample_id(inst, dst, src[0], src[1]);
1779 break;
1780
1781 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1782 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1783 break;
1784
1785 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1786 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1787 generate_unpack_half_2x16_split(inst, dst, src[0]);
1788 break;
1789
1790 case FS_OPCODE_PLACEHOLDER_HALT:
1791 /* This is the place where the final HALT needs to be inserted if
1792 * we've emitted any discards. If not, this will emit no code.
1793 */
1794 patch_discard_jumps_to_fb_writes();
1795 break;
1796
1797 default:
1798 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1799 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1800 opcode_descs[inst->opcode].name);
1801 } else {
1802 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1803 }
1804 abort();
1805 }
1806
1807 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1808 brw_dump_compile(p, stdout,
1809 last_native_insn_offset, p->next_insn_offset);
1810
1811 foreach_list(node, &cfg->block_list) {
1812 bblock_link *link = (bblock_link *)node;
1813 bblock_t *block = link->block;
1814
1815 if (block->end == inst) {
1816 printf(" END B%d", block->block_num);
1817 foreach_list(successor_node, &block->children) {
1818 bblock_link *successor_link =
1819 (bblock_link *)successor_node;
1820 bblock_t *successor_block = successor_link->block;
1821 printf(" ->B%d", successor_block->block_num);
1822 }
1823 printf("\n");
1824 }
1825 }
1826 }
1827
1828 last_native_insn_offset = p->next_insn_offset;
1829 }
1830
1831 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1832 printf("\n");
1833 }
1834
1835 brw_set_uip_jip(p);
1836
1837 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
1838 * emit issues, it doesn't get the jump distances into the output,
1839 * which is often something we want to debug. So this is here in
1840 * case you're doing that.
1841 */
1842 if (dump_file) {
1843 brw_dump_compile(p, dump_file, 0, p->next_insn_offset);
1844 }
1845 }
1846
1847 const unsigned *
1848 fs_generator::generate_assembly(exec_list *simd8_instructions,
1849 exec_list *simd16_instructions,
1850 unsigned *assembly_size,
1851 FILE *dump_file)
1852 {
1853 assert(simd8_instructions || simd16_instructions);
1854
1855 if (simd8_instructions) {
1856 dispatch_width = 8;
1857 generate_code(simd8_instructions, dump_file);
1858 }
1859
1860 if (simd16_instructions) {
1861 /* We have to do a compaction pass now, or the one at the end of
1862 * execution will squash down where our prog_offset start needs
1863 * to be.
1864 */
1865 brw_compact_instructions(p);
1866
1867 /* align to 64 byte boundary. */
1868 while ((p->nr_insn * sizeof(struct brw_instruction)) % 64) {
1869 brw_NOP(p);
1870 }
1871
1872 /* Save off the start of this SIMD16 program */
1873 c->prog_data.prog_offset_16 = p->nr_insn * sizeof(struct brw_instruction);
1874
1875 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1876
1877 dispatch_width = 16;
1878 generate_code(simd16_instructions, dump_file);
1879 }
1880
1881 return brw_get_program(p, assembly_size);
1882 }