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[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 fs_generator::fs_generator(struct brw_context *brw,
40 void *mem_ctx,
41 const struct brw_wm_prog_key *key,
42 struct brw_wm_prog_data *prog_data,
43 struct gl_shader_program *shader_prog,
44 struct gl_fragment_program *fp,
45 bool runtime_check_aads_emit,
46 bool debug_flag)
47
48 : brw(brw), stage(MESA_SHADER_FRAGMENT), key(key),
49 prog_data(&prog_data->base), shader_prog(shader_prog),
50 prog(&fp->Base), runtime_check_aads_emit(runtime_check_aads_emit),
51 debug_flag(debug_flag), mem_ctx(mem_ctx)
52 {
53 ctx = &brw->ctx;
54
55 p = rzalloc(mem_ctx, struct brw_compile);
56 brw_init_compile(brw, p, mem_ctx);
57 }
58
59 fs_generator::~fs_generator()
60 {
61 }
62
63 bool
64 fs_generator::patch_discard_jumps_to_fb_writes()
65 {
66 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
67 return false;
68
69 int scale = brw_jump_scale(brw);
70
71 /* There is a somewhat strange undocumented requirement of using
72 * HALT, according to the simulator. If some channel has HALTed to
73 * a particular UIP, then by the end of the program, every channel
74 * must have HALTed to that UIP. Furthermore, the tracking is a
75 * stack, so you can't do the final halt of a UIP after starting
76 * halting to a new UIP.
77 *
78 * Symptoms of not emitting this instruction on actual hardware
79 * included GPU hangs and sparkly rendering on the piglit discard
80 * tests.
81 */
82 brw_inst *last_halt = gen6_HALT(p);
83 brw_inst_set_uip(brw, last_halt, 1 * scale);
84 brw_inst_set_jip(brw, last_halt, 1 * scale);
85
86 int ip = p->nr_insn;
87
88 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
89 brw_inst *patch = &p->store[patch_ip->ip];
90
91 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
92 /* HALT takes a half-instruction distance from the pre-incremented IP. */
93 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
94 }
95
96 this->discard_halt_patches.make_empty();
97 return true;
98 }
99
100 void
101 fs_generator::fire_fb_write(fs_inst *inst,
102 struct brw_reg payload,
103 struct brw_reg implied_header,
104 GLuint nr)
105 {
106 uint32_t msg_control;
107
108 assert(stage == MESA_SHADER_FRAGMENT);
109 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
110
111 if (brw->gen < 6) {
112 brw_push_insn_state(p);
113 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
114 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
115 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
116 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
117 brw_pop_insn_state(p);
118 }
119
120 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
121 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
122 else if (prog_data->dual_src_blend)
123 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
124 else if (dispatch_width == 16)
125 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
126 else
127 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
128
129 uint32_t surf_index =
130 prog_data->binding_table.render_target_start + inst->target;
131
132 brw_fb_WRITE(p,
133 dispatch_width,
134 payload,
135 implied_header,
136 msg_control,
137 surf_index,
138 nr,
139 0,
140 inst->eot,
141 inst->header_present);
142
143 brw_mark_surface_used(&prog_data->base, surf_index);
144 }
145
146 void
147 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
148 {
149 assert(stage == MESA_SHADER_FRAGMENT);
150 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
151 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
152 struct brw_reg implied_header;
153
154 if (inst->base_mrf >= 0)
155 payload = brw_message_reg(inst->base_mrf);
156
157 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
158 * move, here's g1.
159 */
160 if (inst->header_present) {
161 brw_push_insn_state(p);
162 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
163 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
164 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
165 brw_set_default_flag_reg(p, 0, 0);
166
167 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
168 * present.
169 */
170 if (prog_data->uses_kill || key->alpha_test_func) {
171 struct brw_reg pixel_mask;
172
173 if (brw->gen >= 6)
174 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
175 else
176 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
177
178 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
179 }
180
181 if (brw->gen >= 6) {
182 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
183 brw_MOV(p,
184 retype(payload, BRW_REGISTER_TYPE_UD),
185 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
186 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
187
188 if (inst->target > 0 && key->replicate_alpha) {
189 /* Set "Source0 Alpha Present to RenderTarget" bit in message
190 * header.
191 */
192 brw_OR(p,
193 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
194 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
195 brw_imm_ud(0x1 << 11));
196 }
197
198 if (inst->target > 0) {
199 /* Set the render target index for choosing BLEND_STATE. */
200 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
201 BRW_REGISTER_TYPE_UD),
202 brw_imm_ud(inst->target));
203 }
204
205 implied_header = brw_null_reg();
206 } else {
207 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
208 }
209
210 brw_pop_insn_state(p);
211 } else {
212 implied_header = brw_null_reg();
213 }
214
215 if (!runtime_check_aads_emit) {
216 fire_fb_write(inst, payload, implied_header, inst->mlen);
217 } else {
218 /* This can only happen in gen < 6 */
219 assert(brw->gen < 6);
220
221 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
222
223 /* Check runtime bit to detect if we have to send AA data or not */
224 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
225 brw_AND(p,
226 v1_null_ud,
227 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
228 brw_imm_ud(1<<26));
229 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
230
231 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
232 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
233 {
234 /* Don't send AA data */
235 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
236 }
237 brw_land_fwd_jump(p, jmp);
238 fire_fb_write(inst, payload, implied_header, inst->mlen);
239 }
240 }
241
242 void
243 fs_generator::generate_blorp_fb_write(fs_inst *inst)
244 {
245 brw_fb_WRITE(p,
246 16 /* dispatch_width */,
247 brw_message_reg(inst->base_mrf),
248 brw_reg_from_fs_reg(&inst->src[0]),
249 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
250 inst->target,
251 inst->mlen,
252 0,
253 true,
254 inst->header_present);
255 }
256
257 /* Computes the integer pixel x,y values from the origin.
258 *
259 * This is the basis of gl_FragCoord computation, but is also used
260 * pre-gen6 for computing the deltas from v0 for computing
261 * interpolation.
262 */
263 void
264 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
265 {
266 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
267 struct brw_reg src;
268 struct brw_reg deltas;
269
270 if (is_x) {
271 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
272 deltas = brw_imm_v(0x10101010);
273 } else {
274 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
275 deltas = brw_imm_v(0x11001100);
276 }
277
278 if (dispatch_width == 16) {
279 dst = vec16(dst);
280 }
281
282 /* We do this SIMD8 or SIMD16, but since the destination is UW we
283 * don't do compression in the SIMD16 case.
284 */
285 brw_push_insn_state(p);
286 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
287 brw_ADD(p, dst, src, deltas);
288 brw_pop_insn_state(p);
289 }
290
291 void
292 fs_generator::generate_linterp(fs_inst *inst,
293 struct brw_reg dst, struct brw_reg *src)
294 {
295 struct brw_reg delta_x = src[0];
296 struct brw_reg delta_y = src[1];
297 struct brw_reg interp = src[2];
298
299 if (brw->has_pln &&
300 delta_y.nr == delta_x.nr + 1 &&
301 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
302 brw_PLN(p, dst, interp, delta_x);
303 } else {
304 brw_LINE(p, brw_null_reg(), interp, delta_x);
305 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
306 }
307 }
308
309 void
310 fs_generator::generate_math_gen6(fs_inst *inst,
311 struct brw_reg dst,
312 struct brw_reg src0,
313 struct brw_reg src1)
314 {
315 int op = brw_math_function(inst->opcode);
316 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
317
318 if (dispatch_width == 8) {
319 gen6_math(p, dst, op, src0, src1);
320 } else if (dispatch_width == 16) {
321 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
322 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
323 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
324 gen6_math(p, sechalf(dst), op, sechalf(src0),
325 binop ? sechalf(src1) : brw_null_reg());
326 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
327 }
328 }
329
330 void
331 fs_generator::generate_math_gen4(fs_inst *inst,
332 struct brw_reg dst,
333 struct brw_reg src)
334 {
335 int op = brw_math_function(inst->opcode);
336
337 assert(inst->mlen >= 1);
338
339 if (dispatch_width == 8) {
340 gen4_math(p, dst,
341 op,
342 inst->base_mrf, src,
343 BRW_MATH_PRECISION_FULL);
344 } else if (dispatch_width == 16) {
345 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
346 gen4_math(p, firsthalf(dst),
347 op,
348 inst->base_mrf, firsthalf(src),
349 BRW_MATH_PRECISION_FULL);
350 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
351 gen4_math(p, sechalf(dst),
352 op,
353 inst->base_mrf + 1, sechalf(src),
354 BRW_MATH_PRECISION_FULL);
355
356 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
357 }
358 }
359
360 void
361 fs_generator::generate_math_g45(fs_inst *inst,
362 struct brw_reg dst,
363 struct brw_reg src)
364 {
365 if (inst->opcode == SHADER_OPCODE_POW ||
366 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
367 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
368 generate_math_gen4(inst, dst, src);
369 return;
370 }
371
372 int op = brw_math_function(inst->opcode);
373
374 assert(inst->mlen >= 1);
375
376 gen4_math(p, dst,
377 op,
378 inst->base_mrf, src,
379 BRW_MATH_PRECISION_FULL);
380 }
381
382 void
383 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
384 struct brw_reg sampler_index)
385 {
386 int msg_type = -1;
387 int rlen = 4;
388 uint32_t simd_mode;
389 uint32_t return_format;
390
391 switch (dst.type) {
392 case BRW_REGISTER_TYPE_D:
393 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
394 break;
395 case BRW_REGISTER_TYPE_UD:
396 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
397 break;
398 default:
399 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
400 break;
401 }
402
403 switch (inst->exec_size) {
404 case 8:
405 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
406 break;
407 case 16:
408 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
409 break;
410 default:
411 unreachable("Invalid width for texture instruction");
412 }
413
414 if (brw->gen >= 5) {
415 switch (inst->opcode) {
416 case SHADER_OPCODE_TEX:
417 if (inst->shadow_compare) {
418 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
419 } else {
420 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
421 }
422 break;
423 case FS_OPCODE_TXB:
424 if (inst->shadow_compare) {
425 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
426 } else {
427 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
428 }
429 break;
430 case SHADER_OPCODE_TXL:
431 if (inst->shadow_compare) {
432 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
433 } else {
434 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
435 }
436 break;
437 case SHADER_OPCODE_TXS:
438 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
439 break;
440 case SHADER_OPCODE_TXD:
441 if (inst->shadow_compare) {
442 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
443 assert(brw->gen >= 8 || brw->is_haswell);
444 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
445 } else {
446 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
447 }
448 break;
449 case SHADER_OPCODE_TXF:
450 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
451 break;
452 case SHADER_OPCODE_TXF_CMS:
453 if (brw->gen >= 7)
454 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
455 else
456 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
457 break;
458 case SHADER_OPCODE_TXF_UMS:
459 assert(brw->gen >= 7);
460 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
461 break;
462 case SHADER_OPCODE_TXF_MCS:
463 assert(brw->gen >= 7);
464 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
465 break;
466 case SHADER_OPCODE_LOD:
467 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
468 break;
469 case SHADER_OPCODE_TG4:
470 if (inst->shadow_compare) {
471 assert(brw->gen >= 7);
472 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
473 } else {
474 assert(brw->gen >= 6);
475 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
476 }
477 break;
478 case SHADER_OPCODE_TG4_OFFSET:
479 assert(brw->gen >= 7);
480 if (inst->shadow_compare) {
481 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
482 } else {
483 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
484 }
485 break;
486 default:
487 unreachable("not reached");
488 }
489 } else {
490 switch (inst->opcode) {
491 case SHADER_OPCODE_TEX:
492 /* Note that G45 and older determines shadow compare and dispatch width
493 * from message length for most messages.
494 */
495 assert(dispatch_width == 8);
496 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
497 if (inst->shadow_compare) {
498 assert(inst->mlen == 6);
499 } else {
500 assert(inst->mlen <= 4);
501 }
502 break;
503 case FS_OPCODE_TXB:
504 if (inst->shadow_compare) {
505 assert(inst->mlen == 6);
506 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
507 } else {
508 assert(inst->mlen == 9);
509 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
510 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
511 }
512 break;
513 case SHADER_OPCODE_TXL:
514 if (inst->shadow_compare) {
515 assert(inst->mlen == 6);
516 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
517 } else {
518 assert(inst->mlen == 9);
519 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
520 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
521 }
522 break;
523 case SHADER_OPCODE_TXD:
524 /* There is no sample_d_c message; comparisons are done manually */
525 assert(inst->mlen == 7 || inst->mlen == 10);
526 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
527 break;
528 case SHADER_OPCODE_TXF:
529 assert(inst->mlen == 9);
530 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
531 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
532 break;
533 case SHADER_OPCODE_TXS:
534 assert(inst->mlen == 3);
535 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
536 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
537 break;
538 default:
539 unreachable("not reached");
540 }
541 }
542 assert(msg_type != -1);
543
544 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
545 rlen = 8;
546 dst = vec16(dst);
547 }
548
549 assert(brw->gen < 7 || !inst->header_present ||
550 src.file == BRW_GENERAL_REGISTER_FILE);
551
552 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
553
554 /* Load the message header if present. If there's a texture offset,
555 * we need to set it up explicitly and load the offset bitfield.
556 * Otherwise, we can use an implied move from g0 to the first message reg.
557 */
558 if (inst->header_present) {
559 if (brw->gen < 6 && !inst->offset) {
560 /* Set up an implied move from g0 to the MRF. */
561 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
562 } else {
563 struct brw_reg header_reg;
564
565 if (brw->gen >= 7) {
566 header_reg = src;
567 } else {
568 assert(inst->base_mrf != -1);
569 header_reg = brw_message_reg(inst->base_mrf);
570 }
571
572 brw_push_insn_state(p);
573 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
574 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
575 /* Explicitly set up the message header by copying g0 to the MRF. */
576 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
577
578 if (inst->offset) {
579 /* Set the offset bits in DWord 2. */
580 brw_MOV(p, get_element_ud(header_reg, 2),
581 brw_imm_ud(inst->offset));
582 }
583
584 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index, dst);
585 brw_pop_insn_state(p);
586 }
587 }
588
589 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
590 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
591 ? prog_data->binding_table.gather_texture_start
592 : prog_data->binding_table.texture_start;
593
594 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
595 uint32_t sampler = sampler_index.dw1.ud;
596
597 brw_SAMPLE(p,
598 retype(dst, BRW_REGISTER_TYPE_UW),
599 inst->base_mrf,
600 src,
601 sampler + base_binding_table_index,
602 sampler % 16,
603 msg_type,
604 rlen,
605 inst->mlen,
606 inst->header_present,
607 simd_mode,
608 return_format);
609
610 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
611 } else {
612 /* Non-const sampler index */
613 /* Note: this clobbers `dst` as a temporary before emitting the send */
614
615 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
616 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
617
618 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
619
620 brw_push_insn_state(p);
621 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
622 brw_set_default_access_mode(p, BRW_ALIGN_1);
623
624 /* Some care required: `sampler` and `temp` may alias:
625 * addr = sampler & 0xff
626 * temp = (sampler << 8) & 0xf00
627 * addr = addr | temp
628 */
629 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
630 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
631 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
632 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
633 brw_OR(p, addr, addr, temp);
634
635 /* a0.0 |= <descriptor> */
636 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
637 brw_set_sampler_message(p, insn_or,
638 0 /* surface */,
639 0 /* sampler */,
640 msg_type,
641 rlen,
642 inst->mlen /* mlen */,
643 inst->header_present /* header */,
644 simd_mode,
645 return_format);
646 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
647 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
648 brw_set_src0(p, insn_or, addr);
649 brw_set_dest(p, insn_or, addr);
650
651
652 /* dst = send(offset, a0.0) */
653 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
654 brw_set_dest(p, insn_send, dst);
655 brw_set_src0(p, insn_send, src);
656 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
657
658 brw_pop_insn_state(p);
659
660 /* visitor knows more than we do about the surface limit required,
661 * so has already done marking.
662 */
663 }
664 }
665
666
667 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
668 * looking like:
669 *
670 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
671 *
672 * Ideally, we want to produce:
673 *
674 * DDX DDY
675 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
676 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
677 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
678 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
679 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
680 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
681 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
682 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
683 *
684 * and add another set of two more subspans if in 16-pixel dispatch mode.
685 *
686 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
687 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
688 * pair. But the ideal approximation may impose a huge performance cost on
689 * sample_d. On at least Haswell, sample_d instruction does some
690 * optimizations if the same LOD is used for all pixels in the subspan.
691 *
692 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
693 * appropriate swizzling.
694 */
695 void
696 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
697 struct brw_reg quality)
698 {
699 unsigned vstride, width;
700 assert(quality.file == BRW_IMMEDIATE_VALUE);
701 assert(quality.type == BRW_REGISTER_TYPE_D);
702
703 assert(stage == MESA_SHADER_FRAGMENT);
704 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
705
706 int quality_value = quality.dw1.d;
707
708 if (quality_value == BRW_DERIVATIVE_FINE ||
709 (key->high_quality_derivatives && quality_value != BRW_DERIVATIVE_COARSE)) {
710 /* produce accurate derivatives */
711 vstride = BRW_VERTICAL_STRIDE_2;
712 width = BRW_WIDTH_2;
713 }
714 else {
715 /* replicate the derivative at the top-left pixel to other pixels */
716 vstride = BRW_VERTICAL_STRIDE_4;
717 width = BRW_WIDTH_4;
718 }
719
720 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
721 BRW_REGISTER_TYPE_F,
722 vstride,
723 width,
724 BRW_HORIZONTAL_STRIDE_0,
725 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
726 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
727 BRW_REGISTER_TYPE_F,
728 vstride,
729 width,
730 BRW_HORIZONTAL_STRIDE_0,
731 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
732 brw_ADD(p, dst, src0, negate(src1));
733 }
734
735 /* The negate_value boolean is used to negate the derivative computation for
736 * FBOs, since they place the origin at the upper left instead of the lower
737 * left.
738 */
739 void
740 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
741 struct brw_reg quality, bool negate_value)
742 {
743 assert(quality.file == BRW_IMMEDIATE_VALUE);
744 assert(quality.type == BRW_REGISTER_TYPE_D);
745
746 assert(stage == MESA_SHADER_FRAGMENT);
747 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
748
749 int quality_value = quality.dw1.d;
750
751 if (quality_value == BRW_DERIVATIVE_FINE ||
752 (key->high_quality_derivatives && quality_value != BRW_DERIVATIVE_COARSE)) {
753 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
754 * Region Restrictions):
755 *
756 * In Align16 access mode, SIMD16 is not allowed for DW operations
757 * and SIMD8 is not allowed for DF operations.
758 *
759 * In this context, "DW operations" means "operations acting on 32-bit
760 * values", so it includes operations on floats.
761 *
762 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
763 * (Instruction Compression -> Rules and Restrictions):
764 *
765 * A compressed instruction must be in Align1 access mode. Align16
766 * mode instructions cannot be compressed.
767 *
768 * Similar text exists in the g45 PRM.
769 *
770 * On these platforms, if we're building a SIMD16 shader, we need to
771 * manually unroll to a pair of SIMD8 instructions.
772 */
773 bool unroll_to_simd8 =
774 (dispatch_width == 16 &&
775 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
776
777 /* produce accurate derivatives */
778 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
779 BRW_REGISTER_TYPE_F,
780 BRW_VERTICAL_STRIDE_4,
781 BRW_WIDTH_4,
782 BRW_HORIZONTAL_STRIDE_1,
783 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
784 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
785 BRW_REGISTER_TYPE_F,
786 BRW_VERTICAL_STRIDE_4,
787 BRW_WIDTH_4,
788 BRW_HORIZONTAL_STRIDE_1,
789 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
790 brw_push_insn_state(p);
791 brw_set_default_access_mode(p, BRW_ALIGN_16);
792 if (unroll_to_simd8) {
793 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
794 if (negate_value) {
795 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
796 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
797 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
798 } else {
799 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
800 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
801 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
802 }
803 } else {
804 if (negate_value)
805 brw_ADD(p, dst, src1, negate(src0));
806 else
807 brw_ADD(p, dst, src0, negate(src1));
808 }
809 brw_pop_insn_state(p);
810 } else {
811 /* replicate the derivative at the top-left pixel to other pixels */
812 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
813 BRW_REGISTER_TYPE_F,
814 BRW_VERTICAL_STRIDE_4,
815 BRW_WIDTH_4,
816 BRW_HORIZONTAL_STRIDE_0,
817 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
818 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
819 BRW_REGISTER_TYPE_F,
820 BRW_VERTICAL_STRIDE_4,
821 BRW_WIDTH_4,
822 BRW_HORIZONTAL_STRIDE_0,
823 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
824 if (negate_value)
825 brw_ADD(p, dst, src1, negate(src0));
826 else
827 brw_ADD(p, dst, src0, negate(src1));
828 }
829 }
830
831 void
832 fs_generator::generate_discard_jump(fs_inst *inst)
833 {
834 assert(brw->gen >= 6);
835
836 /* This HALT will be patched up at FB write time to point UIP at the end of
837 * the program, and at brw_uip_jip() JIP will be set to the end of the
838 * current block (or the program).
839 */
840 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
841
842 brw_push_insn_state(p);
843 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
844 gen6_HALT(p);
845 brw_pop_insn_state(p);
846 }
847
848 void
849 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
850 {
851 assert(inst->mlen != 0);
852
853 brw_MOV(p,
854 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
855 retype(src, BRW_REGISTER_TYPE_UD));
856 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
857 inst->exec_size / 8, inst->offset);
858 }
859
860 void
861 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
862 {
863 assert(inst->mlen != 0);
864
865 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
866 inst->exec_size / 8, inst->offset);
867 }
868
869 void
870 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
871 {
872 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
873 }
874
875 void
876 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
877 struct brw_reg dst,
878 struct brw_reg index,
879 struct brw_reg offset)
880 {
881 assert(inst->mlen != 0);
882
883 assert(index.file == BRW_IMMEDIATE_VALUE &&
884 index.type == BRW_REGISTER_TYPE_UD);
885 uint32_t surf_index = index.dw1.ud;
886
887 assert(offset.file == BRW_IMMEDIATE_VALUE &&
888 offset.type == BRW_REGISTER_TYPE_UD);
889 uint32_t read_offset = offset.dw1.ud;
890
891 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
892 read_offset, surf_index);
893
894 brw_mark_surface_used(prog_data, surf_index);
895 }
896
897 void
898 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
899 struct brw_reg dst,
900 struct brw_reg index,
901 struct brw_reg offset)
902 {
903 assert(inst->mlen == 0);
904 assert(index.type == BRW_REGISTER_TYPE_UD);
905
906 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
907 /* Reference just the dword we need, to avoid angering validate_reg(). */
908 offset = brw_vec1_grf(offset.nr, 0);
909
910 /* We use the SIMD4x2 mode because we want to end up with 4 components in
911 * the destination loaded consecutively from the same offset (which appears
912 * in the first component, and the rest are ignored).
913 */
914 dst.width = BRW_WIDTH_4;
915
916 if (index.file == BRW_IMMEDIATE_VALUE) {
917
918 uint32_t surf_index = index.dw1.ud;
919
920 brw_push_insn_state(p);
921 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
922 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
923 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
924 brw_pop_insn_state(p);
925
926 brw_set_dest(p, send, dst);
927 brw_set_src0(p, send, offset);
928 brw_set_sampler_message(p, send,
929 surf_index,
930 0, /* LD message ignores sampler unit */
931 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
932 1, /* rlen */
933 1, /* mlen */
934 false, /* no header */
935 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
936 0);
937
938 brw_mark_surface_used(prog_data, surf_index);
939
940 } else {
941
942 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
943
944 brw_push_insn_state(p);
945 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
946 brw_set_default_access_mode(p, BRW_ALIGN_1);
947
948 /* a0.0 = surf_index & 0xff */
949 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
950 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
951 brw_set_dest(p, insn_and, addr);
952 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
953 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
954
955
956 /* a0.0 |= <descriptor> */
957 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
958 brw_set_sampler_message(p, insn_or,
959 0 /* surface */,
960 0 /* sampler */,
961 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
962 1 /* rlen */,
963 1 /* mlen */,
964 false /* header */,
965 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
966 0);
967 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
968 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
969 brw_set_src0(p, insn_or, addr);
970 brw_set_dest(p, insn_or, addr);
971
972
973 /* dst = send(offset, a0.0) */
974 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
975 brw_set_dest(p, insn_send, dst);
976 brw_set_src0(p, insn_send, offset);
977 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
978
979 brw_pop_insn_state(p);
980
981 /* visitor knows more than we do about the surface limit required,
982 * so has already done marking.
983 */
984
985 }
986 }
987
988 void
989 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
990 struct brw_reg dst,
991 struct brw_reg index,
992 struct brw_reg offset)
993 {
994 assert(brw->gen < 7); /* Should use the gen7 variant. */
995 assert(inst->header_present);
996 assert(inst->mlen);
997
998 assert(index.file == BRW_IMMEDIATE_VALUE &&
999 index.type == BRW_REGISTER_TYPE_UD);
1000 uint32_t surf_index = index.dw1.ud;
1001
1002 uint32_t simd_mode, rlen, msg_type;
1003 if (dispatch_width == 16) {
1004 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1005 rlen = 8;
1006 } else {
1007 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1008 rlen = 4;
1009 }
1010
1011 if (brw->gen >= 5)
1012 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1013 else {
1014 /* We always use the SIMD16 message so that we only have to load U, and
1015 * not V or R.
1016 */
1017 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1018 assert(inst->mlen == 3);
1019 assert(inst->regs_written == 8);
1020 rlen = 8;
1021 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1022 }
1023
1024 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1025 BRW_REGISTER_TYPE_D);
1026 brw_MOV(p, offset_mrf, offset);
1027
1028 struct brw_reg header = brw_vec8_grf(0, 0);
1029 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1030
1031 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1032 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
1033 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1034 brw_set_src0(p, send, header);
1035 if (brw->gen < 6)
1036 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
1037
1038 /* Our surface is set up as floats, regardless of what actual data is
1039 * stored in it.
1040 */
1041 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1042 brw_set_sampler_message(p, send,
1043 surf_index,
1044 0, /* sampler (unused) */
1045 msg_type,
1046 rlen,
1047 inst->mlen,
1048 inst->header_present,
1049 simd_mode,
1050 return_format);
1051
1052 brw_mark_surface_used(prog_data, surf_index);
1053 }
1054
1055 void
1056 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1057 struct brw_reg dst,
1058 struct brw_reg index,
1059 struct brw_reg offset)
1060 {
1061 assert(brw->gen >= 7);
1062 /* Varying-offset pull constant loads are treated as a normal expression on
1063 * gen7, so the fact that it's a send message is hidden at the IR level.
1064 */
1065 assert(!inst->header_present);
1066 assert(!inst->mlen);
1067 assert(index.type == BRW_REGISTER_TYPE_UD);
1068
1069 uint32_t simd_mode, rlen, mlen;
1070 if (dispatch_width == 16) {
1071 mlen = 2;
1072 rlen = 8;
1073 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1074 } else {
1075 mlen = 1;
1076 rlen = 4;
1077 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1078 }
1079
1080 if (index.file == BRW_IMMEDIATE_VALUE) {
1081
1082 uint32_t surf_index = index.dw1.ud;
1083
1084 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1085 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1086 brw_set_src0(p, send, offset);
1087 brw_set_sampler_message(p, send,
1088 surf_index,
1089 0, /* LD message ignores sampler unit */
1090 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1091 rlen,
1092 mlen,
1093 false, /* no header */
1094 simd_mode,
1095 0);
1096
1097 brw_mark_surface_used(prog_data, surf_index);
1098
1099 } else {
1100
1101 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1102
1103 brw_push_insn_state(p);
1104 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1105 brw_set_default_access_mode(p, BRW_ALIGN_1);
1106
1107 /* a0.0 = surf_index & 0xff */
1108 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1109 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1110 brw_set_dest(p, insn_and, addr);
1111 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1112 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1113
1114
1115 /* a0.0 |= <descriptor> */
1116 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1117 brw_set_sampler_message(p, insn_or,
1118 0 /* surface */,
1119 0 /* sampler */,
1120 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1121 rlen /* rlen */,
1122 mlen /* mlen */,
1123 false /* header */,
1124 simd_mode,
1125 0);
1126 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1127 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1128 brw_set_src0(p, insn_or, addr);
1129 brw_set_dest(p, insn_or, addr);
1130
1131
1132 /* dst = send(offset, a0.0) */
1133 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1134 brw_set_dest(p, insn_send, retype(dst, BRW_REGISTER_TYPE_UW));
1135 brw_set_src0(p, insn_send, offset);
1136 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1137
1138 brw_pop_insn_state(p);
1139
1140 /* visitor knows more than we do about the surface limit required,
1141 * so has already done marking.
1142 */
1143 }
1144 }
1145
1146 /**
1147 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1148 * into the flags register (f0.0).
1149 *
1150 * Used only on Gen6 and above.
1151 */
1152 void
1153 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1154 {
1155 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1156 struct brw_reg dispatch_mask;
1157
1158 if (brw->gen >= 6)
1159 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1160 else
1161 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1162
1163 brw_push_insn_state(p);
1164 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1165 brw_MOV(p, flags, dispatch_mask);
1166 brw_pop_insn_state(p);
1167 }
1168
1169 void
1170 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1171 struct brw_reg dst,
1172 struct brw_reg src,
1173 struct brw_reg msg_data,
1174 unsigned msg_type)
1175 {
1176 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1177 msg_data.type == BRW_REGISTER_TYPE_UD);
1178
1179 brw_pixel_interpolator_query(p,
1180 retype(dst, BRW_REGISTER_TYPE_UW),
1181 src,
1182 inst->pi_noperspective,
1183 msg_type,
1184 msg_data.dw1.ud,
1185 inst->mlen,
1186 inst->regs_written);
1187 }
1188
1189
1190 static uint32_t brw_file_from_reg(fs_reg *reg)
1191 {
1192 switch (reg->file) {
1193 case GRF:
1194 return BRW_GENERAL_REGISTER_FILE;
1195 case MRF:
1196 return BRW_MESSAGE_REGISTER_FILE;
1197 case IMM:
1198 return BRW_IMMEDIATE_VALUE;
1199 default:
1200 unreachable("not reached");
1201 }
1202 }
1203
1204 struct brw_reg
1205 brw_reg_from_fs_reg(fs_reg *reg)
1206 {
1207 struct brw_reg brw_reg;
1208
1209 switch (reg->file) {
1210 case GRF:
1211 case MRF:
1212 if (reg->stride == 0) {
1213 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
1214 } else if (reg->width < 8) {
1215 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1216 brw_reg = stride(brw_reg, reg->width * reg->stride,
1217 reg->width, reg->stride);
1218 } else {
1219 /* From the Haswell PRM:
1220 *
1221 * VertStride must be used to cross GRF register boundaries. This
1222 * rule implies that elements within a 'Width' cannot cross GRF
1223 * boundaries.
1224 *
1225 * So, for registers with width > 8, we have to use a width of 8
1226 * and trust the compression state to sort out the exec size.
1227 */
1228 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1229 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
1230 }
1231
1232 brw_reg = retype(brw_reg, reg->type);
1233 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
1234 break;
1235 case IMM:
1236 switch (reg->type) {
1237 case BRW_REGISTER_TYPE_F:
1238 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
1239 break;
1240 case BRW_REGISTER_TYPE_D:
1241 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
1242 break;
1243 case BRW_REGISTER_TYPE_UD:
1244 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
1245 break;
1246 default:
1247 unreachable("not reached");
1248 }
1249 break;
1250 case HW_REG:
1251 assert(reg->type == reg->fixed_hw_reg.type);
1252 brw_reg = reg->fixed_hw_reg;
1253 break;
1254 case BAD_FILE:
1255 /* Probably unused. */
1256 brw_reg = brw_null_reg();
1257 break;
1258 case UNIFORM:
1259 unreachable("not reached");
1260 default:
1261 unreachable("not reached");
1262 }
1263 if (reg->abs)
1264 brw_reg = brw_abs(brw_reg);
1265 if (reg->negate)
1266 brw_reg = negate(brw_reg);
1267
1268 return brw_reg;
1269 }
1270
1271 /**
1272 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1273 * sampler LD messages.
1274 *
1275 * We don't want to bake it into the send message's code generation because
1276 * that means we don't get a chance to schedule the instructions.
1277 */
1278 void
1279 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1280 struct brw_reg dst,
1281 struct brw_reg value)
1282 {
1283 assert(value.file == BRW_IMMEDIATE_VALUE);
1284
1285 brw_push_insn_state(p);
1286 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1287 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1288 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1289 brw_pop_insn_state(p);
1290 }
1291
1292 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1293 * (when mask is passed as a uniform) of register mask before moving it
1294 * to register dst.
1295 */
1296 void
1297 fs_generator::generate_set_omask(fs_inst *inst,
1298 struct brw_reg dst,
1299 struct brw_reg mask)
1300 {
1301 bool stride_8_8_1 =
1302 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1303 mask.width == BRW_WIDTH_8 &&
1304 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1305
1306 bool stride_0_1_0 =
1307 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1308 mask.width == BRW_WIDTH_1 &&
1309 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1310
1311 assert(stride_8_8_1 || stride_0_1_0);
1312 assert(dst.type == BRW_REGISTER_TYPE_UW);
1313
1314 if (dispatch_width == 16)
1315 dst = vec16(dst);
1316 brw_push_insn_state(p);
1317 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1318 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1319
1320 if (stride_8_8_1) {
1321 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1322 } else if (stride_0_1_0) {
1323 brw_MOV(p, dst, retype(mask, dst.type));
1324 }
1325 brw_pop_insn_state(p);
1326 }
1327
1328 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1329 * the ADD instruction.
1330 */
1331 void
1332 fs_generator::generate_set_sample_id(fs_inst *inst,
1333 struct brw_reg dst,
1334 struct brw_reg src0,
1335 struct brw_reg src1)
1336 {
1337 assert(dst.type == BRW_REGISTER_TYPE_D ||
1338 dst.type == BRW_REGISTER_TYPE_UD);
1339 assert(src0.type == BRW_REGISTER_TYPE_D ||
1340 src0.type == BRW_REGISTER_TYPE_UD);
1341
1342 brw_push_insn_state(p);
1343 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1344 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1345 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1346 if (dispatch_width == 8) {
1347 brw_ADD(p, dst, src0, reg);
1348 } else if (dispatch_width == 16) {
1349 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1350 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1351 }
1352 brw_pop_insn_state(p);
1353 }
1354
1355 /**
1356 * Change the register's data type from UD to W, doubling the strides in order
1357 * to compensate for halving the data type width.
1358 */
1359 static struct brw_reg
1360 ud_reg_to_w(struct brw_reg r)
1361 {
1362 assert(r.type == BRW_REGISTER_TYPE_UD);
1363 r.type = BRW_REGISTER_TYPE_W;
1364
1365 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1366 * doubles the real stride.
1367 */
1368 if (r.hstride != 0)
1369 ++r.hstride;
1370 if (r.vstride != 0)
1371 ++r.vstride;
1372
1373 return r;
1374 }
1375
1376 void
1377 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1378 struct brw_reg dst,
1379 struct brw_reg x,
1380 struct brw_reg y)
1381 {
1382 assert(brw->gen >= 7);
1383 assert(dst.type == BRW_REGISTER_TYPE_UD);
1384 assert(x.type == BRW_REGISTER_TYPE_F);
1385 assert(y.type == BRW_REGISTER_TYPE_F);
1386
1387 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1388 *
1389 * Because this instruction does not have a 16-bit floating-point type,
1390 * the destination data type must be Word (W).
1391 *
1392 * The destination must be DWord-aligned and specify a horizontal stride
1393 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1394 * each destination channel and the upper word is not modified.
1395 */
1396 struct brw_reg dst_w = ud_reg_to_w(dst);
1397
1398 /* Give each 32-bit channel of dst the form below , where "." means
1399 * unchanged.
1400 * 0x....hhhh
1401 */
1402 brw_F32TO16(p, dst_w, y);
1403
1404 /* Now the form:
1405 * 0xhhhh0000
1406 */
1407 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1408
1409 /* And, finally the form of packHalf2x16's output:
1410 * 0xhhhhllll
1411 */
1412 brw_F32TO16(p, dst_w, x);
1413 }
1414
1415 void
1416 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1417 struct brw_reg dst,
1418 struct brw_reg src)
1419 {
1420 assert(brw->gen >= 7);
1421 assert(dst.type == BRW_REGISTER_TYPE_F);
1422 assert(src.type == BRW_REGISTER_TYPE_UD);
1423
1424 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1425 *
1426 * Because this instruction does not have a 16-bit floating-point type,
1427 * the source data type must be Word (W). The destination type must be
1428 * F (Float).
1429 */
1430 struct brw_reg src_w = ud_reg_to_w(src);
1431
1432 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1433 * For the Y case, we wish to access only the upper word; therefore
1434 * a 16-bit subregister offset is needed.
1435 */
1436 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1437 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1438 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1439 src_w.subnr += 2;
1440
1441 brw_F16TO32(p, dst, src_w);
1442 }
1443
1444 void
1445 fs_generator::generate_shader_time_add(fs_inst *inst,
1446 struct brw_reg payload,
1447 struct brw_reg offset,
1448 struct brw_reg value)
1449 {
1450 assert(brw->gen >= 7);
1451 brw_push_insn_state(p);
1452 brw_set_default_mask_control(p, true);
1453
1454 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1455 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1456 offset.type);
1457 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1458 value.type);
1459
1460 assert(offset.file == BRW_IMMEDIATE_VALUE);
1461 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1462 value.width = BRW_WIDTH_1;
1463 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1464 value.vstride = BRW_VERTICAL_STRIDE_0;
1465 } else {
1466 assert(value.file == BRW_IMMEDIATE_VALUE);
1467 }
1468
1469 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1470 * case, and we don't really care about squeezing every bit of performance
1471 * out of this path, so we just emit the MOVs from here.
1472 */
1473 brw_MOV(p, payload_offset, offset);
1474 brw_MOV(p, payload_value, value);
1475 brw_shader_time_add(p, payload,
1476 prog_data->binding_table.shader_time_start);
1477 brw_pop_insn_state(p);
1478
1479 brw_mark_surface_used(prog_data,
1480 prog_data->binding_table.shader_time_start);
1481 }
1482
1483 void
1484 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1485 struct brw_reg payload,
1486 struct brw_reg atomic_op,
1487 struct brw_reg surf_index)
1488 {
1489 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1490 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1491 surf_index.file == BRW_IMMEDIATE_VALUE &&
1492 surf_index.type == BRW_REGISTER_TYPE_UD);
1493
1494 brw_untyped_atomic(p, dst, payload, atomic_op.dw1.ud, surf_index.dw1.ud,
1495 inst->mlen, inst->exec_size / 8);
1496
1497 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1498 }
1499
1500 void
1501 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1502 struct brw_reg payload,
1503 struct brw_reg surf_index)
1504 {
1505 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1506 surf_index.type == BRW_REGISTER_TYPE_UD);
1507
1508 brw_untyped_surface_read(p, dst, payload,
1509 surf_index.dw1.ud,
1510 inst->mlen, inst->exec_size / 8);
1511
1512 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1513 }
1514
1515 int
1516 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1517 {
1518 /* align to 64 byte boundary. */
1519 while (p->next_insn_offset % 64)
1520 brw_NOP(p);
1521
1522 this->dispatch_width = dispatch_width;
1523 if (dispatch_width == 16)
1524 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1525
1526 int start_offset = p->next_insn_offset;
1527 int loop_count = 0;
1528
1529 struct annotation_info annotation;
1530 memset(&annotation, 0, sizeof(annotation));
1531
1532 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1533 struct brw_reg src[3], dst;
1534 unsigned int last_insn_offset = p->next_insn_offset;
1535
1536 if (unlikely(debug_flag))
1537 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1538
1539 for (unsigned int i = 0; i < inst->sources; i++) {
1540 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1541
1542 /* The accumulator result appears to get used for the
1543 * conditional modifier generation. When negating a UD
1544 * value, there is a 33rd bit generated for the sign in the
1545 * accumulator value, so now you can't check, for example,
1546 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1547 */
1548 assert(!inst->conditional_mod ||
1549 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1550 !inst->src[i].negate);
1551 }
1552 dst = brw_reg_from_fs_reg(&inst->dst);
1553
1554 brw_set_default_predicate_control(p, inst->predicate);
1555 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1556 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1557 brw_set_default_saturate(p, inst->saturate);
1558 brw_set_default_mask_control(p, inst->force_writemask_all);
1559 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1560
1561 switch (inst->exec_size) {
1562 case 1:
1563 case 2:
1564 case 4:
1565 assert(inst->force_writemask_all);
1566 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1567 break;
1568 case 8:
1569 if (inst->force_sechalf) {
1570 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1571 } else {
1572 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1573 }
1574 break;
1575 case 16:
1576 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1577 break;
1578 default:
1579 unreachable(!"Invalid instruction width");
1580 }
1581
1582 switch (inst->opcode) {
1583 case BRW_OPCODE_MOV:
1584 brw_MOV(p, dst, src[0]);
1585 break;
1586 case BRW_OPCODE_ADD:
1587 brw_ADD(p, dst, src[0], src[1]);
1588 break;
1589 case BRW_OPCODE_MUL:
1590 brw_MUL(p, dst, src[0], src[1]);
1591 break;
1592 case BRW_OPCODE_AVG:
1593 brw_AVG(p, dst, src[0], src[1]);
1594 break;
1595 case BRW_OPCODE_MACH:
1596 brw_MACH(p, dst, src[0], src[1]);
1597 break;
1598
1599 case BRW_OPCODE_MAD:
1600 assert(brw->gen >= 6);
1601 brw_set_default_access_mode(p, BRW_ALIGN_16);
1602 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1603 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1604 brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1605 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1606 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1607 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1608 } else {
1609 brw_MAD(p, dst, src[0], src[1], src[2]);
1610 }
1611 brw_set_default_access_mode(p, BRW_ALIGN_1);
1612 break;
1613
1614 case BRW_OPCODE_LRP:
1615 assert(brw->gen >= 6);
1616 brw_set_default_access_mode(p, BRW_ALIGN_16);
1617 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1618 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1619 brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1620 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1621 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1622 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1623 } else {
1624 brw_LRP(p, dst, src[0], src[1], src[2]);
1625 }
1626 brw_set_default_access_mode(p, BRW_ALIGN_1);
1627 break;
1628
1629 case BRW_OPCODE_FRC:
1630 brw_FRC(p, dst, src[0]);
1631 break;
1632 case BRW_OPCODE_RNDD:
1633 brw_RNDD(p, dst, src[0]);
1634 break;
1635 case BRW_OPCODE_RNDE:
1636 brw_RNDE(p, dst, src[0]);
1637 break;
1638 case BRW_OPCODE_RNDZ:
1639 brw_RNDZ(p, dst, src[0]);
1640 break;
1641
1642 case BRW_OPCODE_AND:
1643 brw_AND(p, dst, src[0], src[1]);
1644 break;
1645 case BRW_OPCODE_OR:
1646 brw_OR(p, dst, src[0], src[1]);
1647 break;
1648 case BRW_OPCODE_XOR:
1649 brw_XOR(p, dst, src[0], src[1]);
1650 break;
1651 case BRW_OPCODE_NOT:
1652 brw_NOT(p, dst, src[0]);
1653 break;
1654 case BRW_OPCODE_ASR:
1655 brw_ASR(p, dst, src[0], src[1]);
1656 break;
1657 case BRW_OPCODE_SHR:
1658 brw_SHR(p, dst, src[0], src[1]);
1659 break;
1660 case BRW_OPCODE_SHL:
1661 brw_SHL(p, dst, src[0], src[1]);
1662 break;
1663 case BRW_OPCODE_F32TO16:
1664 assert(brw->gen >= 7);
1665 brw_F32TO16(p, dst, src[0]);
1666 break;
1667 case BRW_OPCODE_F16TO32:
1668 assert(brw->gen >= 7);
1669 brw_F16TO32(p, dst, src[0]);
1670 break;
1671 case BRW_OPCODE_CMP:
1672 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1673 break;
1674 case BRW_OPCODE_SEL:
1675 brw_SEL(p, dst, src[0], src[1]);
1676 break;
1677 case BRW_OPCODE_BFREV:
1678 assert(brw->gen >= 7);
1679 /* BFREV only supports UD type for src and dst. */
1680 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1681 retype(src[0], BRW_REGISTER_TYPE_UD));
1682 break;
1683 case BRW_OPCODE_FBH:
1684 assert(brw->gen >= 7);
1685 /* FBH only supports UD type for dst. */
1686 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1687 break;
1688 case BRW_OPCODE_FBL:
1689 assert(brw->gen >= 7);
1690 /* FBL only supports UD type for dst. */
1691 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1692 break;
1693 case BRW_OPCODE_CBIT:
1694 assert(brw->gen >= 7);
1695 /* CBIT only supports UD type for dst. */
1696 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1697 break;
1698 case BRW_OPCODE_ADDC:
1699 assert(brw->gen >= 7);
1700 brw_ADDC(p, dst, src[0], src[1]);
1701 break;
1702 case BRW_OPCODE_SUBB:
1703 assert(brw->gen >= 7);
1704 brw_SUBB(p, dst, src[0], src[1]);
1705 break;
1706 case BRW_OPCODE_MAC:
1707 brw_MAC(p, dst, src[0], src[1]);
1708 break;
1709
1710 case BRW_OPCODE_BFE:
1711 assert(brw->gen >= 7);
1712 brw_set_default_access_mode(p, BRW_ALIGN_16);
1713 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1714 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1715 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1716 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1717 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1718 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1719 } else {
1720 brw_BFE(p, dst, src[0], src[1], src[2]);
1721 }
1722 brw_set_default_access_mode(p, BRW_ALIGN_1);
1723 break;
1724
1725 case BRW_OPCODE_BFI1:
1726 assert(brw->gen >= 7);
1727 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1728 * should
1729 *
1730 * "Force BFI instructions to be executed always in SIMD8."
1731 */
1732 if (dispatch_width == 16 && brw->is_haswell) {
1733 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1734 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1735 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1736 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1737 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1738 } else {
1739 brw_BFI1(p, dst, src[0], src[1]);
1740 }
1741 break;
1742 case BRW_OPCODE_BFI2:
1743 assert(brw->gen >= 7);
1744 brw_set_default_access_mode(p, BRW_ALIGN_16);
1745 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1746 * should
1747 *
1748 * "Force BFI instructions to be executed always in SIMD8."
1749 *
1750 * Otherwise we would be able to emit compressed instructions like we
1751 * do for the other three-source instructions.
1752 */
1753 if (dispatch_width == 16 && brw->gen < 8) {
1754 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1755 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1756 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1757 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1758 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1759 } else {
1760 brw_BFI2(p, dst, src[0], src[1], src[2]);
1761 }
1762 brw_set_default_access_mode(p, BRW_ALIGN_1);
1763 break;
1764
1765 case BRW_OPCODE_IF:
1766 if (inst->src[0].file != BAD_FILE) {
1767 /* The instruction has an embedded compare (only allowed on gen6) */
1768 assert(brw->gen == 6);
1769 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1770 } else {
1771 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1772 }
1773 break;
1774
1775 case BRW_OPCODE_ELSE:
1776 brw_ELSE(p);
1777 break;
1778 case BRW_OPCODE_ENDIF:
1779 brw_ENDIF(p);
1780 break;
1781
1782 case BRW_OPCODE_DO:
1783 brw_DO(p, BRW_EXECUTE_8);
1784 break;
1785
1786 case BRW_OPCODE_BREAK:
1787 brw_BREAK(p);
1788 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1789 break;
1790 case BRW_OPCODE_CONTINUE:
1791 brw_CONT(p);
1792 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1793 break;
1794
1795 case BRW_OPCODE_WHILE:
1796 brw_WHILE(p);
1797 loop_count++;
1798 break;
1799
1800 case SHADER_OPCODE_RCP:
1801 case SHADER_OPCODE_RSQ:
1802 case SHADER_OPCODE_SQRT:
1803 case SHADER_OPCODE_EXP2:
1804 case SHADER_OPCODE_LOG2:
1805 case SHADER_OPCODE_SIN:
1806 case SHADER_OPCODE_COS:
1807 assert(brw->gen < 6 || inst->mlen == 0);
1808 if (brw->gen >= 7) {
1809 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1810 brw_null_reg());
1811 } else if (brw->gen == 6) {
1812 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1813 } else if (brw->gen == 5 || brw->is_g4x) {
1814 generate_math_g45(inst, dst, src[0]);
1815 } else {
1816 generate_math_gen4(inst, dst, src[0]);
1817 }
1818 break;
1819 case SHADER_OPCODE_INT_QUOTIENT:
1820 case SHADER_OPCODE_INT_REMAINDER:
1821 case SHADER_OPCODE_POW:
1822 assert(brw->gen < 6 || inst->mlen == 0);
1823 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1824 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1825 } else if (brw->gen >= 6) {
1826 generate_math_gen6(inst, dst, src[0], src[1]);
1827 } else {
1828 generate_math_gen4(inst, dst, src[0]);
1829 }
1830 break;
1831 case FS_OPCODE_PIXEL_X:
1832 generate_pixel_xy(dst, true);
1833 break;
1834 case FS_OPCODE_PIXEL_Y:
1835 generate_pixel_xy(dst, false);
1836 break;
1837 case FS_OPCODE_CINTERP:
1838 brw_MOV(p, dst, src[0]);
1839 break;
1840 case FS_OPCODE_LINTERP:
1841 generate_linterp(inst, dst, src);
1842 break;
1843 case SHADER_OPCODE_TEX:
1844 case FS_OPCODE_TXB:
1845 case SHADER_OPCODE_TXD:
1846 case SHADER_OPCODE_TXF:
1847 case SHADER_OPCODE_TXF_CMS:
1848 case SHADER_OPCODE_TXF_UMS:
1849 case SHADER_OPCODE_TXF_MCS:
1850 case SHADER_OPCODE_TXL:
1851 case SHADER_OPCODE_TXS:
1852 case SHADER_OPCODE_LOD:
1853 case SHADER_OPCODE_TG4:
1854 case SHADER_OPCODE_TG4_OFFSET:
1855 generate_tex(inst, dst, src[0], src[1]);
1856 break;
1857 case FS_OPCODE_DDX:
1858 generate_ddx(inst, dst, src[0], src[1]);
1859 break;
1860 case FS_OPCODE_DDY:
1861 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1862 * guarantee that key->render_to_fbo is set).
1863 */
1864 assert(stage == MESA_SHADER_FRAGMENT &&
1865 ((gl_fragment_program *) prog)->UsesDFdy);
1866 generate_ddy(inst, dst, src[0], src[1],
1867 ((brw_wm_prog_key * const) this->key)->render_to_fbo);
1868 break;
1869
1870 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1871 generate_scratch_write(inst, src[0]);
1872 break;
1873
1874 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1875 generate_scratch_read(inst, dst);
1876 break;
1877
1878 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1879 generate_scratch_read_gen7(inst, dst);
1880 break;
1881
1882 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1883 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1884 break;
1885
1886 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1887 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1888 break;
1889
1890 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1891 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1892 break;
1893
1894 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1895 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1896 break;
1897
1898 case FS_OPCODE_REP_FB_WRITE:
1899 case FS_OPCODE_FB_WRITE:
1900 generate_fb_write(inst, src[0]);
1901 break;
1902
1903 case FS_OPCODE_BLORP_FB_WRITE:
1904 generate_blorp_fb_write(inst);
1905 break;
1906
1907 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1908 generate_mov_dispatch_to_flags(inst);
1909 break;
1910
1911 case FS_OPCODE_DISCARD_JUMP:
1912 generate_discard_jump(inst);
1913 break;
1914
1915 case SHADER_OPCODE_SHADER_TIME_ADD:
1916 generate_shader_time_add(inst, src[0], src[1], src[2]);
1917 break;
1918
1919 case SHADER_OPCODE_UNTYPED_ATOMIC:
1920 generate_untyped_atomic(inst, dst, src[0], src[1], src[2]);
1921 break;
1922
1923 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1924 generate_untyped_surface_read(inst, dst, src[0], src[1]);
1925 break;
1926
1927 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1928 generate_set_simd4x2_offset(inst, dst, src[0]);
1929 break;
1930
1931 case FS_OPCODE_SET_OMASK:
1932 generate_set_omask(inst, dst, src[0]);
1933 break;
1934
1935 case FS_OPCODE_SET_SAMPLE_ID:
1936 generate_set_sample_id(inst, dst, src[0], src[1]);
1937 break;
1938
1939 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1940 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1941 break;
1942
1943 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1944 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1945 generate_unpack_half_2x16_split(inst, dst, src[0]);
1946 break;
1947
1948 case FS_OPCODE_PLACEHOLDER_HALT:
1949 /* This is the place where the final HALT needs to be inserted if
1950 * we've emitted any discards. If not, this will emit no code.
1951 */
1952 if (!patch_discard_jumps_to_fb_writes()) {
1953 if (unlikely(debug_flag)) {
1954 annotation.ann_count--;
1955 }
1956 }
1957 break;
1958
1959 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
1960 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1961 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
1962 break;
1963
1964 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
1965 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1966 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
1967 break;
1968
1969 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
1970 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1971 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
1972 break;
1973
1974 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
1975 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1976 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
1977 break;
1978
1979 default:
1980 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1981 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1982 opcode_descs[inst->opcode].name);
1983 } else {
1984 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1985 }
1986 abort();
1987
1988 case SHADER_OPCODE_LOAD_PAYLOAD:
1989 unreachable("Should be lowered by lower_load_payload()");
1990 }
1991
1992 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1993 assert(p->next_insn_offset == last_insn_offset + 16 ||
1994 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1995 "emitting more than 1 instruction");
1996
1997 brw_inst *last = &p->store[last_insn_offset / 16];
1998
1999 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
2000 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
2001 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
2002 }
2003 }
2004
2005 brw_set_uip_jip(p);
2006 annotation_finalize(&annotation, p->next_insn_offset);
2007
2008 int before_size = p->next_insn_offset - start_offset;
2009 brw_compact_instructions(p, start_offset, annotation.ann_count,
2010 annotation.ann);
2011 int after_size = p->next_insn_offset - start_offset;
2012
2013 if (unlikely(debug_flag)) {
2014 if (shader_prog) {
2015 fprintf(stderr,
2016 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
2017 shader_prog->Label ? shader_prog->Label : "unnamed",
2018 shader_prog->Name, dispatch_width);
2019 } else if (prog) {
2020 fprintf(stderr,
2021 "Native code for fragment program %d (SIMD%d dispatch):\n",
2022 prog->Id, dispatch_width);
2023 } else {
2024 fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
2025 dispatch_width);
2026 }
2027 fprintf(stderr, "SIMD%d shader: %d instructions. %d loops. Compacted %d to %d"
2028 " bytes (%.0f%%)\n",
2029 dispatch_width, before_size / 16, loop_count, before_size, after_size,
2030 100.0f * (before_size - after_size) / before_size);
2031
2032 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
2033 ralloc_free(annotation.ann);
2034 }
2035
2036 return start_offset;
2037 }
2038
2039 const unsigned *
2040 fs_generator::get_assembly(unsigned int *assembly_size)
2041 {
2042 return brw_get_program(p, assembly_size);
2043 }