projects / mesa.git / blob
? search:


47fcf126b3b1999803ca6374fbdc465176ea5483
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 static struct brw_reg
40 brw_reg_from_fs_reg(fs_reg *reg)
41 {
42 struct brw_reg brw_reg;
43
44 switch (reg->file) {
45 case GRF:
46 case MRF:
47 if (reg->stride == 0) {
48 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
49 } else if (reg->width < 8) {
50 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
51 brw_reg = stride(brw_reg, reg->width * reg->stride,
52 reg->width, reg->stride);
53 } else {
54 /* From the Haswell PRM:
55 *
56 * VertStride must be used to cross GRF register boundaries. This
57 * rule implies that elements within a 'Width' cannot cross GRF
58 * boundaries.
59 *
60 * So, for registers with width > 8, we have to use a width of 8
61 * and trust the compression state to sort out the exec size.
62 */
63 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
64 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
65 }
66
67 brw_reg = retype(brw_reg, reg->type);
68 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
69 break;
70 case IMM:
71 switch (reg->type) {
72 case BRW_REGISTER_TYPE_F:
73 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
74 break;
75 case BRW_REGISTER_TYPE_D:
76 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
77 break;
78 case BRW_REGISTER_TYPE_UD:
79 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
80 break;
81 case BRW_REGISTER_TYPE_VF:
82 brw_reg = brw_imm_vf(reg->fixed_hw_reg.dw1.ud);
83 break;
84 default:
85 unreachable("not reached");
86 }
87 break;
88 case HW_REG:
89 assert(reg->type == reg->fixed_hw_reg.type);
90 brw_reg = reg->fixed_hw_reg;
91 break;
92 case BAD_FILE:
93 /* Probably unused. */
94 brw_reg = brw_null_reg();
95 break;
96 case UNIFORM:
97 unreachable("not reached");
98 default:
99 unreachable("not reached");
100 }
101 if (reg->abs)
102 brw_reg = brw_abs(brw_reg);
103 if (reg->negate)
104 brw_reg = negate(brw_reg);
105
106 return brw_reg;
107 }
108
109 fs_generator::fs_generator(struct brw_context *brw,
110 void *mem_ctx,
111 const struct brw_wm_prog_key *key,
112 struct brw_wm_prog_data *prog_data,
113 struct gl_shader_program *shader_prog,
114 struct gl_fragment_program *fp,
115 bool runtime_check_aads_emit,
116 bool debug_flag)
117
118 : brw(brw), stage(MESA_SHADER_FRAGMENT), key(key),
119 prog_data(&prog_data->base), shader_prog(shader_prog),
120 prog(&fp->Base), runtime_check_aads_emit(runtime_check_aads_emit),
121 debug_flag(debug_flag), mem_ctx(mem_ctx)
122 {
123 ctx = &brw->ctx;
124
125 p = rzalloc(mem_ctx, struct brw_compile);
126 brw_init_compile(brw, p, mem_ctx);
127 }
128
129 fs_generator::~fs_generator()
130 {
131 }
132
133 class ip_record : public exec_node {
134 public:
135 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
136
137 ip_record(int ip)
138 {
139 this->ip = ip;
140 }
141
142 int ip;
143 };
144
145 bool
146 fs_generator::patch_discard_jumps_to_fb_writes()
147 {
148 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
149 return false;
150
151 int scale = brw_jump_scale(brw);
152
153 /* There is a somewhat strange undocumented requirement of using
154 * HALT, according to the simulator. If some channel has HALTed to
155 * a particular UIP, then by the end of the program, every channel
156 * must have HALTed to that UIP. Furthermore, the tracking is a
157 * stack, so you can't do the final halt of a UIP after starting
158 * halting to a new UIP.
159 *
160 * Symptoms of not emitting this instruction on actual hardware
161 * included GPU hangs and sparkly rendering on the piglit discard
162 * tests.
163 */
164 brw_inst *last_halt = gen6_HALT(p);
165 brw_inst_set_uip(brw, last_halt, 1 * scale);
166 brw_inst_set_jip(brw, last_halt, 1 * scale);
167
168 int ip = p->nr_insn;
169
170 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
171 brw_inst *patch = &p->store[patch_ip->ip];
172
173 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
174 /* HALT takes a half-instruction distance from the pre-incremented IP. */
175 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
176 }
177
178 this->discard_halt_patches.make_empty();
179 return true;
180 }
181
182 void
183 fs_generator::fire_fb_write(fs_inst *inst,
184 struct brw_reg payload,
185 struct brw_reg implied_header,
186 GLuint nr)
187 {
188 uint32_t msg_control;
189
190 assert(stage == MESA_SHADER_FRAGMENT);
191 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
192
193 if (brw->gen < 6) {
194 brw_push_insn_state(p);
195 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
196 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
197 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
198 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
199 brw_pop_insn_state(p);
200 }
201
202 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
203 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
204 else if (prog_data->dual_src_blend)
205 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
206 else if (dispatch_width == 16)
207 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
208 else
209 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
210
211 uint32_t surf_index =
212 prog_data->binding_table.render_target_start + inst->target;
213
214 brw_fb_WRITE(p,
215 dispatch_width,
216 payload,
217 implied_header,
218 msg_control,
219 surf_index,
220 nr,
221 0,
222 inst->eot,
223 inst->header_present);
224
225 brw_mark_surface_used(&prog_data->base, surf_index);
226 }
227
228 void
229 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
230 {
231 assert(stage == MESA_SHADER_FRAGMENT);
232 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
233 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
234 struct brw_reg implied_header;
235
236 if (brw->gen < 8 && !brw->is_haswell) {
237 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
238 }
239
240 if (inst->base_mrf >= 0)
241 payload = brw_message_reg(inst->base_mrf);
242
243 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
244 * move, here's g1.
245 */
246 if (inst->header_present) {
247 brw_push_insn_state(p);
248 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
249 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
250 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
251 brw_set_default_flag_reg(p, 0, 0);
252
253 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
254 * present.
255 */
256 if (prog_data->uses_kill) {
257 struct brw_reg pixel_mask;
258
259 if (brw->gen >= 6)
260 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
261 else
262 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
263
264 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
265 }
266
267 if (brw->gen >= 6) {
268 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
269 brw_MOV(p,
270 retype(payload, BRW_REGISTER_TYPE_UD),
271 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
272 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
273
274 if (inst->target > 0 && key->replicate_alpha) {
275 /* Set "Source0 Alpha Present to RenderTarget" bit in message
276 * header.
277 */
278 brw_OR(p,
279 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
280 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
281 brw_imm_ud(0x1 << 11));
282 }
283
284 if (inst->target > 0) {
285 /* Set the render target index for choosing BLEND_STATE. */
286 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
287 BRW_REGISTER_TYPE_UD),
288 brw_imm_ud(inst->target));
289 }
290
291 implied_header = brw_null_reg();
292 } else {
293 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
294 }
295
296 brw_pop_insn_state(p);
297 } else {
298 implied_header = brw_null_reg();
299 }
300
301 if (!runtime_check_aads_emit) {
302 fire_fb_write(inst, payload, implied_header, inst->mlen);
303 } else {
304 /* This can only happen in gen < 6 */
305 assert(brw->gen < 6);
306
307 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
308
309 /* Check runtime bit to detect if we have to send AA data or not */
310 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
311 brw_AND(p,
312 v1_null_ud,
313 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
314 brw_imm_ud(1<<26));
315 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
316
317 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
318 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
319 {
320 /* Don't send AA data */
321 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
322 }
323 brw_land_fwd_jump(p, jmp);
324 fire_fb_write(inst, payload, implied_header, inst->mlen);
325 }
326 }
327
328 void
329 fs_generator::generate_blorp_fb_write(fs_inst *inst)
330 {
331 brw_fb_WRITE(p,
332 16 /* dispatch_width */,
333 brw_message_reg(inst->base_mrf),
334 brw_reg_from_fs_reg(&inst->src[0]),
335 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
336 inst->target,
337 inst->mlen,
338 0,
339 true,
340 inst->header_present);
341 }
342
343 /* Computes the integer pixel x,y values from the origin.
344 *
345 * This is the basis of gl_FragCoord computation, but is also used
346 * pre-gen6 for computing the deltas from v0 for computing
347 * interpolation.
348 */
349 void
350 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
351 {
352 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
353 struct brw_reg src;
354 struct brw_reg deltas;
355
356 if (is_x) {
357 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
358 deltas = brw_imm_v(0x10101010);
359 } else {
360 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
361 deltas = brw_imm_v(0x11001100);
362 }
363
364 if (dispatch_width == 16) {
365 dst = vec16(dst);
366 }
367
368 /* We do this SIMD8 or SIMD16, but since the destination is UW we
369 * don't do compression in the SIMD16 case.
370 */
371 brw_push_insn_state(p);
372 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
373 brw_ADD(p, dst, src, deltas);
374 brw_pop_insn_state(p);
375 }
376
377 void
378 fs_generator::generate_linterp(fs_inst *inst,
379 struct brw_reg dst, struct brw_reg *src)
380 {
381 struct brw_reg delta_x = src[0];
382 struct brw_reg delta_y = src[1];
383 struct brw_reg interp = src[2];
384
385 if (brw->has_pln &&
386 delta_y.nr == delta_x.nr + 1 &&
387 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
388 brw_PLN(p, dst, interp, delta_x);
389 } else {
390 brw_LINE(p, brw_null_reg(), interp, delta_x);
391 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
392 }
393 }
394
395 void
396 fs_generator::generate_math_gen6(fs_inst *inst,
397 struct brw_reg dst,
398 struct brw_reg src0,
399 struct brw_reg src1)
400 {
401 int op = brw_math_function(inst->opcode);
402 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
403
404 if (dispatch_width == 8) {
405 gen6_math(p, dst, op, src0, src1);
406 } else if (dispatch_width == 16) {
407 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
408 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
409 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
410 gen6_math(p, sechalf(dst), op, sechalf(src0),
411 binop ? sechalf(src1) : brw_null_reg());
412 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
413 }
414 }
415
416 void
417 fs_generator::generate_math_gen4(fs_inst *inst,
418 struct brw_reg dst,
419 struct brw_reg src)
420 {
421 int op = brw_math_function(inst->opcode);
422
423 assert(inst->mlen >= 1);
424
425 if (dispatch_width == 8) {
426 gen4_math(p, dst,
427 op,
428 inst->base_mrf, src,
429 BRW_MATH_PRECISION_FULL);
430 } else if (dispatch_width == 16) {
431 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
432 gen4_math(p, firsthalf(dst),
433 op,
434 inst->base_mrf, firsthalf(src),
435 BRW_MATH_PRECISION_FULL);
436 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
437 gen4_math(p, sechalf(dst),
438 op,
439 inst->base_mrf + 1, sechalf(src),
440 BRW_MATH_PRECISION_FULL);
441
442 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
443 }
444 }
445
446 void
447 fs_generator::generate_math_g45(fs_inst *inst,
448 struct brw_reg dst,
449 struct brw_reg src)
450 {
451 if (inst->opcode == SHADER_OPCODE_POW ||
452 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
453 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
454 generate_math_gen4(inst, dst, src);
455 return;
456 }
457
458 int op = brw_math_function(inst->opcode);
459
460 assert(inst->mlen >= 1);
461
462 gen4_math(p, dst,
463 op,
464 inst->base_mrf, src,
465 BRW_MATH_PRECISION_FULL);
466 }
467
468 void
469 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
470 struct brw_reg sampler_index)
471 {
472 int msg_type = -1;
473 int rlen = 4;
474 uint32_t simd_mode;
475 uint32_t return_format;
476
477 switch (dst.type) {
478 case BRW_REGISTER_TYPE_D:
479 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
480 break;
481 case BRW_REGISTER_TYPE_UD:
482 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
483 break;
484 default:
485 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
486 break;
487 }
488
489 switch (inst->exec_size) {
490 case 8:
491 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
492 break;
493 case 16:
494 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
495 break;
496 default:
497 unreachable("Invalid width for texture instruction");
498 }
499
500 if (brw->gen >= 5) {
501 switch (inst->opcode) {
502 case SHADER_OPCODE_TEX:
503 if (inst->shadow_compare) {
504 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
505 } else {
506 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
507 }
508 break;
509 case FS_OPCODE_TXB:
510 if (inst->shadow_compare) {
511 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
512 } else {
513 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
514 }
515 break;
516 case SHADER_OPCODE_TXL:
517 if (inst->shadow_compare) {
518 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
519 } else {
520 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
521 }
522 break;
523 case SHADER_OPCODE_TXS:
524 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
525 break;
526 case SHADER_OPCODE_TXD:
527 if (inst->shadow_compare) {
528 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
529 assert(brw->gen >= 8 || brw->is_haswell);
530 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
531 } else {
532 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
533 }
534 break;
535 case SHADER_OPCODE_TXF:
536 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
537 break;
538 case SHADER_OPCODE_TXF_CMS:
539 if (brw->gen >= 7)
540 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
541 else
542 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
543 break;
544 case SHADER_OPCODE_TXF_UMS:
545 assert(brw->gen >= 7);
546 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
547 break;
548 case SHADER_OPCODE_TXF_MCS:
549 assert(brw->gen >= 7);
550 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
551 break;
552 case SHADER_OPCODE_LOD:
553 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
554 break;
555 case SHADER_OPCODE_TG4:
556 if (inst->shadow_compare) {
557 assert(brw->gen >= 7);
558 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
559 } else {
560 assert(brw->gen >= 6);
561 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
562 }
563 break;
564 case SHADER_OPCODE_TG4_OFFSET:
565 assert(brw->gen >= 7);
566 if (inst->shadow_compare) {
567 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
568 } else {
569 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
570 }
571 break;
572 default:
573 unreachable("not reached");
574 }
575 } else {
576 switch (inst->opcode) {
577 case SHADER_OPCODE_TEX:
578 /* Note that G45 and older determines shadow compare and dispatch width
579 * from message length for most messages.
580 */
581 assert(dispatch_width == 8);
582 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
583 if (inst->shadow_compare) {
584 assert(inst->mlen == 6);
585 } else {
586 assert(inst->mlen <= 4);
587 }
588 break;
589 case FS_OPCODE_TXB:
590 if (inst->shadow_compare) {
591 assert(inst->mlen == 6);
592 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
593 } else {
594 assert(inst->mlen == 9);
595 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
596 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
597 }
598 break;
599 case SHADER_OPCODE_TXL:
600 if (inst->shadow_compare) {
601 assert(inst->mlen == 6);
602 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
603 } else {
604 assert(inst->mlen == 9);
605 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
606 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
607 }
608 break;
609 case SHADER_OPCODE_TXD:
610 /* There is no sample_d_c message; comparisons are done manually */
611 assert(inst->mlen == 7 || inst->mlen == 10);
612 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
613 break;
614 case SHADER_OPCODE_TXF:
615 assert(inst->mlen == 9);
616 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
617 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
618 break;
619 case SHADER_OPCODE_TXS:
620 assert(inst->mlen == 3);
621 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
622 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
623 break;
624 default:
625 unreachable("not reached");
626 }
627 }
628 assert(msg_type != -1);
629
630 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
631 rlen = 8;
632 dst = vec16(dst);
633 }
634
635 assert(brw->gen < 7 || !inst->header_present ||
636 src.file == BRW_GENERAL_REGISTER_FILE);
637
638 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
639
640 /* Load the message header if present. If there's a texture offset,
641 * we need to set it up explicitly and load the offset bitfield.
642 * Otherwise, we can use an implied move from g0 to the first message reg.
643 */
644 if (inst->header_present) {
645 if (brw->gen < 6 && !inst->offset) {
646 /* Set up an implied move from g0 to the MRF. */
647 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
648 } else {
649 struct brw_reg header_reg;
650
651 if (brw->gen >= 7) {
652 header_reg = src;
653 } else {
654 assert(inst->base_mrf != -1);
655 header_reg = brw_message_reg(inst->base_mrf);
656 }
657
658 brw_push_insn_state(p);
659 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
660 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
661 /* Explicitly set up the message header by copying g0 to the MRF. */
662 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
663
664 if (inst->offset) {
665 /* Set the offset bits in DWord 2. */
666 brw_MOV(p, get_element_ud(header_reg, 2),
667 brw_imm_ud(inst->offset));
668 }
669
670 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index, dst);
671 brw_pop_insn_state(p);
672 }
673 }
674
675 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
676 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
677 ? prog_data->binding_table.gather_texture_start
678 : prog_data->binding_table.texture_start;
679
680 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
681 uint32_t sampler = sampler_index.dw1.ud;
682
683 brw_SAMPLE(p,
684 retype(dst, BRW_REGISTER_TYPE_UW),
685 inst->base_mrf,
686 src,
687 sampler + base_binding_table_index,
688 sampler % 16,
689 msg_type,
690 rlen,
691 inst->mlen,
692 inst->header_present,
693 simd_mode,
694 return_format);
695
696 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
697 } else {
698 /* Non-const sampler index */
699 /* Note: this clobbers `dst` as a temporary before emitting the send */
700
701 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
702 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
703
704 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
705
706 brw_push_insn_state(p);
707 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
708 brw_set_default_access_mode(p, BRW_ALIGN_1);
709
710 /* Some care required: `sampler` and `temp` may alias:
711 * addr = sampler & 0xff
712 * temp = (sampler << 8) & 0xf00
713 * addr = addr | temp
714 */
715 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
716 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
717 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
718 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
719 brw_OR(p, addr, addr, temp);
720
721 /* a0.0 |= <descriptor> */
722 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
723 brw_set_sampler_message(p, insn_or,
724 0 /* surface */,
725 0 /* sampler */,
726 msg_type,
727 rlen,
728 inst->mlen /* mlen */,
729 inst->header_present /* header */,
730 simd_mode,
731 return_format);
732 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
733 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
734 brw_set_src0(p, insn_or, addr);
735 brw_set_dest(p, insn_or, addr);
736
737
738 /* dst = send(offset, a0.0) */
739 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
740 brw_set_dest(p, insn_send, dst);
741 brw_set_src0(p, insn_send, src);
742 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
743
744 brw_pop_insn_state(p);
745
746 /* visitor knows more than we do about the surface limit required,
747 * so has already done marking.
748 */
749 }
750 }
751
752
753 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
754 * looking like:
755 *
756 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
757 *
758 * Ideally, we want to produce:
759 *
760 * DDX DDY
761 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
762 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
763 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
764 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
765 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
766 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
767 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
768 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
769 *
770 * and add another set of two more subspans if in 16-pixel dispatch mode.
771 *
772 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
773 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
774 * pair. But the ideal approximation may impose a huge performance cost on
775 * sample_d. On at least Haswell, sample_d instruction does some
776 * optimizations if the same LOD is used for all pixels in the subspan.
777 *
778 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
779 * appropriate swizzling.
780 */
781 void
782 fs_generator::generate_ddx(enum opcode opcode,
783 struct brw_reg dst, struct brw_reg src)
784 {
785 unsigned vstride, width;
786
787 if (opcode == FS_OPCODE_DDX_FINE) {
788 /* produce accurate derivatives */
789 vstride = BRW_VERTICAL_STRIDE_2;
790 width = BRW_WIDTH_2;
791 } else {
792 /* replicate the derivative at the top-left pixel to other pixels */
793 vstride = BRW_VERTICAL_STRIDE_4;
794 width = BRW_WIDTH_4;
795 }
796
797 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
798 BRW_REGISTER_TYPE_F,
799 vstride,
800 width,
801 BRW_HORIZONTAL_STRIDE_0,
802 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
803 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
804 BRW_REGISTER_TYPE_F,
805 vstride,
806 width,
807 BRW_HORIZONTAL_STRIDE_0,
808 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
809 brw_ADD(p, dst, src0, negate(src1));
810 }
811
812 /* The negate_value boolean is used to negate the derivative computation for
813 * FBOs, since they place the origin at the upper left instead of the lower
814 * left.
815 */
816 void
817 fs_generator::generate_ddy(enum opcode opcode,
818 struct brw_reg dst, struct brw_reg src,
819 bool negate_value)
820 {
821 if (opcode == FS_OPCODE_DDY_FINE) {
822 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
823 * Region Restrictions):
824 *
825 * In Align16 access mode, SIMD16 is not allowed for DW operations
826 * and SIMD8 is not allowed for DF operations.
827 *
828 * In this context, "DW operations" means "operations acting on 32-bit
829 * values", so it includes operations on floats.
830 *
831 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
832 * (Instruction Compression -> Rules and Restrictions):
833 *
834 * A compressed instruction must be in Align1 access mode. Align16
835 * mode instructions cannot be compressed.
836 *
837 * Similar text exists in the g45 PRM.
838 *
839 * On these platforms, if we're building a SIMD16 shader, we need to
840 * manually unroll to a pair of SIMD8 instructions.
841 */
842 bool unroll_to_simd8 =
843 (dispatch_width == 16 &&
844 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
845
846 /* produce accurate derivatives */
847 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
848 BRW_REGISTER_TYPE_F,
849 BRW_VERTICAL_STRIDE_4,
850 BRW_WIDTH_4,
851 BRW_HORIZONTAL_STRIDE_1,
852 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
853 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
854 BRW_REGISTER_TYPE_F,
855 BRW_VERTICAL_STRIDE_4,
856 BRW_WIDTH_4,
857 BRW_HORIZONTAL_STRIDE_1,
858 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
859 brw_push_insn_state(p);
860 brw_set_default_access_mode(p, BRW_ALIGN_16);
861 if (unroll_to_simd8) {
862 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
863 if (negate_value) {
864 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
865 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
866 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
867 } else {
868 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
869 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
870 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
871 }
872 } else {
873 if (negate_value)
874 brw_ADD(p, dst, src1, negate(src0));
875 else
876 brw_ADD(p, dst, src0, negate(src1));
877 }
878 brw_pop_insn_state(p);
879 } else {
880 /* replicate the derivative at the top-left pixel to other pixels */
881 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
882 BRW_REGISTER_TYPE_F,
883 BRW_VERTICAL_STRIDE_4,
884 BRW_WIDTH_4,
885 BRW_HORIZONTAL_STRIDE_0,
886 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
887 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
888 BRW_REGISTER_TYPE_F,
889 BRW_VERTICAL_STRIDE_4,
890 BRW_WIDTH_4,
891 BRW_HORIZONTAL_STRIDE_0,
892 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
893 if (negate_value)
894 brw_ADD(p, dst, src1, negate(src0));
895 else
896 brw_ADD(p, dst, src0, negate(src1));
897 }
898 }
899
900 void
901 fs_generator::generate_discard_jump(fs_inst *inst)
902 {
903 assert(brw->gen >= 6);
904
905 /* This HALT will be patched up at FB write time to point UIP at the end of
906 * the program, and at brw_uip_jip() JIP will be set to the end of the
907 * current block (or the program).
908 */
909 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
910
911 brw_push_insn_state(p);
912 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
913 gen6_HALT(p);
914 brw_pop_insn_state(p);
915 }
916
917 void
918 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
919 {
920 assert(inst->mlen != 0);
921
922 brw_MOV(p,
923 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
924 retype(src, BRW_REGISTER_TYPE_UD));
925 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
926 inst->exec_size / 8, inst->offset);
927 }
928
929 void
930 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
931 {
932 assert(inst->mlen != 0);
933
934 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
935 inst->exec_size / 8, inst->offset);
936 }
937
938 void
939 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
940 {
941 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
942 }
943
944 void
945 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
946 struct brw_reg dst,
947 struct brw_reg index,
948 struct brw_reg offset)
949 {
950 assert(inst->mlen != 0);
951
952 assert(index.file == BRW_IMMEDIATE_VALUE &&
953 index.type == BRW_REGISTER_TYPE_UD);
954 uint32_t surf_index = index.dw1.ud;
955
956 assert(offset.file == BRW_IMMEDIATE_VALUE &&
957 offset.type == BRW_REGISTER_TYPE_UD);
958 uint32_t read_offset = offset.dw1.ud;
959
960 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
961 read_offset, surf_index);
962
963 brw_mark_surface_used(prog_data, surf_index);
964 }
965
966 void
967 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
968 struct brw_reg dst,
969 struct brw_reg index,
970 struct brw_reg offset)
971 {
972 assert(inst->mlen == 0);
973 assert(index.type == BRW_REGISTER_TYPE_UD);
974
975 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
976 /* Reference just the dword we need, to avoid angering validate_reg(). */
977 offset = brw_vec1_grf(offset.nr, 0);
978
979 /* We use the SIMD4x2 mode because we want to end up with 4 components in
980 * the destination loaded consecutively from the same offset (which appears
981 * in the first component, and the rest are ignored).
982 */
983 dst.width = BRW_WIDTH_4;
984
985 if (index.file == BRW_IMMEDIATE_VALUE) {
986
987 uint32_t surf_index = index.dw1.ud;
988
989 brw_push_insn_state(p);
990 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
991 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
992 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
993 brw_pop_insn_state(p);
994
995 brw_set_dest(p, send, dst);
996 brw_set_src0(p, send, offset);
997 brw_set_sampler_message(p, send,
998 surf_index,
999 0, /* LD message ignores sampler unit */
1000 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1001 1, /* rlen */
1002 1, /* mlen */
1003 false, /* no header */
1004 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1005 0);
1006
1007 brw_mark_surface_used(prog_data, surf_index);
1008
1009 } else {
1010
1011 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1012
1013 brw_push_insn_state(p);
1014 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1015 brw_set_default_access_mode(p, BRW_ALIGN_1);
1016
1017 /* a0.0 = surf_index & 0xff */
1018 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1019 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1020 brw_set_dest(p, insn_and, addr);
1021 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1022 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1023
1024
1025 /* a0.0 |= <descriptor> */
1026 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1027 brw_set_sampler_message(p, insn_or,
1028 0 /* surface */,
1029 0 /* sampler */,
1030 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1031 1 /* rlen */,
1032 1 /* mlen */,
1033 false /* header */,
1034 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1035 0);
1036 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1037 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1038 brw_set_src0(p, insn_or, addr);
1039 brw_set_dest(p, insn_or, addr);
1040
1041
1042 /* dst = send(offset, a0.0) */
1043 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1044 brw_set_dest(p, insn_send, dst);
1045 brw_set_src0(p, insn_send, offset);
1046 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1047
1048 brw_pop_insn_state(p);
1049
1050 /* visitor knows more than we do about the surface limit required,
1051 * so has already done marking.
1052 */
1053
1054 }
1055 }
1056
1057 void
1058 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1059 struct brw_reg dst,
1060 struct brw_reg index,
1061 struct brw_reg offset)
1062 {
1063 assert(brw->gen < 7); /* Should use the gen7 variant. */
1064 assert(inst->header_present);
1065 assert(inst->mlen);
1066
1067 assert(index.file == BRW_IMMEDIATE_VALUE &&
1068 index.type == BRW_REGISTER_TYPE_UD);
1069 uint32_t surf_index = index.dw1.ud;
1070
1071 uint32_t simd_mode, rlen, msg_type;
1072 if (dispatch_width == 16) {
1073 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1074 rlen = 8;
1075 } else {
1076 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1077 rlen = 4;
1078 }
1079
1080 if (brw->gen >= 5)
1081 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1082 else {
1083 /* We always use the SIMD16 message so that we only have to load U, and
1084 * not V or R.
1085 */
1086 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1087 assert(inst->mlen == 3);
1088 assert(inst->regs_written == 8);
1089 rlen = 8;
1090 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1091 }
1092
1093 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1094 BRW_REGISTER_TYPE_D);
1095 brw_MOV(p, offset_mrf, offset);
1096
1097 struct brw_reg header = brw_vec8_grf(0, 0);
1098 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1099
1100 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1101 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
1102 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1103 brw_set_src0(p, send, header);
1104 if (brw->gen < 6)
1105 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
1106
1107 /* Our surface is set up as floats, regardless of what actual data is
1108 * stored in it.
1109 */
1110 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1111 brw_set_sampler_message(p, send,
1112 surf_index,
1113 0, /* sampler (unused) */
1114 msg_type,
1115 rlen,
1116 inst->mlen,
1117 inst->header_present,
1118 simd_mode,
1119 return_format);
1120
1121 brw_mark_surface_used(prog_data, surf_index);
1122 }
1123
1124 void
1125 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1126 struct brw_reg dst,
1127 struct brw_reg index,
1128 struct brw_reg offset)
1129 {
1130 assert(brw->gen >= 7);
1131 /* Varying-offset pull constant loads are treated as a normal expression on
1132 * gen7, so the fact that it's a send message is hidden at the IR level.
1133 */
1134 assert(!inst->header_present);
1135 assert(!inst->mlen);
1136 assert(index.type == BRW_REGISTER_TYPE_UD);
1137
1138 uint32_t simd_mode, rlen, mlen;
1139 if (dispatch_width == 16) {
1140 mlen = 2;
1141 rlen = 8;
1142 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1143 } else {
1144 mlen = 1;
1145 rlen = 4;
1146 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1147 }
1148
1149 if (index.file == BRW_IMMEDIATE_VALUE) {
1150
1151 uint32_t surf_index = index.dw1.ud;
1152
1153 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1154 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1155 brw_set_src0(p, send, offset);
1156 brw_set_sampler_message(p, send,
1157 surf_index,
1158 0, /* LD message ignores sampler unit */
1159 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1160 rlen,
1161 mlen,
1162 false, /* no header */
1163 simd_mode,
1164 0);
1165
1166 brw_mark_surface_used(prog_data, surf_index);
1167
1168 } else {
1169
1170 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1171
1172 brw_push_insn_state(p);
1173 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1174 brw_set_default_access_mode(p, BRW_ALIGN_1);
1175
1176 /* a0.0 = surf_index & 0xff */
1177 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1178 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1179 brw_set_dest(p, insn_and, addr);
1180 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1181 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1182
1183
1184 /* a0.0 |= <descriptor> */
1185 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1186 brw_set_sampler_message(p, insn_or,
1187 0 /* surface */,
1188 0 /* sampler */,
1189 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1190 rlen /* rlen */,
1191 mlen /* mlen */,
1192 false /* header */,
1193 simd_mode,
1194 0);
1195 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1196 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1197 brw_set_src0(p, insn_or, addr);
1198 brw_set_dest(p, insn_or, addr);
1199
1200
1201 /* dst = send(offset, a0.0) */
1202 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1203 brw_set_dest(p, insn_send, retype(dst, BRW_REGISTER_TYPE_UW));
1204 brw_set_src0(p, insn_send, offset);
1205 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1206
1207 brw_pop_insn_state(p);
1208
1209 /* visitor knows more than we do about the surface limit required,
1210 * so has already done marking.
1211 */
1212 }
1213 }
1214
1215 /**
1216 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1217 * into the flags register (f0.0).
1218 *
1219 * Used only on Gen6 and above.
1220 */
1221 void
1222 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1223 {
1224 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1225 struct brw_reg dispatch_mask;
1226
1227 if (brw->gen >= 6)
1228 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1229 else
1230 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1231
1232 brw_push_insn_state(p);
1233 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1234 brw_MOV(p, flags, dispatch_mask);
1235 brw_pop_insn_state(p);
1236 }
1237
1238 void
1239 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1240 struct brw_reg dst,
1241 struct brw_reg src,
1242 struct brw_reg msg_data,
1243 unsigned msg_type)
1244 {
1245 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1246 msg_data.type == BRW_REGISTER_TYPE_UD);
1247
1248 brw_pixel_interpolator_query(p,
1249 retype(dst, BRW_REGISTER_TYPE_UW),
1250 src,
1251 inst->pi_noperspective,
1252 msg_type,
1253 msg_data.dw1.ud,
1254 inst->mlen,
1255 inst->regs_written);
1256 }
1257
1258
1259 static uint32_t brw_file_from_reg(fs_reg *reg)
1260 {
1261 switch (reg->file) {
1262 case GRF:
1263 return BRW_GENERAL_REGISTER_FILE;
1264 case MRF:
1265 return BRW_MESSAGE_REGISTER_FILE;
1266 case IMM:
1267 return BRW_IMMEDIATE_VALUE;
1268 default:
1269 unreachable("not reached");
1270 }
1271 }
1272
1273 /**
1274 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1275 * sampler LD messages.
1276 *
1277 * We don't want to bake it into the send message's code generation because
1278 * that means we don't get a chance to schedule the instructions.
1279 */
1280 void
1281 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1282 struct brw_reg dst,
1283 struct brw_reg value)
1284 {
1285 assert(value.file == BRW_IMMEDIATE_VALUE);
1286
1287 brw_push_insn_state(p);
1288 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1289 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1290 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1291 brw_pop_insn_state(p);
1292 }
1293
1294 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1295 * (when mask is passed as a uniform) of register mask before moving it
1296 * to register dst.
1297 */
1298 void
1299 fs_generator::generate_set_omask(fs_inst *inst,
1300 struct brw_reg dst,
1301 struct brw_reg mask)
1302 {
1303 bool stride_8_8_1 =
1304 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1305 mask.width == BRW_WIDTH_8 &&
1306 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1307
1308 bool stride_0_1_0 =
1309 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1310 mask.width == BRW_WIDTH_1 &&
1311 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1312
1313 assert(stride_8_8_1 || stride_0_1_0);
1314 assert(dst.type == BRW_REGISTER_TYPE_UW);
1315
1316 if (dispatch_width == 16)
1317 dst = vec16(dst);
1318 brw_push_insn_state(p);
1319 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1320 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1321
1322 if (stride_8_8_1) {
1323 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1324 } else if (stride_0_1_0) {
1325 brw_MOV(p, dst, retype(mask, dst.type));
1326 }
1327 brw_pop_insn_state(p);
1328 }
1329
1330 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1331 * the ADD instruction.
1332 */
1333 void
1334 fs_generator::generate_set_sample_id(fs_inst *inst,
1335 struct brw_reg dst,
1336 struct brw_reg src0,
1337 struct brw_reg src1)
1338 {
1339 assert(dst.type == BRW_REGISTER_TYPE_D ||
1340 dst.type == BRW_REGISTER_TYPE_UD);
1341 assert(src0.type == BRW_REGISTER_TYPE_D ||
1342 src0.type == BRW_REGISTER_TYPE_UD);
1343
1344 brw_push_insn_state(p);
1345 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1346 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1347 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1348 if (dispatch_width == 8) {
1349 brw_ADD(p, dst, src0, reg);
1350 } else if (dispatch_width == 16) {
1351 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1352 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1353 }
1354 brw_pop_insn_state(p);
1355 }
1356
1357 /**
1358 * Change the register's data type from UD to W, doubling the strides in order
1359 * to compensate for halving the data type width.
1360 */
1361 static struct brw_reg
1362 ud_reg_to_w(struct brw_reg r)
1363 {
1364 assert(r.type == BRW_REGISTER_TYPE_UD);
1365 r.type = BRW_REGISTER_TYPE_W;
1366
1367 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1368 * doubles the real stride.
1369 */
1370 if (r.hstride != 0)
1371 ++r.hstride;
1372 if (r.vstride != 0)
1373 ++r.vstride;
1374
1375 return r;
1376 }
1377
1378 void
1379 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1380 struct brw_reg dst,
1381 struct brw_reg x,
1382 struct brw_reg y)
1383 {
1384 assert(brw->gen >= 7);
1385 assert(dst.type == BRW_REGISTER_TYPE_UD);
1386 assert(x.type == BRW_REGISTER_TYPE_F);
1387 assert(y.type == BRW_REGISTER_TYPE_F);
1388
1389 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1390 *
1391 * Because this instruction does not have a 16-bit floating-point type,
1392 * the destination data type must be Word (W).
1393 *
1394 * The destination must be DWord-aligned and specify a horizontal stride
1395 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1396 * each destination channel and the upper word is not modified.
1397 */
1398 struct brw_reg dst_w = ud_reg_to_w(dst);
1399
1400 /* Give each 32-bit channel of dst the form below , where "." means
1401 * unchanged.
1402 * 0x....hhhh
1403 */
1404 brw_F32TO16(p, dst_w, y);
1405
1406 /* Now the form:
1407 * 0xhhhh0000
1408 */
1409 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1410
1411 /* And, finally the form of packHalf2x16's output:
1412 * 0xhhhhllll
1413 */
1414 brw_F32TO16(p, dst_w, x);
1415 }
1416
1417 void
1418 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1419 struct brw_reg dst,
1420 struct brw_reg src)
1421 {
1422 assert(brw->gen >= 7);
1423 assert(dst.type == BRW_REGISTER_TYPE_F);
1424 assert(src.type == BRW_REGISTER_TYPE_UD);
1425
1426 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1427 *
1428 * Because this instruction does not have a 16-bit floating-point type,
1429 * the source data type must be Word (W). The destination type must be
1430 * F (Float).
1431 */
1432 struct brw_reg src_w = ud_reg_to_w(src);
1433
1434 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1435 * For the Y case, we wish to access only the upper word; therefore
1436 * a 16-bit subregister offset is needed.
1437 */
1438 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1439 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1440 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1441 src_w.subnr += 2;
1442
1443 brw_F16TO32(p, dst, src_w);
1444 }
1445
1446 void
1447 fs_generator::generate_shader_time_add(fs_inst *inst,
1448 struct brw_reg payload,
1449 struct brw_reg offset,
1450 struct brw_reg value)
1451 {
1452 assert(brw->gen >= 7);
1453 brw_push_insn_state(p);
1454 brw_set_default_mask_control(p, true);
1455
1456 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1457 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1458 offset.type);
1459 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1460 value.type);
1461
1462 assert(offset.file == BRW_IMMEDIATE_VALUE);
1463 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1464 value.width = BRW_WIDTH_1;
1465 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1466 value.vstride = BRW_VERTICAL_STRIDE_0;
1467 } else {
1468 assert(value.file == BRW_IMMEDIATE_VALUE);
1469 }
1470
1471 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1472 * case, and we don't really care about squeezing every bit of performance
1473 * out of this path, so we just emit the MOVs from here.
1474 */
1475 brw_MOV(p, payload_offset, offset);
1476 brw_MOV(p, payload_value, value);
1477 brw_shader_time_add(p, payload,
1478 prog_data->binding_table.shader_time_start);
1479 brw_pop_insn_state(p);
1480
1481 brw_mark_surface_used(prog_data,
1482 prog_data->binding_table.shader_time_start);
1483 }
1484
1485 void
1486 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1487 struct brw_reg payload,
1488 struct brw_reg atomic_op,
1489 struct brw_reg surf_index)
1490 {
1491 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1492 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1493 surf_index.file == BRW_IMMEDIATE_VALUE &&
1494 surf_index.type == BRW_REGISTER_TYPE_UD);
1495
1496 brw_untyped_atomic(p, dst, payload, atomic_op.dw1.ud, surf_index.dw1.ud,
1497 inst->mlen, inst->exec_size / 8);
1498
1499 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1500 }
1501
1502 void
1503 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1504 struct brw_reg payload,
1505 struct brw_reg surf_index)
1506 {
1507 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1508 surf_index.type == BRW_REGISTER_TYPE_UD);
1509
1510 brw_untyped_surface_read(p, dst, payload,
1511 surf_index.dw1.ud,
1512 inst->mlen, inst->exec_size / 8);
1513
1514 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1515 }
1516
1517 int
1518 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1519 {
1520 /* align to 64 byte boundary. */
1521 while (p->next_insn_offset % 64)
1522 brw_NOP(p);
1523
1524 this->dispatch_width = dispatch_width;
1525 if (dispatch_width == 16)
1526 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1527
1528 int start_offset = p->next_insn_offset;
1529 int loop_count = 0;
1530
1531 struct annotation_info annotation;
1532 memset(&annotation, 0, sizeof(annotation));
1533
1534 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1535 struct brw_reg src[3], dst;
1536 unsigned int last_insn_offset = p->next_insn_offset;
1537
1538 if (unlikely(debug_flag))
1539 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1540
1541 for (unsigned int i = 0; i < inst->sources; i++) {
1542 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1543
1544 /* The accumulator result appears to get used for the
1545 * conditional modifier generation. When negating a UD
1546 * value, there is a 33rd bit generated for the sign in the
1547 * accumulator value, so now you can't check, for example,
1548 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1549 */
1550 assert(!inst->conditional_mod ||
1551 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1552 !inst->src[i].negate);
1553 }
1554 dst = brw_reg_from_fs_reg(&inst->dst);
1555
1556 brw_set_default_predicate_control(p, inst->predicate);
1557 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1558 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1559 brw_set_default_saturate(p, inst->saturate);
1560 brw_set_default_mask_control(p, inst->force_writemask_all);
1561 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1562
1563 switch (inst->exec_size) {
1564 case 1:
1565 case 2:
1566 case 4:
1567 assert(inst->force_writemask_all);
1568 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1569 break;
1570 case 8:
1571 if (inst->force_sechalf) {
1572 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1573 } else {
1574 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1575 }
1576 break;
1577 case 16:
1578 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1579 break;
1580 default:
1581 unreachable(!"Invalid instruction width");
1582 }
1583
1584 switch (inst->opcode) {
1585 case BRW_OPCODE_MOV:
1586 brw_MOV(p, dst, src[0]);
1587 break;
1588 case BRW_OPCODE_ADD:
1589 brw_ADD(p, dst, src[0], src[1]);
1590 break;
1591 case BRW_OPCODE_MUL:
1592 brw_MUL(p, dst, src[0], src[1]);
1593 break;
1594 case BRW_OPCODE_AVG:
1595 brw_AVG(p, dst, src[0], src[1]);
1596 break;
1597 case BRW_OPCODE_MACH:
1598 brw_MACH(p, dst, src[0], src[1]);
1599 break;
1600
1601 case BRW_OPCODE_MAD:
1602 assert(brw->gen >= 6);
1603 brw_set_default_access_mode(p, BRW_ALIGN_16);
1604 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1605 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1606 brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1607 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1608 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1609 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1610 } else {
1611 brw_MAD(p, dst, src[0], src[1], src[2]);
1612 }
1613 brw_set_default_access_mode(p, BRW_ALIGN_1);
1614 break;
1615
1616 case BRW_OPCODE_LRP:
1617 assert(brw->gen >= 6);
1618 brw_set_default_access_mode(p, BRW_ALIGN_16);
1619 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1620 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1621 brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1622 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1623 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1624 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1625 } else {
1626 brw_LRP(p, dst, src[0], src[1], src[2]);
1627 }
1628 brw_set_default_access_mode(p, BRW_ALIGN_1);
1629 break;
1630
1631 case BRW_OPCODE_FRC:
1632 brw_FRC(p, dst, src[0]);
1633 break;
1634 case BRW_OPCODE_RNDD:
1635 brw_RNDD(p, dst, src[0]);
1636 break;
1637 case BRW_OPCODE_RNDE:
1638 brw_RNDE(p, dst, src[0]);
1639 break;
1640 case BRW_OPCODE_RNDZ:
1641 brw_RNDZ(p, dst, src[0]);
1642 break;
1643
1644 case BRW_OPCODE_AND:
1645 brw_AND(p, dst, src[0], src[1]);
1646 break;
1647 case BRW_OPCODE_OR:
1648 brw_OR(p, dst, src[0], src[1]);
1649 break;
1650 case BRW_OPCODE_XOR:
1651 brw_XOR(p, dst, src[0], src[1]);
1652 break;
1653 case BRW_OPCODE_NOT:
1654 brw_NOT(p, dst, src[0]);
1655 break;
1656 case BRW_OPCODE_ASR:
1657 brw_ASR(p, dst, src[0], src[1]);
1658 break;
1659 case BRW_OPCODE_SHR:
1660 brw_SHR(p, dst, src[0], src[1]);
1661 break;
1662 case BRW_OPCODE_SHL:
1663 brw_SHL(p, dst, src[0], src[1]);
1664 break;
1665 case BRW_OPCODE_F32TO16:
1666 assert(brw->gen >= 7);
1667 brw_F32TO16(p, dst, src[0]);
1668 break;
1669 case BRW_OPCODE_F16TO32:
1670 assert(brw->gen >= 7);
1671 brw_F16TO32(p, dst, src[0]);
1672 break;
1673 case BRW_OPCODE_CMP:
1674 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1675 break;
1676 case BRW_OPCODE_SEL:
1677 brw_SEL(p, dst, src[0], src[1]);
1678 break;
1679 case BRW_OPCODE_BFREV:
1680 assert(brw->gen >= 7);
1681 /* BFREV only supports UD type for src and dst. */
1682 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1683 retype(src[0], BRW_REGISTER_TYPE_UD));
1684 break;
1685 case BRW_OPCODE_FBH:
1686 assert(brw->gen >= 7);
1687 /* FBH only supports UD type for dst. */
1688 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1689 break;
1690 case BRW_OPCODE_FBL:
1691 assert(brw->gen >= 7);
1692 /* FBL only supports UD type for dst. */
1693 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1694 break;
1695 case BRW_OPCODE_CBIT:
1696 assert(brw->gen >= 7);
1697 /* CBIT only supports UD type for dst. */
1698 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1699 break;
1700 case BRW_OPCODE_ADDC:
1701 assert(brw->gen >= 7);
1702 brw_ADDC(p, dst, src[0], src[1]);
1703 break;
1704 case BRW_OPCODE_SUBB:
1705 assert(brw->gen >= 7);
1706 brw_SUBB(p, dst, src[0], src[1]);
1707 break;
1708 case BRW_OPCODE_MAC:
1709 brw_MAC(p, dst, src[0], src[1]);
1710 break;
1711
1712 case BRW_OPCODE_BFE:
1713 assert(brw->gen >= 7);
1714 brw_set_default_access_mode(p, BRW_ALIGN_16);
1715 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1716 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1717 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1718 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1719 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1720 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1721 } else {
1722 brw_BFE(p, dst, src[0], src[1], src[2]);
1723 }
1724 brw_set_default_access_mode(p, BRW_ALIGN_1);
1725 break;
1726
1727 case BRW_OPCODE_BFI1:
1728 assert(brw->gen >= 7);
1729 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1730 * should
1731 *
1732 * "Force BFI instructions to be executed always in SIMD8."
1733 */
1734 if (dispatch_width == 16 && brw->is_haswell) {
1735 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1736 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1737 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1738 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1739 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1740 } else {
1741 brw_BFI1(p, dst, src[0], src[1]);
1742 }
1743 break;
1744 case BRW_OPCODE_BFI2:
1745 assert(brw->gen >= 7);
1746 brw_set_default_access_mode(p, BRW_ALIGN_16);
1747 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1748 * should
1749 *
1750 * "Force BFI instructions to be executed always in SIMD8."
1751 *
1752 * Otherwise we would be able to emit compressed instructions like we
1753 * do for the other three-source instructions.
1754 */
1755 if (dispatch_width == 16 && brw->gen < 8) {
1756 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1757 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1758 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1759 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1760 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1761 } else {
1762 brw_BFI2(p, dst, src[0], src[1], src[2]);
1763 }
1764 brw_set_default_access_mode(p, BRW_ALIGN_1);
1765 break;
1766
1767 case BRW_OPCODE_IF:
1768 if (inst->src[0].file != BAD_FILE) {
1769 /* The instruction has an embedded compare (only allowed on gen6) */
1770 assert(brw->gen == 6);
1771 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1772 } else {
1773 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1774 }
1775 break;
1776
1777 case BRW_OPCODE_ELSE:
1778 brw_ELSE(p);
1779 break;
1780 case BRW_OPCODE_ENDIF:
1781 brw_ENDIF(p);
1782 break;
1783
1784 case BRW_OPCODE_DO:
1785 brw_DO(p, BRW_EXECUTE_8);
1786 break;
1787
1788 case BRW_OPCODE_BREAK:
1789 brw_BREAK(p);
1790 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1791 break;
1792 case BRW_OPCODE_CONTINUE:
1793 brw_CONT(p);
1794 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1795 break;
1796
1797 case BRW_OPCODE_WHILE:
1798 brw_WHILE(p);
1799 loop_count++;
1800 break;
1801
1802 case SHADER_OPCODE_RCP:
1803 case SHADER_OPCODE_RSQ:
1804 case SHADER_OPCODE_SQRT:
1805 case SHADER_OPCODE_EXP2:
1806 case SHADER_OPCODE_LOG2:
1807 case SHADER_OPCODE_SIN:
1808 case SHADER_OPCODE_COS:
1809 assert(brw->gen < 6 || inst->mlen == 0);
1810 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1811 if (brw->gen >= 7) {
1812 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1813 brw_null_reg());
1814 } else if (brw->gen == 6) {
1815 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1816 } else if (brw->gen == 5 || brw->is_g4x) {
1817 generate_math_g45(inst, dst, src[0]);
1818 } else {
1819 generate_math_gen4(inst, dst, src[0]);
1820 }
1821 break;
1822 case SHADER_OPCODE_INT_QUOTIENT:
1823 case SHADER_OPCODE_INT_REMAINDER:
1824 case SHADER_OPCODE_POW:
1825 assert(brw->gen < 6 || inst->mlen == 0);
1826 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1827 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1828 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1829 } else if (brw->gen >= 6) {
1830 generate_math_gen6(inst, dst, src[0], src[1]);
1831 } else {
1832 generate_math_gen4(inst, dst, src[0]);
1833 }
1834 break;
1835 case FS_OPCODE_PIXEL_X:
1836 generate_pixel_xy(dst, true);
1837 break;
1838 case FS_OPCODE_PIXEL_Y:
1839 generate_pixel_xy(dst, false);
1840 break;
1841 case FS_OPCODE_CINTERP:
1842 brw_MOV(p, dst, src[0]);
1843 break;
1844 case FS_OPCODE_LINTERP:
1845 generate_linterp(inst, dst, src);
1846 break;
1847 case SHADER_OPCODE_TEX:
1848 case FS_OPCODE_TXB:
1849 case SHADER_OPCODE_TXD:
1850 case SHADER_OPCODE_TXF:
1851 case SHADER_OPCODE_TXF_CMS:
1852 case SHADER_OPCODE_TXF_UMS:
1853 case SHADER_OPCODE_TXF_MCS:
1854 case SHADER_OPCODE_TXL:
1855 case SHADER_OPCODE_TXS:
1856 case SHADER_OPCODE_LOD:
1857 case SHADER_OPCODE_TG4:
1858 case SHADER_OPCODE_TG4_OFFSET:
1859 generate_tex(inst, dst, src[0], src[1]);
1860 break;
1861 case FS_OPCODE_DDX_COARSE:
1862 case FS_OPCODE_DDX_FINE:
1863 generate_ddx(inst->opcode, dst, src[0]);
1864 break;
1865 case FS_OPCODE_DDY_COARSE:
1866 case FS_OPCODE_DDY_FINE:
1867 assert(src[1].file == BRW_IMMEDIATE_VALUE);
1868 generate_ddy(inst->opcode, dst, src[0], src[1].dw1.ud);
1869 break;
1870
1871 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1872 generate_scratch_write(inst, src[0]);
1873 break;
1874
1875 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1876 generate_scratch_read(inst, dst);
1877 break;
1878
1879 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1880 generate_scratch_read_gen7(inst, dst);
1881 break;
1882
1883 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1884 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1885 break;
1886
1887 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1888 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1889 break;
1890
1891 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1892 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1893 break;
1894
1895 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1896 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1897 break;
1898
1899 case FS_OPCODE_REP_FB_WRITE:
1900 case FS_OPCODE_FB_WRITE:
1901 generate_fb_write(inst, src[0]);
1902 break;
1903
1904 case FS_OPCODE_BLORP_FB_WRITE:
1905 generate_blorp_fb_write(inst);
1906 break;
1907
1908 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1909 generate_mov_dispatch_to_flags(inst);
1910 break;
1911
1912 case FS_OPCODE_DISCARD_JUMP:
1913 generate_discard_jump(inst);
1914 break;
1915
1916 case SHADER_OPCODE_SHADER_TIME_ADD:
1917 generate_shader_time_add(inst, src[0], src[1], src[2]);
1918 break;
1919
1920 case SHADER_OPCODE_UNTYPED_ATOMIC:
1921 generate_untyped_atomic(inst, dst, src[0], src[1], src[2]);
1922 break;
1923
1924 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1925 generate_untyped_surface_read(inst, dst, src[0], src[1]);
1926 break;
1927
1928 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1929 generate_set_simd4x2_offset(inst, dst, src[0]);
1930 break;
1931
1932 case FS_OPCODE_SET_OMASK:
1933 generate_set_omask(inst, dst, src[0]);
1934 break;
1935
1936 case FS_OPCODE_SET_SAMPLE_ID:
1937 generate_set_sample_id(inst, dst, src[0], src[1]);
1938 break;
1939
1940 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1941 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1942 break;
1943
1944 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1945 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1946 generate_unpack_half_2x16_split(inst, dst, src[0]);
1947 break;
1948
1949 case FS_OPCODE_PLACEHOLDER_HALT:
1950 /* This is the place where the final HALT needs to be inserted if
1951 * we've emitted any discards. If not, this will emit no code.
1952 */
1953 if (!patch_discard_jumps_to_fb_writes()) {
1954 if (unlikely(debug_flag)) {
1955 annotation.ann_count--;
1956 }
1957 }
1958 break;
1959
1960 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
1961 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1962 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
1963 break;
1964
1965 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
1966 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1967 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
1968 break;
1969
1970 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
1971 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1972 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
1973 break;
1974
1975 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
1976 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1977 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
1978 break;
1979
1980 default:
1981 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1982 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1983 opcode_descs[inst->opcode].name);
1984 } else {
1985 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1986 }
1987 abort();
1988
1989 case SHADER_OPCODE_LOAD_PAYLOAD:
1990 unreachable("Should be lowered by lower_load_payload()");
1991 }
1992
1993 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1994 assert(p->next_insn_offset == last_insn_offset + 16 ||
1995 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1996 "emitting more than 1 instruction");
1997
1998 brw_inst *last = &p->store[last_insn_offset / 16];
1999
2000 if (inst->conditional_mod)
2001 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
2002 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
2003 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
2004 }
2005 }
2006
2007 brw_set_uip_jip(p);
2008 annotation_finalize(&annotation, p->next_insn_offset);
2009
2010 int before_size = p->next_insn_offset - start_offset;
2011 brw_compact_instructions(p, start_offset, annotation.ann_count,
2012 annotation.ann);
2013 int after_size = p->next_insn_offset - start_offset;
2014
2015 if (unlikely(debug_flag)) {
2016 if (shader_prog) {
2017 fprintf(stderr,
2018 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
2019 shader_prog->Label ? shader_prog->Label : "unnamed",
2020 shader_prog->Name, dispatch_width);
2021 } else if (prog) {
2022 fprintf(stderr,
2023 "Native code for fragment program %d (SIMD%d dispatch):\n",
2024 prog->Id, dispatch_width);
2025 } else {
2026 fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
2027 dispatch_width);
2028 }
2029 fprintf(stderr, "SIMD%d shader: %d instructions. %d loops. Compacted %d to %d"
2030 " bytes (%.0f%%)\n",
2031 dispatch_width, before_size / 16, loop_count, before_size, after_size,
2032 100.0f * (before_size - after_size) / before_size);
2033
2034 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
2035 ralloc_free(annotation.ann);
2036 }
2037
2038 return start_offset;
2039 }
2040
2041 const unsigned *
2042 fs_generator::get_assembly(unsigned int *assembly_size)
2043 {
2044 return brw_get_program(p, assembly_size);
2045 }