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i965/fs: extend exec_size halving in the generator
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "brw_eu.h"
31 #include "brw_fs.h"
32 #include "brw_cfg.h"
33 #include "brw_program.h"
34
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case ARF:
40 return BRW_ARCHITECTURE_REGISTER_FILE;
41 case FIXED_GRF:
42 case VGRF:
43 return BRW_GENERAL_REGISTER_FILE;
44 case MRF:
45 return BRW_MESSAGE_REGISTER_FILE;
46 case IMM:
47 return BRW_IMMEDIATE_VALUE;
48 case BAD_FILE:
49 case ATTR:
50 case UNIFORM:
51 unreachable("not reached");
52 }
53 return BRW_ARCHITECTURE_REGISTER_FILE;
54 }
55
56 static struct brw_reg
57 brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
58 {
59 struct brw_reg brw_reg;
60
61 switch (reg->file) {
62 case MRF:
63 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(gen));
64 /* Fallthrough */
65 case VGRF:
66 if (reg->stride == 0) {
67 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
68 } else if (inst->exec_size * reg->stride * type_sz(reg->type) <= 32) {
69 brw_reg = brw_vecn_reg(inst->exec_size, brw_file_from_reg(reg),
70 reg->nr, 0);
71 brw_reg = stride(brw_reg, inst->exec_size * reg->stride,
72 inst->exec_size, reg->stride);
73 } else {
74 /* From the Haswell PRM:
75 *
76 * VertStride must be used to cross GRF register boundaries. This
77 * rule implies that elements within a 'Width' cannot cross GRF
78 * boundaries.
79 *
80 * So, for registers that are large enough, we have to split the exec
81 * size in two and trust the compression state to sort it out.
82 */
83 assert(inst->exec_size / 2 * reg->stride * type_sz(reg->type) <= 32);
84 brw_reg = brw_vecn_reg(inst->exec_size / 2, brw_file_from_reg(reg),
85 reg->nr, 0);
86 brw_reg = stride(brw_reg, inst->exec_size / 2 * reg->stride,
87 inst->exec_size / 2, reg->stride);
88 }
89
90 brw_reg = retype(brw_reg, reg->type);
91 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
92 brw_reg.abs = reg->abs;
93 brw_reg.negate = reg->negate;
94 break;
95 case ARF:
96 case FIXED_GRF:
97 case IMM:
98 brw_reg = reg->as_brw_reg();
99 break;
100 case BAD_FILE:
101 /* Probably unused. */
102 brw_reg = brw_null_reg();
103 break;
104 case ATTR:
105 case UNIFORM:
106 unreachable("not reached");
107 }
108
109 return brw_reg;
110 }
111
112 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
113 void *mem_ctx,
114 const void *key,
115 struct brw_stage_prog_data *prog_data,
116 unsigned promoted_constants,
117 bool runtime_check_aads_emit,
118 gl_shader_stage stage)
119
120 : compiler(compiler), log_data(log_data),
121 devinfo(compiler->devinfo), key(key),
122 prog_data(prog_data),
123 promoted_constants(promoted_constants),
124 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
125 stage(stage), mem_ctx(mem_ctx)
126 {
127 p = rzalloc(mem_ctx, struct brw_codegen);
128 brw_init_codegen(devinfo, p, mem_ctx);
129 }
130
131 fs_generator::~fs_generator()
132 {
133 }
134
135 class ip_record : public exec_node {
136 public:
137 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
138
139 ip_record(int ip)
140 {
141 this->ip = ip;
142 }
143
144 int ip;
145 };
146
147 bool
148 fs_generator::patch_discard_jumps_to_fb_writes()
149 {
150 if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
151 return false;
152
153 int scale = brw_jump_scale(p->devinfo);
154
155 /* There is a somewhat strange undocumented requirement of using
156 * HALT, according to the simulator. If some channel has HALTed to
157 * a particular UIP, then by the end of the program, every channel
158 * must have HALTed to that UIP. Furthermore, the tracking is a
159 * stack, so you can't do the final halt of a UIP after starting
160 * halting to a new UIP.
161 *
162 * Symptoms of not emitting this instruction on actual hardware
163 * included GPU hangs and sparkly rendering on the piglit discard
164 * tests.
165 */
166 brw_inst *last_halt = gen6_HALT(p);
167 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
168 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
169
170 int ip = p->nr_insn;
171
172 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
173 brw_inst *patch = &p->store[patch_ip->ip];
174
175 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
176 /* HALT takes a half-instruction distance from the pre-incremented IP. */
177 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
178 }
179
180 this->discard_halt_patches.make_empty();
181 return true;
182 }
183
184 void
185 fs_generator::fire_fb_write(fs_inst *inst,
186 struct brw_reg payload,
187 struct brw_reg implied_header,
188 GLuint nr)
189 {
190 uint32_t msg_control;
191
192 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
193
194 if (devinfo->gen < 6) {
195 brw_push_insn_state(p);
196 brw_set_default_exec_size(p, BRW_EXECUTE_8);
197 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
198 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
199 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
200 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
201 brw_pop_insn_state(p);
202 }
203
204 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
205 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
206 else if (prog_data->dual_src_blend) {
207 if (!inst->force_sechalf)
208 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
209 else
210 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
211 } else if (inst->exec_size == 16)
212 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
213 else
214 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
215
216 uint32_t surf_index =
217 prog_data->binding_table.render_target_start + inst->target;
218
219 bool last_render_target = inst->eot ||
220 (prog_data->dual_src_blend && dispatch_width == 16);
221
222
223 brw_fb_WRITE(p,
224 dispatch_width,
225 payload,
226 implied_header,
227 msg_control,
228 surf_index,
229 nr,
230 0,
231 inst->eot,
232 last_render_target,
233 inst->header_size != 0);
234
235 brw_mark_surface_used(&prog_data->base, surf_index);
236 }
237
238 void
239 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
240 {
241 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
242 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
243 struct brw_reg implied_header;
244
245 if (devinfo->gen < 8 && !devinfo->is_haswell) {
246 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
247 }
248
249 if (inst->base_mrf >= 0)
250 payload = brw_message_reg(inst->base_mrf);
251
252 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
253 * move, here's g1.
254 */
255 if (inst->header_size != 0) {
256 brw_push_insn_state(p);
257 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
258 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
259 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
260 brw_set_default_flag_reg(p, 0, 0);
261
262 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
263 * present.
264 */
265 if (prog_data->uses_kill) {
266 struct brw_reg pixel_mask;
267
268 if (devinfo->gen >= 6)
269 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
270 else
271 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
272
273 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
274 }
275
276 if (devinfo->gen >= 6) {
277 brw_push_insn_state(p);
278 brw_set_default_exec_size(p, BRW_EXECUTE_16);
279 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
280 brw_MOV(p,
281 retype(payload, BRW_REGISTER_TYPE_UD),
282 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
283 brw_pop_insn_state(p);
284
285 if (inst->target > 0 && key->replicate_alpha) {
286 /* Set "Source0 Alpha Present to RenderTarget" bit in message
287 * header.
288 */
289 brw_OR(p,
290 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
291 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
292 brw_imm_ud(0x1 << 11));
293 }
294
295 if (inst->target > 0) {
296 /* Set the render target index for choosing BLEND_STATE. */
297 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
298 BRW_REGISTER_TYPE_UD),
299 brw_imm_ud(inst->target));
300 }
301
302 /* Set computes stencil to render target */
303 if (prog_data->computed_stencil) {
304 brw_OR(p,
305 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
306 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
307 brw_imm_ud(0x1 << 14));
308 }
309
310 implied_header = brw_null_reg();
311 } else {
312 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
313 }
314
315 brw_pop_insn_state(p);
316 } else {
317 implied_header = brw_null_reg();
318 }
319
320 if (!runtime_check_aads_emit) {
321 fire_fb_write(inst, payload, implied_header, inst->mlen);
322 } else {
323 /* This can only happen in gen < 6 */
324 assert(devinfo->gen < 6);
325
326 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
327
328 /* Check runtime bit to detect if we have to send AA data or not */
329 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
330 brw_AND(p,
331 v1_null_ud,
332 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
333 brw_imm_ud(1<<26));
334 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
335
336 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
337 brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
338 {
339 /* Don't send AA data */
340 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
341 }
342 brw_land_fwd_jump(p, jmp);
343 fire_fb_write(inst, payload, implied_header, inst->mlen);
344 }
345 }
346
347 void
348 fs_generator::generate_mov_indirect(fs_inst *inst,
349 struct brw_reg dst,
350 struct brw_reg reg,
351 struct brw_reg indirect_byte_offset)
352 {
353 assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD);
354 assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE);
355
356 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
357
358 if (indirect_byte_offset.file == BRW_IMMEDIATE_VALUE) {
359 imm_byte_offset += indirect_byte_offset.ud;
360
361 reg.nr = imm_byte_offset / REG_SIZE;
362 reg.subnr = imm_byte_offset % REG_SIZE;
363 brw_MOV(p, dst, reg);
364 } else {
365 /* Prior to Broadwell, there are only 8 address registers. */
366 assert(inst->exec_size == 8 || devinfo->gen >= 8);
367
368 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
369 struct brw_reg addr = vec8(brw_address_reg(0));
370
371 /* The destination stride of an instruction (in bytes) must be greater
372 * than or equal to the size of the rest of the instruction. Since the
373 * address register is of type UW, we can't use a D-type instruction.
374 * In order to get around this, re retype to UW and use a stride.
375 */
376 indirect_byte_offset =
377 retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);
378
379 struct brw_reg ind_src;
380 if (devinfo->gen < 8) {
381 /* From the Haswell PRM section "Register Region Restrictions":
382 *
383 * "The lower bits of the AddressImmediate must not overflow to
384 * change the register address. The lower 5 bits of Address
385 * Immediate when added to lower 5 bits of address register gives
386 * the sub-register offset. The upper bits of Address Immediate
387 * when added to upper bits of address register gives the register
388 * address. Any overflow from sub-register offset is dropped."
389 *
390 * This restriction is only listed in the Haswell PRM but emperical
391 * testing indicates that it applies on all older generations and is
392 * lifted on Broadwell.
393 *
394 * Since the indirect may cause us to cross a register boundary, this
395 * makes the base offset almost useless. We could try and do
396 * something clever where we use a actual base offset if
397 * base_offset % 32 == 0 but that would mean we were generating
398 * different code depending on the base offset. Instead, for the
399 * sake of consistency, we'll just do the add ourselves.
400 */
401 brw_ADD(p, addr, indirect_byte_offset, brw_imm_uw(imm_byte_offset));
402 ind_src = brw_VxH_indirect(0, 0);
403 } else {
404 brw_MOV(p, addr, indirect_byte_offset);
405 ind_src = brw_VxH_indirect(0, imm_byte_offset);
406 }
407
408 brw_inst *mov = brw_MOV(p, dst, retype(ind_src, dst.type));
409
410 if (devinfo->gen == 6 && dst.file == BRW_MESSAGE_REGISTER_FILE &&
411 !inst->get_next()->is_tail_sentinel() &&
412 ((fs_inst *)inst->get_next())->mlen > 0) {
413 /* From the Sandybridge PRM:
414 *
415 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
416 * instruction that “indexed/indirect” source AND is followed by a
417 * send, the instruction requires a “Switch”. This is to avoid
418 * race condition where send may dispatch before MRF is updated."
419 */
420 brw_inst_set_thread_control(devinfo, mov, BRW_THREAD_SWITCH);
421 }
422 }
423 }
424
425 void
426 fs_generator::generate_urb_read(fs_inst *inst,
427 struct brw_reg dst,
428 struct brw_reg header)
429 {
430 assert(header.file == BRW_GENERAL_REGISTER_FILE);
431 assert(header.type == BRW_REGISTER_TYPE_UD);
432
433 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
434 brw_set_dest(p, send, dst);
435 brw_set_src0(p, send, header);
436 brw_set_src1(p, send, brw_imm_ud(0u));
437
438 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
439 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
440
441 if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
442 brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
443
444 brw_inst_set_mlen(p->devinfo, send, inst->mlen);
445 brw_inst_set_rlen(p->devinfo, send, inst->regs_written);
446 brw_inst_set_header_present(p->devinfo, send, true);
447 brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
448 }
449
450 void
451 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
452 {
453 brw_inst *insn;
454
455 insn = brw_next_insn(p, BRW_OPCODE_SEND);
456
457 brw_set_dest(p, insn, brw_null_reg());
458 brw_set_src0(p, insn, payload);
459 brw_set_src1(p, insn, brw_imm_d(0));
460
461 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
462 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
463
464 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
465 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
466 brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
467
468 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
469 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
470 brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
471
472 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
473 brw_inst_set_rlen(p->devinfo, insn, 0);
474 brw_inst_set_eot(p->devinfo, insn, inst->eot);
475 brw_inst_set_header_present(p->devinfo, insn, true);
476 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
477 }
478
479 void
480 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
481 {
482 struct brw_inst *insn;
483
484 insn = brw_next_insn(p, BRW_OPCODE_SEND);
485
486 brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW));
487 brw_set_src0(p, insn, payload);
488 brw_set_src1(p, insn, brw_imm_d(0));
489
490 /* Terminate a compute shader by sending a message to the thread spawner.
491 */
492 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
493 brw_inst_set_mlen(devinfo, insn, 1);
494 brw_inst_set_rlen(devinfo, insn, 0);
495 brw_inst_set_eot(devinfo, insn, inst->eot);
496 brw_inst_set_header_present(devinfo, insn, false);
497
498 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
499 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
500
501 /* Note that even though the thread has a URB resource associated with it,
502 * we set the "do not dereference URB" bit, because the URB resource is
503 * managed by the fixed-function unit, so it will free it automatically.
504 */
505 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
506
507 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
508 }
509
510 void
511 fs_generator::generate_stencil_ref_packing(fs_inst *inst,
512 struct brw_reg dst,
513 struct brw_reg src)
514 {
515 assert(dispatch_width == 8);
516 assert(devinfo->gen >= 9);
517
518 /* Stencil value updates are provided in 8 slots of 1 byte per slot.
519 * Presumably, in order to save memory bandwidth, the stencil reference
520 * values written from the FS need to be packed into 2 dwords (this makes
521 * sense because the stencil values are limited to 1 byte each and a SIMD8
522 * send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
523 *
524 * The spec is confusing here because in the payload definition of MDP_RTW_S8
525 * (Message Data Payload for Render Target Writes with Stencil 8b) the
526 * stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
527 * dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
528 * packed values specified above and diagrammed below:
529 *
530 * 31 0
531 * --------------------------------
532 * DW | |
533 * 2-7 | IGNORED |
534 * | |
535 * --------------------------------
536 * DW1 | STC | STC | STC | STC |
537 * | slot7 | slot6 | slot5 | slot4|
538 * --------------------------------
539 * DW0 | STC | STC | STC | STC |
540 * | slot3 | slot2 | slot1 | slot0|
541 * --------------------------------
542 */
543
544 src.vstride = BRW_VERTICAL_STRIDE_4;
545 src.width = BRW_WIDTH_1;
546 src.hstride = BRW_HORIZONTAL_STRIDE_0;
547 assert(src.type == BRW_REGISTER_TYPE_UB);
548 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UB), src);
549 }
550
551 void
552 fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
553 {
554 brw_barrier(p, src);
555 brw_WAIT(p);
556 }
557
558 void
559 fs_generator::generate_blorp_fb_write(fs_inst *inst, struct brw_reg payload)
560 {
561 brw_fb_WRITE(p,
562 16 /* dispatch_width */,
563 inst->base_mrf >= 0 ?
564 brw_message_reg(inst->base_mrf) : payload,
565 brw_null_reg(),
566 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
567 inst->target,
568 inst->mlen,
569 0,
570 true,
571 true,
572 inst->header_size != 0);
573 }
574
575 void
576 fs_generator::generate_linterp(fs_inst *inst,
577 struct brw_reg dst, struct brw_reg *src)
578 {
579 /* PLN reads:
580 * / in SIMD16 \
581 * -----------------------------------
582 * | src1+0 | src1+1 | src1+2 | src1+3 |
583 * |-----------------------------------|
584 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
585 * -----------------------------------
586 *
587 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
588 *
589 * -----------------------------------
590 * | src1+0 | src1+1 | src1+2 | src1+3 |
591 * |-----------------------------------|
592 * |(x0, x1)|(y0, y1)| | | in SIMD8
593 * |-----------------------------------|
594 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
595 * -----------------------------------
596 *
597 * See also: emit_interpolation_setup_gen4().
598 */
599 struct brw_reg delta_x = src[0];
600 struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
601 struct brw_reg interp = src[1];
602
603 if (devinfo->has_pln &&
604 (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
605 brw_PLN(p, dst, interp, delta_x);
606 } else {
607 brw_LINE(p, brw_null_reg(), interp, delta_x);
608 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
609 }
610 }
611
612 void
613 fs_generator::generate_math_gen6(fs_inst *inst,
614 struct brw_reg dst,
615 struct brw_reg src0,
616 struct brw_reg src1)
617 {
618 int op = brw_math_function(inst->opcode);
619 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
620
621 if (dispatch_width == 8) {
622 gen6_math(p, dst, op, src0, src1);
623 } else if (dispatch_width == 16) {
624 brw_push_insn_state(p);
625 brw_set_default_exec_size(p, BRW_EXECUTE_8);
626 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
627 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
628 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
629 gen6_math(p, sechalf(dst), op, sechalf(src0),
630 binop ? sechalf(src1) : brw_null_reg());
631 brw_pop_insn_state(p);
632 }
633 }
634
635 void
636 fs_generator::generate_math_gen4(fs_inst *inst,
637 struct brw_reg dst,
638 struct brw_reg src)
639 {
640 int op = brw_math_function(inst->opcode);
641
642 assert(inst->mlen >= 1);
643
644 if (dispatch_width == 8) {
645 gen4_math(p, dst,
646 op,
647 inst->base_mrf, src,
648 BRW_MATH_PRECISION_FULL);
649 } else if (dispatch_width == 16) {
650 brw_set_default_exec_size(p, BRW_EXECUTE_8);
651 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
652 gen4_math(p, firsthalf(dst),
653 op,
654 inst->base_mrf, firsthalf(src),
655 BRW_MATH_PRECISION_FULL);
656 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
657 gen4_math(p, sechalf(dst),
658 op,
659 inst->base_mrf + 1, sechalf(src),
660 BRW_MATH_PRECISION_FULL);
661
662 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
663 }
664 }
665
666 void
667 fs_generator::generate_math_g45(fs_inst *inst,
668 struct brw_reg dst,
669 struct brw_reg src)
670 {
671 if (inst->opcode == SHADER_OPCODE_POW ||
672 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
673 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
674 generate_math_gen4(inst, dst, src);
675 return;
676 }
677
678 int op = brw_math_function(inst->opcode);
679
680 assert(inst->mlen >= 1);
681
682 gen4_math(p, dst,
683 op,
684 inst->base_mrf, src,
685 BRW_MATH_PRECISION_FULL);
686 }
687
688 void
689 fs_generator::generate_get_buffer_size(fs_inst *inst,
690 struct brw_reg dst,
691 struct brw_reg src,
692 struct brw_reg surf_index)
693 {
694 assert(devinfo->gen >= 7);
695 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
696
697 uint32_t simd_mode;
698 int rlen = 4;
699
700 switch (inst->exec_size) {
701 case 8:
702 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
703 break;
704 case 16:
705 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
706 break;
707 default:
708 unreachable("Invalid width for texture instruction");
709 }
710
711 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
712 rlen = 8;
713 dst = vec16(dst);
714 }
715
716 brw_SAMPLE(p,
717 retype(dst, BRW_REGISTER_TYPE_UW),
718 inst->base_mrf,
719 src,
720 surf_index.ud,
721 0,
722 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
723 rlen, /* response length */
724 inst->mlen,
725 inst->header_size > 0,
726 simd_mode,
727 BRW_SAMPLER_RETURN_FORMAT_SINT32);
728
729 brw_mark_surface_used(prog_data, surf_index.ud);
730 }
731
732 void
733 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
734 struct brw_reg surface_index,
735 struct brw_reg sampler_index)
736 {
737 int msg_type = -1;
738 uint32_t simd_mode;
739 uint32_t return_format;
740 bool is_combined_send = inst->eot;
741
742 switch (dst.type) {
743 case BRW_REGISTER_TYPE_D:
744 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
745 break;
746 case BRW_REGISTER_TYPE_UD:
747 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
748 break;
749 default:
750 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
751 break;
752 }
753
754 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
755 * is set as part of the message descriptor. On gen4, the PRM seems to
756 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
757 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
758 * gone from the message descriptor entirely and you just get UINT32 all
759 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
760 * just stomp it to UINT32 all the time.
761 */
762 if (inst->opcode == SHADER_OPCODE_TXS)
763 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
764
765 switch (inst->exec_size) {
766 case 8:
767 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
768 break;
769 case 16:
770 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
771 break;
772 default:
773 unreachable("Invalid width for texture instruction");
774 }
775
776 if (devinfo->gen >= 5) {
777 switch (inst->opcode) {
778 case SHADER_OPCODE_TEX:
779 if (inst->shadow_compare) {
780 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
781 } else {
782 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
783 }
784 break;
785 case FS_OPCODE_TXB:
786 if (inst->shadow_compare) {
787 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
788 } else {
789 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
790 }
791 break;
792 case SHADER_OPCODE_TXL:
793 if (inst->shadow_compare) {
794 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
795 } else {
796 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
797 }
798 break;
799 case SHADER_OPCODE_TXS:
800 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
801 break;
802 case SHADER_OPCODE_TXD:
803 if (inst->shadow_compare) {
804 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
805 assert(devinfo->gen >= 8 || devinfo->is_haswell);
806 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
807 } else {
808 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
809 }
810 break;
811 case SHADER_OPCODE_TXF:
812 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
813 break;
814 case SHADER_OPCODE_TXF_CMS_W:
815 assert(devinfo->gen >= 9);
816 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
817 break;
818 case SHADER_OPCODE_TXF_CMS:
819 if (devinfo->gen >= 7)
820 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
821 else
822 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
823 break;
824 case SHADER_OPCODE_TXF_UMS:
825 assert(devinfo->gen >= 7);
826 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
827 break;
828 case SHADER_OPCODE_TXF_MCS:
829 assert(devinfo->gen >= 7);
830 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
831 break;
832 case SHADER_OPCODE_LOD:
833 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
834 break;
835 case SHADER_OPCODE_TG4:
836 if (inst->shadow_compare) {
837 assert(devinfo->gen >= 7);
838 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
839 } else {
840 assert(devinfo->gen >= 6);
841 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
842 }
843 break;
844 case SHADER_OPCODE_TG4_OFFSET:
845 assert(devinfo->gen >= 7);
846 if (inst->shadow_compare) {
847 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
848 } else {
849 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
850 }
851 break;
852 case SHADER_OPCODE_SAMPLEINFO:
853 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
854 break;
855 default:
856 unreachable("not reached");
857 }
858 } else {
859 switch (inst->opcode) {
860 case SHADER_OPCODE_TEX:
861 /* Note that G45 and older determines shadow compare and dispatch width
862 * from message length for most messages.
863 */
864 if (inst->exec_size == 8) {
865 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
866 if (inst->shadow_compare) {
867 assert(inst->mlen == 6);
868 } else {
869 assert(inst->mlen <= 4);
870 }
871 } else {
872 if (inst->shadow_compare) {
873 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
874 assert(inst->mlen == 9);
875 } else {
876 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
877 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
878 }
879 }
880 break;
881 case FS_OPCODE_TXB:
882 if (inst->shadow_compare) {
883 assert(inst->exec_size == 8);
884 assert(inst->mlen == 6);
885 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
886 } else {
887 assert(inst->mlen == 9);
888 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
889 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
890 }
891 break;
892 case SHADER_OPCODE_TXL:
893 if (inst->shadow_compare) {
894 assert(inst->exec_size == 8);
895 assert(inst->mlen == 6);
896 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
897 } else {
898 assert(inst->mlen == 9);
899 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
900 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
901 }
902 break;
903 case SHADER_OPCODE_TXD:
904 /* There is no sample_d_c message; comparisons are done manually */
905 assert(inst->exec_size == 8);
906 assert(inst->mlen == 7 || inst->mlen == 10);
907 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
908 break;
909 case SHADER_OPCODE_TXF:
910 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
911 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
912 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
913 break;
914 case SHADER_OPCODE_TXS:
915 assert(inst->mlen == 3);
916 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
917 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
918 break;
919 default:
920 unreachable("not reached");
921 }
922 }
923 assert(msg_type != -1);
924
925 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
926 dst = vec16(dst);
927 }
928
929 assert(devinfo->gen < 7 || inst->header_size == 0 ||
930 src.file == BRW_GENERAL_REGISTER_FILE);
931
932 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
933
934 /* Load the message header if present. If there's a texture offset,
935 * we need to set it up explicitly and load the offset bitfield.
936 * Otherwise, we can use an implied move from g0 to the first message reg.
937 */
938 if (inst->header_size != 0) {
939 if (devinfo->gen < 6 && !inst->offset) {
940 /* Set up an implied move from g0 to the MRF. */
941 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
942 } else {
943 struct brw_reg header_reg;
944
945 if (devinfo->gen >= 7) {
946 header_reg = src;
947 } else {
948 assert(inst->base_mrf != -1);
949 header_reg = brw_message_reg(inst->base_mrf);
950 }
951
952 brw_push_insn_state(p);
953 brw_set_default_exec_size(p, BRW_EXECUTE_8);
954 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
955 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
956 /* Explicitly set up the message header by copying g0 to the MRF. */
957 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
958
959 if (inst->offset) {
960 /* Set the offset bits in DWord 2. */
961 brw_MOV(p, get_element_ud(header_reg, 2),
962 brw_imm_ud(inst->offset));
963 } else if (stage != MESA_SHADER_VERTEX &&
964 stage != MESA_SHADER_FRAGMENT) {
965 /* The vertex and fragment stages have g0.2 set to 0, so
966 * header0.2 is 0 when g0 is copied. Other stages may not, so we
967 * must set it to 0 to avoid setting undesirable bits in the
968 * message.
969 */
970 brw_MOV(p, get_element_ud(header_reg, 2), brw_imm_ud(0));
971 }
972
973 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
974 brw_pop_insn_state(p);
975 }
976 }
977
978 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
979 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
980 ? prog_data->binding_table.gather_texture_start
981 : prog_data->binding_table.texture_start;
982
983 if (surface_index.file == BRW_IMMEDIATE_VALUE &&
984 sampler_index.file == BRW_IMMEDIATE_VALUE) {
985 uint32_t surface = surface_index.ud;
986 uint32_t sampler = sampler_index.ud;
987
988 brw_SAMPLE(p,
989 retype(dst, BRW_REGISTER_TYPE_UW),
990 inst->base_mrf,
991 src,
992 surface + base_binding_table_index,
993 sampler % 16,
994 msg_type,
995 inst->regs_written,
996 inst->mlen,
997 inst->header_size != 0,
998 simd_mode,
999 return_format);
1000
1001 brw_mark_surface_used(prog_data, surface + base_binding_table_index);
1002 } else {
1003 /* Non-const sampler index */
1004
1005 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1006 struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
1007 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
1008
1009 brw_push_insn_state(p);
1010 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1011 brw_set_default_access_mode(p, BRW_ALIGN_1);
1012
1013 if (memcmp(&surface_reg, &sampler_reg, sizeof(surface_reg)) == 0) {
1014 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
1015 } else {
1016 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
1017 brw_OR(p, addr, addr, surface_reg);
1018 }
1019 if (base_binding_table_index)
1020 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
1021 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
1022
1023 brw_pop_insn_state(p);
1024
1025 /* dst = send(offset, a0.0 | <descriptor>) */
1026 brw_inst *insn = brw_send_indirect_message(
1027 p, BRW_SFID_SAMPLER, dst, src, addr);
1028 brw_set_sampler_message(p, insn,
1029 0 /* surface */,
1030 0 /* sampler */,
1031 msg_type,
1032 inst->regs_written,
1033 inst->mlen /* mlen */,
1034 inst->header_size != 0 /* header */,
1035 simd_mode,
1036 return_format);
1037
1038 /* visitor knows more than we do about the surface limit required,
1039 * so has already done marking.
1040 */
1041 }
1042
1043 if (is_combined_send) {
1044 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
1045 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
1046 }
1047 }
1048
1049
1050 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1051 * looking like:
1052 *
1053 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1054 *
1055 * Ideally, we want to produce:
1056 *
1057 * DDX DDY
1058 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1059 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1060 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1061 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1062 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1063 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1064 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1065 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1066 *
1067 * and add another set of two more subspans if in 16-pixel dispatch mode.
1068 *
1069 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1070 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1071 * pair. But the ideal approximation may impose a huge performance cost on
1072 * sample_d. On at least Haswell, sample_d instruction does some
1073 * optimizations if the same LOD is used for all pixels in the subspan.
1074 *
1075 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1076 * appropriate swizzling.
1077 */
1078 void
1079 fs_generator::generate_ddx(enum opcode opcode,
1080 struct brw_reg dst, struct brw_reg src)
1081 {
1082 unsigned vstride, width;
1083
1084 if (opcode == FS_OPCODE_DDX_FINE) {
1085 /* produce accurate derivatives */
1086 vstride = BRW_VERTICAL_STRIDE_2;
1087 width = BRW_WIDTH_2;
1088 } else {
1089 /* replicate the derivative at the top-left pixel to other pixels */
1090 vstride = BRW_VERTICAL_STRIDE_4;
1091 width = BRW_WIDTH_4;
1092 }
1093
1094 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
1095 src.negate, src.abs,
1096 BRW_REGISTER_TYPE_F,
1097 vstride,
1098 width,
1099 BRW_HORIZONTAL_STRIDE_0,
1100 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1101 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1102 src.negate, src.abs,
1103 BRW_REGISTER_TYPE_F,
1104 vstride,
1105 width,
1106 BRW_HORIZONTAL_STRIDE_0,
1107 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1108 brw_ADD(p, dst, src0, negate(src1));
1109 }
1110
1111 /* The negate_value boolean is used to negate the derivative computation for
1112 * FBOs, since they place the origin at the upper left instead of the lower
1113 * left.
1114 */
1115 void
1116 fs_generator::generate_ddy(enum opcode opcode,
1117 struct brw_reg dst, struct brw_reg src,
1118 bool negate_value)
1119 {
1120 if (opcode == FS_OPCODE_DDY_FINE) {
1121 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
1122 * Region Restrictions):
1123 *
1124 * In Align16 access mode, SIMD16 is not allowed for DW operations
1125 * and SIMD8 is not allowed for DF operations.
1126 *
1127 * In this context, "DW operations" means "operations acting on 32-bit
1128 * values", so it includes operations on floats.
1129 *
1130 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
1131 * (Instruction Compression -> Rules and Restrictions):
1132 *
1133 * A compressed instruction must be in Align1 access mode. Align16
1134 * mode instructions cannot be compressed.
1135 *
1136 * Similar text exists in the g45 PRM.
1137 *
1138 * Empirically, compressed align16 instructions using odd register
1139 * numbers don't appear to work on Sandybridge either.
1140 *
1141 * On these platforms, if we're building a SIMD16 shader, we need to
1142 * manually unroll to a pair of SIMD8 instructions.
1143 */
1144 bool unroll_to_simd8 =
1145 (dispatch_width == 16 &&
1146 (devinfo->gen == 4 || devinfo->gen == 6 ||
1147 (devinfo->gen == 7 && !devinfo->is_haswell)));
1148
1149 /* produce accurate derivatives */
1150 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1151 src.negate, src.abs,
1152 BRW_REGISTER_TYPE_F,
1153 BRW_VERTICAL_STRIDE_4,
1154 BRW_WIDTH_4,
1155 BRW_HORIZONTAL_STRIDE_1,
1156 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
1157 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1158 src.negate, src.abs,
1159 BRW_REGISTER_TYPE_F,
1160 BRW_VERTICAL_STRIDE_4,
1161 BRW_WIDTH_4,
1162 BRW_HORIZONTAL_STRIDE_1,
1163 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
1164 brw_push_insn_state(p);
1165 brw_set_default_access_mode(p, BRW_ALIGN_16);
1166 if (unroll_to_simd8) {
1167 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1168 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1169 if (negate_value) {
1170 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
1171 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1172 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
1173 } else {
1174 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
1175 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1176 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
1177 }
1178 } else {
1179 if (negate_value)
1180 brw_ADD(p, dst, src1, negate(src0));
1181 else
1182 brw_ADD(p, dst, src0, negate(src1));
1183 }
1184 brw_pop_insn_state(p);
1185 } else {
1186 /* replicate the derivative at the top-left pixel to other pixels */
1187 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1188 src.negate, src.abs,
1189 BRW_REGISTER_TYPE_F,
1190 BRW_VERTICAL_STRIDE_4,
1191 BRW_WIDTH_4,
1192 BRW_HORIZONTAL_STRIDE_0,
1193 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1194 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
1195 src.negate, src.abs,
1196 BRW_REGISTER_TYPE_F,
1197 BRW_VERTICAL_STRIDE_4,
1198 BRW_WIDTH_4,
1199 BRW_HORIZONTAL_STRIDE_0,
1200 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1201 if (negate_value)
1202 brw_ADD(p, dst, src1, negate(src0));
1203 else
1204 brw_ADD(p, dst, src0, negate(src1));
1205 }
1206 }
1207
1208 void
1209 fs_generator::generate_discard_jump(fs_inst *inst)
1210 {
1211 assert(devinfo->gen >= 6);
1212
1213 /* This HALT will be patched up at FB write time to point UIP at the end of
1214 * the program, and at brw_uip_jip() JIP will be set to the end of the
1215 * current block (or the program).
1216 */
1217 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1218
1219 brw_push_insn_state(p);
1220 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1221 gen6_HALT(p);
1222 brw_pop_insn_state(p);
1223 }
1224
1225 void
1226 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1227 {
1228 assert(inst->mlen != 0);
1229
1230 brw_MOV(p,
1231 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
1232 retype(src, BRW_REGISTER_TYPE_UD));
1233 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1234 inst->exec_size / 8, inst->offset);
1235 }
1236
1237 void
1238 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1239 {
1240 assert(inst->mlen != 0);
1241
1242 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1243 inst->exec_size / 8, inst->offset);
1244 }
1245
1246 void
1247 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1248 {
1249 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1250 }
1251
1252 void
1253 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1254 struct brw_reg dst,
1255 struct brw_reg index,
1256 struct brw_reg offset)
1257 {
1258 assert(inst->mlen != 0);
1259
1260 assert(index.file == BRW_IMMEDIATE_VALUE &&
1261 index.type == BRW_REGISTER_TYPE_UD);
1262 uint32_t surf_index = index.ud;
1263
1264 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1265 offset.type == BRW_REGISTER_TYPE_UD);
1266 uint32_t read_offset = offset.ud;
1267
1268 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1269 read_offset, surf_index);
1270 }
1271
1272 void
1273 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1274 struct brw_reg dst,
1275 struct brw_reg index,
1276 struct brw_reg offset)
1277 {
1278 assert(index.type == BRW_REGISTER_TYPE_UD);
1279
1280 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1281 /* Reference just the dword we need, to avoid angering validate_reg(). */
1282 offset = brw_vec1_grf(offset.nr, 0);
1283
1284 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1285 * the destination loaded consecutively from the same offset (which appears
1286 * in the first component, and the rest are ignored).
1287 */
1288 dst.width = BRW_WIDTH_4;
1289
1290 struct brw_reg src = offset;
1291 bool header_present = false;
1292
1293 if (devinfo->gen >= 9) {
1294 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1295 src = retype(brw_vec4_grf(offset.nr, 0), BRW_REGISTER_TYPE_UD);
1296 header_present = true;
1297
1298 brw_push_insn_state(p);
1299 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1300 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1301 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1302 brw_set_default_access_mode(p, BRW_ALIGN_1);
1303
1304 brw_MOV(p, get_element_ud(src, 2),
1305 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1306 brw_pop_insn_state(p);
1307 }
1308
1309 if (index.file == BRW_IMMEDIATE_VALUE) {
1310
1311 uint32_t surf_index = index.ud;
1312
1313 brw_push_insn_state(p);
1314 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1315 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1316 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1317 brw_inst_set_exec_size(devinfo, send, BRW_EXECUTE_4);
1318 brw_pop_insn_state(p);
1319
1320 brw_set_dest(p, send, dst);
1321 brw_set_src0(p, send, src);
1322 brw_set_sampler_message(p, send,
1323 surf_index,
1324 0, /* LD message ignores sampler unit */
1325 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1326 1, /* rlen */
1327 inst->mlen,
1328 header_present,
1329 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1330 0);
1331 } else {
1332
1333 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1334
1335 brw_push_insn_state(p);
1336 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1337 brw_set_default_access_mode(p, BRW_ALIGN_1);
1338
1339 /* a0.0 = surf_index & 0xff */
1340 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1341 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1342 brw_set_dest(p, insn_and, addr);
1343 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1344 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1345
1346 /* dst = send(payload, a0.0 | <descriptor>) */
1347 brw_inst *insn = brw_send_indirect_message(
1348 p, BRW_SFID_SAMPLER, dst, src, addr);
1349 brw_set_sampler_message(p, insn,
1350 0,
1351 0, /* LD message ignores sampler unit */
1352 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1353 1, /* rlen */
1354 inst->mlen,
1355 header_present,
1356 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1357 0);
1358
1359 brw_pop_insn_state(p);
1360 }
1361 }
1362
1363 void
1364 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1365 struct brw_reg dst,
1366 struct brw_reg index,
1367 struct brw_reg offset)
1368 {
1369 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1370 assert(inst->header_size != 0);
1371 assert(inst->mlen);
1372
1373 assert(index.file == BRW_IMMEDIATE_VALUE &&
1374 index.type == BRW_REGISTER_TYPE_UD);
1375 uint32_t surf_index = index.ud;
1376
1377 uint32_t simd_mode, rlen, msg_type;
1378 if (dispatch_width == 16) {
1379 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1380 rlen = 8;
1381 } else {
1382 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1383 rlen = 4;
1384 }
1385
1386 if (devinfo->gen >= 5)
1387 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1388 else {
1389 /* We always use the SIMD16 message so that we only have to load U, and
1390 * not V or R.
1391 */
1392 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1393 assert(inst->mlen == 3);
1394 assert(inst->regs_written == 8);
1395 rlen = 8;
1396 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1397 }
1398
1399 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1400 BRW_REGISTER_TYPE_D);
1401 brw_MOV(p, offset_mrf, offset);
1402
1403 struct brw_reg header = brw_vec8_grf(0, 0);
1404 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1405
1406 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1407 brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
1408 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1409 brw_set_src0(p, send, header);
1410 if (devinfo->gen < 6)
1411 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1412
1413 /* Our surface is set up as floats, regardless of what actual data is
1414 * stored in it.
1415 */
1416 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1417 brw_set_sampler_message(p, send,
1418 surf_index,
1419 0, /* sampler (unused) */
1420 msg_type,
1421 rlen,
1422 inst->mlen,
1423 inst->header_size != 0,
1424 simd_mode,
1425 return_format);
1426 }
1427
1428 void
1429 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1430 struct brw_reg dst,
1431 struct brw_reg index,
1432 struct brw_reg offset)
1433 {
1434 assert(devinfo->gen >= 7);
1435 /* Varying-offset pull constant loads are treated as a normal expression on
1436 * gen7, so the fact that it's a send message is hidden at the IR level.
1437 */
1438 assert(inst->header_size == 0);
1439 assert(!inst->mlen);
1440 assert(index.type == BRW_REGISTER_TYPE_UD);
1441
1442 uint32_t simd_mode, rlen, mlen;
1443 if (dispatch_width == 16) {
1444 mlen = 2;
1445 rlen = 8;
1446 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1447 } else {
1448 mlen = 1;
1449 rlen = 4;
1450 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1451 }
1452
1453 if (index.file == BRW_IMMEDIATE_VALUE) {
1454
1455 uint32_t surf_index = index.ud;
1456
1457 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1458 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1459 brw_set_src0(p, send, offset);
1460 brw_set_sampler_message(p, send,
1461 surf_index,
1462 0, /* LD message ignores sampler unit */
1463 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1464 rlen,
1465 mlen,
1466 false, /* no header */
1467 simd_mode,
1468 0);
1469
1470 } else {
1471
1472 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1473
1474 brw_push_insn_state(p);
1475 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1476 brw_set_default_access_mode(p, BRW_ALIGN_1);
1477
1478 /* a0.0 = surf_index & 0xff */
1479 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1480 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1481 brw_set_dest(p, insn_and, addr);
1482 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1483 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1484
1485 brw_pop_insn_state(p);
1486
1487 /* dst = send(offset, a0.0 | <descriptor>) */
1488 brw_inst *insn = brw_send_indirect_message(
1489 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1490 offset, addr);
1491 brw_set_sampler_message(p, insn,
1492 0 /* surface */,
1493 0 /* sampler */,
1494 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1495 rlen /* rlen */,
1496 mlen /* mlen */,
1497 false /* header */,
1498 simd_mode,
1499 0);
1500 }
1501 }
1502
1503 /**
1504 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1505 * into the flags register (f0.0).
1506 *
1507 * Used only on Gen6 and above.
1508 */
1509 void
1510 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1511 {
1512 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1513 struct brw_reg dispatch_mask;
1514
1515 if (devinfo->gen >= 6)
1516 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1517 else
1518 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1519
1520 brw_push_insn_state(p);
1521 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1522 brw_MOV(p, flags, dispatch_mask);
1523 brw_pop_insn_state(p);
1524 }
1525
1526 void
1527 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1528 struct brw_reg dst,
1529 struct brw_reg src,
1530 struct brw_reg msg_data,
1531 unsigned msg_type)
1532 {
1533 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1534
1535 brw_pixel_interpolator_query(p,
1536 retype(dst, BRW_REGISTER_TYPE_UW),
1537 src,
1538 inst->pi_noperspective,
1539 msg_type,
1540 msg_data,
1541 inst->mlen,
1542 inst->regs_written);
1543 }
1544
1545
1546 /**
1547 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1548 * sampler LD messages.
1549 *
1550 * We don't want to bake it into the send message's code generation because
1551 * that means we don't get a chance to schedule the instructions.
1552 */
1553 void
1554 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1555 struct brw_reg dst,
1556 struct brw_reg value)
1557 {
1558 assert(value.file == BRW_IMMEDIATE_VALUE);
1559
1560 brw_push_insn_state(p);
1561 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1562 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1563 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1564 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1565 brw_pop_insn_state(p);
1566 }
1567
1568 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1569 * the ADD instruction.
1570 */
1571 void
1572 fs_generator::generate_set_sample_id(fs_inst *inst,
1573 struct brw_reg dst,
1574 struct brw_reg src0,
1575 struct brw_reg src1)
1576 {
1577 assert(dst.type == BRW_REGISTER_TYPE_D ||
1578 dst.type == BRW_REGISTER_TYPE_UD);
1579 assert(src0.type == BRW_REGISTER_TYPE_D ||
1580 src0.type == BRW_REGISTER_TYPE_UD);
1581
1582 struct brw_reg reg = stride(src1, 1, 4, 0);
1583 if (devinfo->gen >= 8 || dispatch_width == 8) {
1584 brw_ADD(p, dst, src0, reg);
1585 } else if (dispatch_width == 16) {
1586 brw_push_insn_state(p);
1587 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1588 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1589 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1590 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1591 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1592 brw_pop_insn_state(p);
1593 }
1594 }
1595
1596 void
1597 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1598 struct brw_reg dst,
1599 struct brw_reg x,
1600 struct brw_reg y)
1601 {
1602 assert(devinfo->gen >= 7);
1603 assert(dst.type == BRW_REGISTER_TYPE_UD);
1604 assert(x.type == BRW_REGISTER_TYPE_F);
1605 assert(y.type == BRW_REGISTER_TYPE_F);
1606
1607 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1608 *
1609 * Because this instruction does not have a 16-bit floating-point type,
1610 * the destination data type must be Word (W).
1611 *
1612 * The destination must be DWord-aligned and specify a horizontal stride
1613 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1614 * each destination channel and the upper word is not modified.
1615 */
1616 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1617
1618 /* Give each 32-bit channel of dst the form below, where "." means
1619 * unchanged.
1620 * 0x....hhhh
1621 */
1622 brw_F32TO16(p, dst_w, y);
1623
1624 /* Now the form:
1625 * 0xhhhh0000
1626 */
1627 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1628
1629 /* And, finally the form of packHalf2x16's output:
1630 * 0xhhhhllll
1631 */
1632 brw_F32TO16(p, dst_w, x);
1633 }
1634
1635 void
1636 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1637 struct brw_reg dst,
1638 struct brw_reg src)
1639 {
1640 assert(devinfo->gen >= 7);
1641 assert(dst.type == BRW_REGISTER_TYPE_F);
1642 assert(src.type == BRW_REGISTER_TYPE_UD);
1643
1644 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1645 *
1646 * Because this instruction does not have a 16-bit floating-point type,
1647 * the source data type must be Word (W). The destination type must be
1648 * F (Float).
1649 */
1650 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1651
1652 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1653 * For the Y case, we wish to access only the upper word; therefore
1654 * a 16-bit subregister offset is needed.
1655 */
1656 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1657 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1658 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1659 src_w.subnr += 2;
1660
1661 brw_F16TO32(p, dst, src_w);
1662 }
1663
1664 void
1665 fs_generator::generate_shader_time_add(fs_inst *inst,
1666 struct brw_reg payload,
1667 struct brw_reg offset,
1668 struct brw_reg value)
1669 {
1670 assert(devinfo->gen >= 7);
1671 brw_push_insn_state(p);
1672 brw_set_default_mask_control(p, true);
1673
1674 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1675 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1676 offset.type);
1677 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1678 value.type);
1679
1680 assert(offset.file == BRW_IMMEDIATE_VALUE);
1681 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1682 value.width = BRW_WIDTH_1;
1683 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1684 value.vstride = BRW_VERTICAL_STRIDE_0;
1685 } else {
1686 assert(value.file == BRW_IMMEDIATE_VALUE);
1687 }
1688
1689 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1690 * case, and we don't really care about squeezing every bit of performance
1691 * out of this path, so we just emit the MOVs from here.
1692 */
1693 brw_MOV(p, payload_offset, offset);
1694 brw_MOV(p, payload_value, value);
1695 brw_shader_time_add(p, payload,
1696 prog_data->binding_table.shader_time_start);
1697 brw_pop_insn_state(p);
1698
1699 brw_mark_surface_used(prog_data,
1700 prog_data->binding_table.shader_time_start);
1701 }
1702
1703 void
1704 fs_generator::enable_debug(const char *shader_name)
1705 {
1706 debug_flag = true;
1707 this->shader_name = shader_name;
1708 }
1709
1710 int
1711 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1712 {
1713 /* align to 64 byte boundary. */
1714 while (p->next_insn_offset % 64)
1715 brw_NOP(p);
1716
1717 this->dispatch_width = dispatch_width;
1718 if (dispatch_width == 16)
1719 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1720
1721 int start_offset = p->next_insn_offset;
1722 int spill_count = 0, fill_count = 0;
1723 int loop_count = 0;
1724
1725 struct annotation_info annotation;
1726 memset(&annotation, 0, sizeof(annotation));
1727
1728 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1729 struct brw_reg src[3], dst;
1730 unsigned int last_insn_offset = p->next_insn_offset;
1731 bool multiple_instructions_emitted = false;
1732
1733 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1734 * "Register Region Restrictions" section: for BDW, SKL:
1735 *
1736 * "A POW/FDIV operation must not be followed by an instruction
1737 * that requires two destination registers."
1738 *
1739 * The documentation is often lacking annotations for Atom parts,
1740 * and empirically this affects CHV as well.
1741 */
1742 if (devinfo->gen >= 8 &&
1743 p->nr_insn > 1 &&
1744 brw_inst_opcode(devinfo, brw_last_inst) == BRW_OPCODE_MATH &&
1745 brw_inst_math_function(devinfo, brw_last_inst) == BRW_MATH_FUNCTION_POW &&
1746 inst->dst.component_size(inst->exec_size) > REG_SIZE) {
1747 brw_NOP(p);
1748 last_insn_offset = p->next_insn_offset;
1749 }
1750
1751 if (unlikely(debug_flag))
1752 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1753
1754 for (unsigned int i = 0; i < inst->sources; i++) {
1755 src[i] = brw_reg_from_fs_reg(inst, &inst->src[i], devinfo->gen);
1756
1757 /* The accumulator result appears to get used for the
1758 * conditional modifier generation. When negating a UD
1759 * value, there is a 33rd bit generated for the sign in the
1760 * accumulator value, so now you can't check, for example,
1761 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1762 */
1763 assert(!inst->conditional_mod ||
1764 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1765 !inst->src[i].negate);
1766 }
1767 dst = brw_reg_from_fs_reg(inst, &inst->dst, devinfo->gen);
1768
1769 brw_set_default_predicate_control(p, inst->predicate);
1770 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1771 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1772 brw_set_default_saturate(p, inst->saturate);
1773 brw_set_default_mask_control(p, inst->force_writemask_all);
1774 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1775 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1776
1777 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1778 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1779
1780 switch (inst->exec_size) {
1781 case 1:
1782 case 2:
1783 case 4:
1784 assert(inst->force_writemask_all);
1785 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1786 break;
1787 case 8:
1788 if (inst->force_sechalf) {
1789 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1790 } else {
1791 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1792 }
1793 break;
1794 case 16:
1795 case 32:
1796 /* If the instruction writes to more than one register, it needs to
1797 * be a "compressed" instruction on Gen <= 5.
1798 */
1799 if (inst->dst.component_size(inst->exec_size) > REG_SIZE)
1800 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1801 else
1802 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1803 break;
1804 default:
1805 unreachable("Invalid instruction width");
1806 }
1807
1808 switch (inst->opcode) {
1809 case BRW_OPCODE_MOV:
1810 brw_MOV(p, dst, src[0]);
1811 break;
1812 case BRW_OPCODE_ADD:
1813 brw_ADD(p, dst, src[0], src[1]);
1814 break;
1815 case BRW_OPCODE_MUL:
1816 brw_MUL(p, dst, src[0], src[1]);
1817 break;
1818 case BRW_OPCODE_AVG:
1819 brw_AVG(p, dst, src[0], src[1]);
1820 break;
1821 case BRW_OPCODE_MACH:
1822 brw_MACH(p, dst, src[0], src[1]);
1823 break;
1824
1825 case BRW_OPCODE_LINE:
1826 brw_LINE(p, dst, src[0], src[1]);
1827 break;
1828
1829 case BRW_OPCODE_MAD:
1830 assert(devinfo->gen >= 6);
1831 brw_set_default_access_mode(p, BRW_ALIGN_16);
1832 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1833 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1834 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1835 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1836 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1837 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1838 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1839
1840 if (inst->conditional_mod) {
1841 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1842 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1843 multiple_instructions_emitted = true;
1844 }
1845 } else {
1846 brw_MAD(p, dst, src[0], src[1], src[2]);
1847 }
1848 brw_set_default_access_mode(p, BRW_ALIGN_1);
1849 break;
1850
1851 case BRW_OPCODE_LRP:
1852 assert(devinfo->gen >= 6);
1853 brw_set_default_access_mode(p, BRW_ALIGN_16);
1854 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1855 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1856 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1857 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1858 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1859 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1860 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1861
1862 if (inst->conditional_mod) {
1863 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1864 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1865 multiple_instructions_emitted = true;
1866 }
1867 } else {
1868 brw_LRP(p, dst, src[0], src[1], src[2]);
1869 }
1870 brw_set_default_access_mode(p, BRW_ALIGN_1);
1871 break;
1872
1873 case BRW_OPCODE_FRC:
1874 brw_FRC(p, dst, src[0]);
1875 break;
1876 case BRW_OPCODE_RNDD:
1877 brw_RNDD(p, dst, src[0]);
1878 break;
1879 case BRW_OPCODE_RNDE:
1880 brw_RNDE(p, dst, src[0]);
1881 break;
1882 case BRW_OPCODE_RNDZ:
1883 brw_RNDZ(p, dst, src[0]);
1884 break;
1885
1886 case BRW_OPCODE_AND:
1887 brw_AND(p, dst, src[0], src[1]);
1888 break;
1889 case BRW_OPCODE_OR:
1890 brw_OR(p, dst, src[0], src[1]);
1891 break;
1892 case BRW_OPCODE_XOR:
1893 brw_XOR(p, dst, src[0], src[1]);
1894 break;
1895 case BRW_OPCODE_NOT:
1896 brw_NOT(p, dst, src[0]);
1897 break;
1898 case BRW_OPCODE_ASR:
1899 brw_ASR(p, dst, src[0], src[1]);
1900 break;
1901 case BRW_OPCODE_SHR:
1902 brw_SHR(p, dst, src[0], src[1]);
1903 break;
1904 case BRW_OPCODE_SHL:
1905 brw_SHL(p, dst, src[0], src[1]);
1906 break;
1907 case BRW_OPCODE_F32TO16:
1908 assert(devinfo->gen >= 7);
1909 brw_F32TO16(p, dst, src[0]);
1910 break;
1911 case BRW_OPCODE_F16TO32:
1912 assert(devinfo->gen >= 7);
1913 brw_F16TO32(p, dst, src[0]);
1914 break;
1915 case BRW_OPCODE_CMP:
1916 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1917 * that when the destination is a GRF that the dependency-clear bit on
1918 * the flag register is cleared early.
1919 *
1920 * Suggested workarounds are to disable coissuing CMP instructions
1921 * or to split CMP(16) instructions into two CMP(8) instructions.
1922 *
1923 * We choose to split into CMP(8) instructions since disabling
1924 * coissuing would affect CMP instructions not otherwise affected by
1925 * the errata.
1926 */
1927 if (dispatch_width == 16 && devinfo->gen == 7 && !devinfo->is_haswell) {
1928 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1929 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1930 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1931 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1932 firsthalf(src[0]), firsthalf(src[1]));
1933 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1934 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1935 sechalf(src[0]), sechalf(src[1]));
1936 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1937
1938 multiple_instructions_emitted = true;
1939 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1940 /* For unknown reasons, the aforementioned workaround is not
1941 * sufficient. Overriding the type when the destination is the
1942 * null register is necessary but not sufficient by itself.
1943 */
1944 assert(dst.nr == BRW_ARF_NULL);
1945 dst.type = BRW_REGISTER_TYPE_D;
1946 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1947 } else {
1948 unreachable("not reached");
1949 }
1950 } else {
1951 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1952 }
1953 break;
1954 case BRW_OPCODE_SEL:
1955 brw_SEL(p, dst, src[0], src[1]);
1956 break;
1957 case BRW_OPCODE_BFREV:
1958 assert(devinfo->gen >= 7);
1959 /* BFREV only supports UD type for src and dst. */
1960 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1961 retype(src[0], BRW_REGISTER_TYPE_UD));
1962 break;
1963 case BRW_OPCODE_FBH:
1964 assert(devinfo->gen >= 7);
1965 /* FBH only supports UD type for dst. */
1966 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1967 break;
1968 case BRW_OPCODE_FBL:
1969 assert(devinfo->gen >= 7);
1970 /* FBL only supports UD type for dst. */
1971 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1972 break;
1973 case BRW_OPCODE_CBIT:
1974 assert(devinfo->gen >= 7);
1975 /* CBIT only supports UD type for dst. */
1976 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1977 break;
1978 case BRW_OPCODE_ADDC:
1979 assert(devinfo->gen >= 7);
1980 brw_ADDC(p, dst, src[0], src[1]);
1981 break;
1982 case BRW_OPCODE_SUBB:
1983 assert(devinfo->gen >= 7);
1984 brw_SUBB(p, dst, src[0], src[1]);
1985 break;
1986 case BRW_OPCODE_MAC:
1987 brw_MAC(p, dst, src[0], src[1]);
1988 break;
1989
1990 case BRW_OPCODE_BFE:
1991 assert(devinfo->gen >= 7);
1992 brw_set_default_access_mode(p, BRW_ALIGN_16);
1993 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1994 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1995 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1996 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1997 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1998 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1999 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
2000 } else {
2001 brw_BFE(p, dst, src[0], src[1], src[2]);
2002 }
2003 brw_set_default_access_mode(p, BRW_ALIGN_1);
2004 break;
2005
2006 case BRW_OPCODE_BFI1:
2007 assert(devinfo->gen >= 7);
2008 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
2009 * should
2010 *
2011 * "Force BFI instructions to be executed always in SIMD8."
2012 */
2013 if (dispatch_width == 16 && devinfo->is_haswell) {
2014 brw_set_default_exec_size(p, BRW_EXECUTE_8);
2015 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
2016 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
2017 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
2018 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
2019 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
2020 } else {
2021 brw_BFI1(p, dst, src[0], src[1]);
2022 }
2023 break;
2024 case BRW_OPCODE_BFI2:
2025 assert(devinfo->gen >= 7);
2026 brw_set_default_access_mode(p, BRW_ALIGN_16);
2027 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
2028 * should
2029 *
2030 * "Force BFI instructions to be executed always in SIMD8."
2031 *
2032 * Otherwise we would be able to emit compressed instructions like we
2033 * do for the other three-source instructions.
2034 */
2035 if (dispatch_width == 16 &&
2036 (devinfo->is_haswell || !devinfo->supports_simd16_3src)) {
2037 brw_set_default_exec_size(p, BRW_EXECUTE_8);
2038 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
2039 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
2040 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
2041 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
2042 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
2043 } else {
2044 brw_BFI2(p, dst, src[0], src[1], src[2]);
2045 }
2046 brw_set_default_access_mode(p, BRW_ALIGN_1);
2047 break;
2048
2049 case BRW_OPCODE_IF:
2050 if (inst->src[0].file != BAD_FILE) {
2051 /* The instruction has an embedded compare (only allowed on gen6) */
2052 assert(devinfo->gen == 6);
2053 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
2054 } else {
2055 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
2056 }
2057 break;
2058
2059 case BRW_OPCODE_ELSE:
2060 brw_ELSE(p);
2061 break;
2062 case BRW_OPCODE_ENDIF:
2063 brw_ENDIF(p);
2064 break;
2065
2066 case BRW_OPCODE_DO:
2067 brw_DO(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
2068 break;
2069
2070 case BRW_OPCODE_BREAK:
2071 brw_BREAK(p);
2072 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2073 break;
2074 case BRW_OPCODE_CONTINUE:
2075 brw_CONT(p);
2076 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2077 break;
2078
2079 case BRW_OPCODE_WHILE:
2080 brw_WHILE(p);
2081 loop_count++;
2082 break;
2083
2084 case SHADER_OPCODE_RCP:
2085 case SHADER_OPCODE_RSQ:
2086 case SHADER_OPCODE_SQRT:
2087 case SHADER_OPCODE_EXP2:
2088 case SHADER_OPCODE_LOG2:
2089 case SHADER_OPCODE_SIN:
2090 case SHADER_OPCODE_COS:
2091 assert(devinfo->gen < 6 || inst->mlen == 0);
2092 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2093 if (devinfo->gen >= 7) {
2094 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
2095 brw_null_reg());
2096 } else if (devinfo->gen == 6) {
2097 generate_math_gen6(inst, dst, src[0], brw_null_reg());
2098 } else if (devinfo->gen == 5 || devinfo->is_g4x) {
2099 generate_math_g45(inst, dst, src[0]);
2100 } else {
2101 generate_math_gen4(inst, dst, src[0]);
2102 }
2103 break;
2104 case SHADER_OPCODE_INT_QUOTIENT:
2105 case SHADER_OPCODE_INT_REMAINDER:
2106 case SHADER_OPCODE_POW:
2107 assert(devinfo->gen < 6 || inst->mlen == 0);
2108 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2109 if (devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
2110 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
2111 } else if (devinfo->gen >= 6) {
2112 generate_math_gen6(inst, dst, src[0], src[1]);
2113 } else {
2114 generate_math_gen4(inst, dst, src[0]);
2115 }
2116 break;
2117 case FS_OPCODE_CINTERP:
2118 brw_MOV(p, dst, src[0]);
2119 break;
2120 case FS_OPCODE_LINTERP:
2121 generate_linterp(inst, dst, src);
2122 break;
2123 case FS_OPCODE_PIXEL_X:
2124 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2125 src[0].subnr = 0 * type_sz(src[0].type);
2126 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2127 break;
2128 case FS_OPCODE_PIXEL_Y:
2129 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2130 src[0].subnr = 4 * type_sz(src[0].type);
2131 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2132 break;
2133 case FS_OPCODE_GET_BUFFER_SIZE:
2134 generate_get_buffer_size(inst, dst, src[0], src[1]);
2135 break;
2136 case SHADER_OPCODE_TEX:
2137 case FS_OPCODE_TXB:
2138 case SHADER_OPCODE_TXD:
2139 case SHADER_OPCODE_TXF:
2140 case SHADER_OPCODE_TXF_CMS:
2141 case SHADER_OPCODE_TXF_CMS_W:
2142 case SHADER_OPCODE_TXF_UMS:
2143 case SHADER_OPCODE_TXF_MCS:
2144 case SHADER_OPCODE_TXL:
2145 case SHADER_OPCODE_TXS:
2146 case SHADER_OPCODE_LOD:
2147 case SHADER_OPCODE_TG4:
2148 case SHADER_OPCODE_TG4_OFFSET:
2149 case SHADER_OPCODE_SAMPLEINFO:
2150 generate_tex(inst, dst, src[0], src[1], src[2]);
2151 break;
2152 case FS_OPCODE_DDX_COARSE:
2153 case FS_OPCODE_DDX_FINE:
2154 generate_ddx(inst->opcode, dst, src[0]);
2155 break;
2156 case FS_OPCODE_DDY_COARSE:
2157 case FS_OPCODE_DDY_FINE:
2158 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2159 generate_ddy(inst->opcode, dst, src[0], src[1].ud);
2160 break;
2161
2162 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
2163 generate_scratch_write(inst, src[0]);
2164 spill_count++;
2165 break;
2166
2167 case SHADER_OPCODE_GEN4_SCRATCH_READ:
2168 generate_scratch_read(inst, dst);
2169 fill_count++;
2170 break;
2171
2172 case SHADER_OPCODE_GEN7_SCRATCH_READ:
2173 generate_scratch_read_gen7(inst, dst);
2174 fill_count++;
2175 break;
2176
2177 case SHADER_OPCODE_MOV_INDIRECT:
2178 generate_mov_indirect(inst, dst, src[0], src[1]);
2179 break;
2180
2181 case SHADER_OPCODE_URB_READ_SIMD8:
2182 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
2183 generate_urb_read(inst, dst, src[0]);
2184 break;
2185
2186 case SHADER_OPCODE_URB_WRITE_SIMD8:
2187 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
2188 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
2189 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
2190 generate_urb_write(inst, src[0]);
2191 break;
2192
2193 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2194 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
2195 break;
2196
2197 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2198 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2199 break;
2200
2201 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
2202 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
2203 break;
2204
2205 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
2206 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2207 break;
2208
2209 case FS_OPCODE_REP_FB_WRITE:
2210 case FS_OPCODE_FB_WRITE:
2211 generate_fb_write(inst, src[0]);
2212 break;
2213
2214 case FS_OPCODE_BLORP_FB_WRITE:
2215 generate_blorp_fb_write(inst, src[0]);
2216 break;
2217
2218 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2219 generate_mov_dispatch_to_flags(inst);
2220 break;
2221
2222 case FS_OPCODE_DISCARD_JUMP:
2223 generate_discard_jump(inst);
2224 break;
2225
2226 case SHADER_OPCODE_SHADER_TIME_ADD:
2227 generate_shader_time_add(inst, src[0], src[1], src[2]);
2228 break;
2229
2230 case SHADER_OPCODE_UNTYPED_ATOMIC:
2231 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2232 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud,
2233 inst->mlen, !inst->dst.is_null());
2234 break;
2235
2236 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2237 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2238 brw_untyped_surface_read(p, dst, src[0], src[1],
2239 inst->mlen, src[2].ud);
2240 break;
2241
2242 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
2243 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2244 brw_untyped_surface_write(p, src[0], src[1],
2245 inst->mlen, src[2].ud);
2246 break;
2247
2248 case SHADER_OPCODE_TYPED_ATOMIC:
2249 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2250 brw_typed_atomic(p, dst, src[0], src[1],
2251 src[2].ud, inst->mlen, !inst->dst.is_null());
2252 break;
2253
2254 case SHADER_OPCODE_TYPED_SURFACE_READ:
2255 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2256 brw_typed_surface_read(p, dst, src[0], src[1],
2257 inst->mlen, src[2].ud);
2258 break;
2259
2260 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
2261 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2262 brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].ud);
2263 break;
2264
2265 case SHADER_OPCODE_MEMORY_FENCE:
2266 brw_memory_fence(p, dst);
2267 break;
2268
2269 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2270 generate_set_simd4x2_offset(inst, dst, src[0]);
2271 break;
2272
2273 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
2274 brw_find_live_channel(p, dst);
2275 break;
2276
2277 case SHADER_OPCODE_BROADCAST:
2278 brw_broadcast(p, dst, src[0], src[1]);
2279 break;
2280
2281 case SHADER_OPCODE_EXTRACT_BYTE: {
2282 assert(src[0].type == BRW_REGISTER_TYPE_D ||
2283 src[0].type == BRW_REGISTER_TYPE_UD);
2284
2285 enum brw_reg_type type =
2286 src[0].type == BRW_REGISTER_TYPE_D ? BRW_REGISTER_TYPE_B
2287 : BRW_REGISTER_TYPE_UB;
2288 brw_MOV(p, dst, spread(suboffset(retype(src[0], type), src[1].ud), 4));
2289 break;
2290 }
2291
2292 case SHADER_OPCODE_EXTRACT_WORD: {
2293 assert(src[0].type == BRW_REGISTER_TYPE_D ||
2294 src[0].type == BRW_REGISTER_TYPE_UD);
2295
2296 enum brw_reg_type type =
2297 src[0].type == BRW_REGISTER_TYPE_D ? BRW_REGISTER_TYPE_W
2298 : BRW_REGISTER_TYPE_UW;
2299 brw_MOV(p, dst, spread(suboffset(retype(src[0], type), src[1].ud), 2));
2300 break;
2301 }
2302
2303 case FS_OPCODE_SET_SAMPLE_ID:
2304 generate_set_sample_id(inst, dst, src[0], src[1]);
2305 break;
2306
2307 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2308 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2309 break;
2310
2311 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2312 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2313 generate_unpack_half_2x16_split(inst, dst, src[0]);
2314 break;
2315
2316 case FS_OPCODE_PLACEHOLDER_HALT:
2317 /* This is the place where the final HALT needs to be inserted if
2318 * we've emitted any discards. If not, this will emit no code.
2319 */
2320 if (!patch_discard_jumps_to_fb_writes()) {
2321 if (unlikely(debug_flag)) {
2322 annotation.ann_count--;
2323 }
2324 }
2325 break;
2326
2327 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2328 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2329 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2330 break;
2331
2332 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2333 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2334 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2335 break;
2336
2337 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2338 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2339 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2340 break;
2341
2342 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2343 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2344 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2345 break;
2346
2347 case CS_OPCODE_CS_TERMINATE:
2348 generate_cs_terminate(inst, src[0]);
2349 break;
2350
2351 case SHADER_OPCODE_BARRIER:
2352 generate_barrier(inst, src[0]);
2353 break;
2354
2355 case FS_OPCODE_PACK_STENCIL_REF:
2356 generate_stencil_ref_packing(inst, dst, src[0]);
2357 break;
2358
2359 default:
2360 unreachable("Unsupported opcode");
2361
2362 case SHADER_OPCODE_LOAD_PAYLOAD:
2363 unreachable("Should be lowered by lower_load_payload()");
2364 }
2365
2366 if (multiple_instructions_emitted)
2367 continue;
2368
2369 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2370 assert(p->next_insn_offset == last_insn_offset + 16 ||
2371 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2372 "emitting more than 1 instruction");
2373
2374 brw_inst *last = &p->store[last_insn_offset / 16];
2375
2376 if (inst->conditional_mod)
2377 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2378 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2379 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2380 }
2381 }
2382
2383 brw_set_uip_jip(p);
2384 annotation_finalize(&annotation, p->next_insn_offset);
2385
2386 #ifndef NDEBUG
2387 bool validated = brw_validate_instructions(p, start_offset, &annotation);
2388 #else
2389 if (unlikely(debug_flag))
2390 brw_validate_instructions(p, start_offset, &annotation);
2391 #endif
2392
2393 int before_size = p->next_insn_offset - start_offset;
2394 brw_compact_instructions(p, start_offset, annotation.ann_count,
2395 annotation.ann);
2396 int after_size = p->next_insn_offset - start_offset;
2397
2398 if (unlikely(debug_flag)) {
2399 fprintf(stderr, "Native code for %s\n"
2400 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2401 " bytes (%.0f%%)\n",
2402 shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
2403 spill_count, fill_count, promoted_constants, before_size, after_size,
2404 100.0f * (before_size - after_size) / before_size);
2405
2406 dump_assembly(p->store, annotation.ann_count, annotation.ann,
2407 p->devinfo);
2408 ralloc_free(annotation.mem_ctx);
2409 }
2410 assert(validated);
2411
2412 compiler->shader_debug_log(log_data,
2413 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2414 "%d:%d spills:fills, Promoted %u constants, "
2415 "compacted %d to %d bytes.",
2416 _mesa_shader_stage_to_abbrev(stage),
2417 dispatch_width, before_size / 16,
2418 loop_count, cfg->cycle_count, spill_count,
2419 fill_count, promoted_constants, before_size,
2420 after_size);
2421
2422 return start_offset;
2423 }
2424
2425 const unsigned *
2426 fs_generator::get_assembly(unsigned int *assembly_size)
2427 {
2428 return brw_get_program(p, assembly_size);
2429 }