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i965/fs: Use the UW type for the destination of VARYING_PULL_CONSTANT_LOAD instructions
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 fs_generator::fs_generator(struct brw_context *brw,
40 void *mem_ctx,
41 const struct brw_wm_prog_key *key,
42 struct brw_wm_prog_data *prog_data,
43 struct gl_shader_program *shader_prog,
44 struct gl_fragment_program *fp,
45 bool runtime_check_aads_emit,
46 bool debug_flag)
47
48 : brw(brw), stage(MESA_SHADER_FRAGMENT), key(key),
49 prog_data(&prog_data->base), shader_prog(shader_prog),
50 prog(&fp->Base), runtime_check_aads_emit(runtime_check_aads_emit),
51 debug_flag(debug_flag), mem_ctx(mem_ctx)
52 {
53 ctx = &brw->ctx;
54
55 p = rzalloc(mem_ctx, struct brw_compile);
56 brw_init_compile(brw, p, mem_ctx);
57 }
58
59 fs_generator::~fs_generator()
60 {
61 }
62
63 bool
64 fs_generator::patch_discard_jumps_to_fb_writes()
65 {
66 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
67 return false;
68
69 int scale = brw_jump_scale(brw);
70
71 /* There is a somewhat strange undocumented requirement of using
72 * HALT, according to the simulator. If some channel has HALTed to
73 * a particular UIP, then by the end of the program, every channel
74 * must have HALTed to that UIP. Furthermore, the tracking is a
75 * stack, so you can't do the final halt of a UIP after starting
76 * halting to a new UIP.
77 *
78 * Symptoms of not emitting this instruction on actual hardware
79 * included GPU hangs and sparkly rendering on the piglit discard
80 * tests.
81 */
82 brw_inst *last_halt = gen6_HALT(p);
83 brw_inst_set_uip(brw, last_halt, 1 * scale);
84 brw_inst_set_jip(brw, last_halt, 1 * scale);
85
86 int ip = p->nr_insn;
87
88 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
89 brw_inst *patch = &p->store[patch_ip->ip];
90
91 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
92 /* HALT takes a half-instruction distance from the pre-incremented IP. */
93 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
94 }
95
96 this->discard_halt_patches.make_empty();
97 return true;
98 }
99
100 void
101 fs_generator::fire_fb_write(fs_inst *inst,
102 GLuint base_reg,
103 struct brw_reg implied_header,
104 GLuint nr)
105 {
106 uint32_t msg_control;
107
108 assert(stage == MESA_SHADER_FRAGMENT);
109 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
110
111 if (brw->gen < 6) {
112 brw_push_insn_state(p);
113 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
114 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
115 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
116 brw_MOV(p,
117 brw_message_reg(base_reg + 1),
118 brw_vec8_grf(1, 0));
119 brw_pop_insn_state(p);
120 }
121
122 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
123 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
124 else if (prog_data->dual_src_blend)
125 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
126 else if (dispatch_width == 16)
127 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
128 else
129 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
130
131 uint32_t surf_index =
132 prog_data->binding_table.render_target_start + inst->target;
133
134 brw_fb_WRITE(p,
135 dispatch_width,
136 base_reg,
137 implied_header,
138 msg_control,
139 surf_index,
140 nr,
141 0,
142 inst->eot,
143 inst->header_present);
144
145 brw_mark_surface_used(&prog_data->base, surf_index);
146 }
147
148 void
149 fs_generator::generate_fb_write(fs_inst *inst)
150 {
151 assert(stage == MESA_SHADER_FRAGMENT);
152 gl_fragment_program *fp = (gl_fragment_program *) prog;
153 struct brw_reg implied_header;
154
155 assert(stage == MESA_SHADER_FRAGMENT);
156 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
157 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
158
159 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
160 * move, here's g1.
161 */
162 if (inst->header_present) {
163 brw_push_insn_state(p);
164 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
165 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
166 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
167 brw_set_default_flag_reg(p, 0, 0);
168
169 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
170 * present.
171 */
172 if (prog_data->uses_kill || key->alpha_test_func) {
173 struct brw_reg pixel_mask;
174
175 if (brw->gen >= 6)
176 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
177 else
178 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
179
180 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
181 }
182
183 if (brw->gen >= 6) {
184 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
185 brw_MOV(p,
186 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
187 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
188 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
189
190 if (inst->target > 0 && key->replicate_alpha) {
191 /* Set "Source0 Alpha Present to RenderTarget" bit in message
192 * header.
193 */
194 brw_OR(p,
195 vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)),
196 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
197 brw_imm_ud(0x1 << 11));
198 }
199
200 if (inst->target > 0) {
201 /* Set the render target index for choosing BLEND_STATE. */
202 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
203 inst->base_mrf, 2),
204 BRW_REGISTER_TYPE_UD),
205 brw_imm_ud(inst->target));
206 }
207
208 implied_header = brw_null_reg();
209 } else {
210 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
211 }
212
213 brw_pop_insn_state(p);
214 } else {
215 implied_header = brw_null_reg();
216 }
217
218 if (!runtime_check_aads_emit) {
219 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
220 } else {
221 /* This can only happen in gen < 6 */
222 assert(brw->gen < 6);
223
224 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
225
226 /* Check runtime bit to detect if we have to send AA data or not */
227 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
228 brw_AND(p,
229 v1_null_ud,
230 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
231 brw_imm_ud(1<<26));
232 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
233
234 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
235 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
236 {
237 /* Don't send AA data */
238 fire_fb_write(inst, inst->base_mrf+1, implied_header, inst->mlen-1);
239 }
240 brw_land_fwd_jump(p, jmp);
241 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
242 }
243 }
244
245 void
246 fs_generator::generate_blorp_fb_write(fs_inst *inst)
247 {
248 brw_fb_WRITE(p,
249 16 /* dispatch_width */,
250 inst->base_mrf,
251 brw_reg_from_fs_reg(&inst->src[0]),
252 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
253 inst->target,
254 inst->mlen,
255 0,
256 true,
257 inst->header_present);
258 }
259
260 /* Computes the integer pixel x,y values from the origin.
261 *
262 * This is the basis of gl_FragCoord computation, but is also used
263 * pre-gen6 for computing the deltas from v0 for computing
264 * interpolation.
265 */
266 void
267 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
268 {
269 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
270 struct brw_reg src;
271 struct brw_reg deltas;
272
273 if (is_x) {
274 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
275 deltas = brw_imm_v(0x10101010);
276 } else {
277 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
278 deltas = brw_imm_v(0x11001100);
279 }
280
281 if (dispatch_width == 16) {
282 dst = vec16(dst);
283 }
284
285 /* We do this SIMD8 or SIMD16, but since the destination is UW we
286 * don't do compression in the SIMD16 case.
287 */
288 brw_push_insn_state(p);
289 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
290 brw_ADD(p, dst, src, deltas);
291 brw_pop_insn_state(p);
292 }
293
294 void
295 fs_generator::generate_linterp(fs_inst *inst,
296 struct brw_reg dst, struct brw_reg *src)
297 {
298 struct brw_reg delta_x = src[0];
299 struct brw_reg delta_y = src[1];
300 struct brw_reg interp = src[2];
301
302 if (brw->has_pln &&
303 delta_y.nr == delta_x.nr + 1 &&
304 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
305 brw_PLN(p, dst, interp, delta_x);
306 } else {
307 brw_LINE(p, brw_null_reg(), interp, delta_x);
308 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
309 }
310 }
311
312 void
313 fs_generator::generate_math_gen6(fs_inst *inst,
314 struct brw_reg dst,
315 struct brw_reg src0,
316 struct brw_reg src1)
317 {
318 int op = brw_math_function(inst->opcode);
319 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
320
321 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
322 gen6_math(p, dst, op, src0, src1);
323
324 if (dispatch_width == 16) {
325 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
326 gen6_math(p, sechalf(dst), op, sechalf(src0),
327 binop ? sechalf(src1) : brw_null_reg());
328 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
329 }
330 }
331
332 void
333 fs_generator::generate_math_gen4(fs_inst *inst,
334 struct brw_reg dst,
335 struct brw_reg src)
336 {
337 int op = brw_math_function(inst->opcode);
338
339 assert(inst->mlen >= 1);
340
341 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
342 gen4_math(p, dst,
343 op,
344 inst->base_mrf, src,
345 BRW_MATH_PRECISION_FULL);
346
347 if (dispatch_width == 16) {
348 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
349 gen4_math(p, sechalf(dst),
350 op,
351 inst->base_mrf + 1, sechalf(src),
352 BRW_MATH_PRECISION_FULL);
353
354 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
355 }
356 }
357
358 void
359 fs_generator::generate_math_g45(fs_inst *inst,
360 struct brw_reg dst,
361 struct brw_reg src)
362 {
363 if (inst->opcode == SHADER_OPCODE_POW ||
364 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
365 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
366 generate_math_gen4(inst, dst, src);
367 return;
368 }
369
370 int op = brw_math_function(inst->opcode);
371
372 assert(inst->mlen >= 1);
373
374 gen4_math(p, dst,
375 op,
376 inst->base_mrf, src,
377 BRW_MATH_PRECISION_FULL);
378 }
379
380 void
381 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
382 struct brw_reg sampler_index)
383 {
384 int msg_type = -1;
385 int rlen = 4;
386 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
387 uint32_t return_format;
388
389 switch (dst.type) {
390 case BRW_REGISTER_TYPE_D:
391 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
392 break;
393 case BRW_REGISTER_TYPE_UD:
394 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
395 break;
396 default:
397 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
398 break;
399 }
400
401 if (dispatch_width == 16 &&
402 !inst->force_uncompressed && !inst->force_sechalf)
403 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
404
405 if (brw->gen >= 5) {
406 switch (inst->opcode) {
407 case SHADER_OPCODE_TEX:
408 if (inst->shadow_compare) {
409 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
410 } else {
411 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
412 }
413 break;
414 case FS_OPCODE_TXB:
415 if (inst->shadow_compare) {
416 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
417 } else {
418 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
419 }
420 break;
421 case SHADER_OPCODE_TXL:
422 if (inst->shadow_compare) {
423 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
424 } else {
425 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
426 }
427 break;
428 case SHADER_OPCODE_TXS:
429 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
430 break;
431 case SHADER_OPCODE_TXD:
432 if (inst->shadow_compare) {
433 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
434 assert(brw->gen >= 8 || brw->is_haswell);
435 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
436 } else {
437 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
438 }
439 break;
440 case SHADER_OPCODE_TXF:
441 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
442 break;
443 case SHADER_OPCODE_TXF_CMS:
444 if (brw->gen >= 7)
445 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
446 else
447 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
448 break;
449 case SHADER_OPCODE_TXF_UMS:
450 assert(brw->gen >= 7);
451 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
452 break;
453 case SHADER_OPCODE_TXF_MCS:
454 assert(brw->gen >= 7);
455 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
456 break;
457 case SHADER_OPCODE_LOD:
458 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
459 break;
460 case SHADER_OPCODE_TG4:
461 if (inst->shadow_compare) {
462 assert(brw->gen >= 7);
463 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
464 } else {
465 assert(brw->gen >= 6);
466 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
467 }
468 break;
469 case SHADER_OPCODE_TG4_OFFSET:
470 assert(brw->gen >= 7);
471 if (inst->shadow_compare) {
472 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
473 } else {
474 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
475 }
476 break;
477 default:
478 unreachable("not reached");
479 }
480 } else {
481 switch (inst->opcode) {
482 case SHADER_OPCODE_TEX:
483 /* Note that G45 and older determines shadow compare and dispatch width
484 * from message length for most messages.
485 */
486 assert(dispatch_width == 8);
487 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
488 if (inst->shadow_compare) {
489 assert(inst->mlen == 6);
490 } else {
491 assert(inst->mlen <= 4);
492 }
493 break;
494 case FS_OPCODE_TXB:
495 if (inst->shadow_compare) {
496 assert(inst->mlen == 6);
497 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
498 } else {
499 assert(inst->mlen == 9);
500 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
501 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
502 }
503 break;
504 case SHADER_OPCODE_TXL:
505 if (inst->shadow_compare) {
506 assert(inst->mlen == 6);
507 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
508 } else {
509 assert(inst->mlen == 9);
510 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
511 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
512 }
513 break;
514 case SHADER_OPCODE_TXD:
515 /* There is no sample_d_c message; comparisons are done manually */
516 assert(inst->mlen == 7 || inst->mlen == 10);
517 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
518 break;
519 case SHADER_OPCODE_TXF:
520 assert(inst->mlen == 9);
521 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
522 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
523 break;
524 case SHADER_OPCODE_TXS:
525 assert(inst->mlen == 3);
526 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
527 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
528 break;
529 default:
530 unreachable("not reached");
531 }
532 }
533 assert(msg_type != -1);
534
535 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
536 rlen = 8;
537 dst = vec16(dst);
538 }
539
540 if (brw->gen >= 7 && inst->header_present && dispatch_width == 16) {
541 /* The send-from-GRF for SIMD16 texturing with a header has an extra
542 * hardware register allocated to it, which we need to skip over (since
543 * our coordinates in the payload are in the even-numbered registers,
544 * and the header comes right before the first one).
545 */
546 assert(src.file == BRW_GENERAL_REGISTER_FILE);
547 src.nr++;
548 }
549
550 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
551
552 /* Load the message header if present. If there's a texture offset,
553 * we need to set it up explicitly and load the offset bitfield.
554 * Otherwise, we can use an implied move from g0 to the first message reg.
555 */
556 if (inst->header_present) {
557 if (brw->gen < 6 && !inst->texture_offset) {
558 /* Set up an implied move from g0 to the MRF. */
559 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
560 } else {
561 struct brw_reg header_reg;
562
563 if (brw->gen >= 7) {
564 header_reg = src;
565 } else {
566 assert(inst->base_mrf != -1);
567 header_reg = brw_message_reg(inst->base_mrf);
568 }
569
570 brw_push_insn_state(p);
571 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
572 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
573 /* Explicitly set up the message header by copying g0 to the MRF. */
574 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
575
576 if (inst->texture_offset) {
577 /* Set the offset bits in DWord 2. */
578 brw_MOV(p, get_element_ud(header_reg, 2),
579 brw_imm_ud(inst->texture_offset));
580 }
581
582 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index, dst);
583 brw_pop_insn_state(p);
584 }
585 }
586
587 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
588 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
589 ? prog_data->binding_table.gather_texture_start
590 : prog_data->binding_table.texture_start;
591
592 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
593 uint32_t sampler = sampler_index.dw1.ud;
594
595 brw_SAMPLE(p,
596 retype(dst, BRW_REGISTER_TYPE_UW),
597 inst->base_mrf,
598 src,
599 sampler + base_binding_table_index,
600 sampler % 16,
601 msg_type,
602 rlen,
603 inst->mlen,
604 inst->header_present,
605 simd_mode,
606 return_format);
607
608 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
609 } else {
610 /* Non-const sampler index */
611 /* Note: this clobbers `dst` as a temporary before emitting the send */
612
613 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
614 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
615
616 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
617
618 brw_push_insn_state(p);
619 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
620 brw_set_default_access_mode(p, BRW_ALIGN_1);
621
622 /* Some care required: `sampler` and `temp` may alias:
623 * addr = sampler & 0xff
624 * temp = (sampler << 8) & 0xf00
625 * addr = addr | temp
626 */
627 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
628 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
629 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
630 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
631 brw_OR(p, addr, addr, temp);
632
633 /* a0.0 |= <descriptor> */
634 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
635 brw_set_sampler_message(p, insn_or,
636 0 /* surface */,
637 0 /* sampler */,
638 msg_type,
639 rlen,
640 inst->mlen /* mlen */,
641 inst->header_present /* header */,
642 simd_mode,
643 return_format);
644 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
645 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
646 brw_set_src0(p, insn_or, addr);
647 brw_set_dest(p, insn_or, addr);
648
649
650 /* dst = send(offset, a0.0) */
651 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
652 brw_set_dest(p, insn_send, dst);
653 brw_set_src0(p, insn_send, src);
654 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
655
656 brw_pop_insn_state(p);
657
658 /* visitor knows more than we do about the surface limit required,
659 * so has already done marking.
660 */
661 }
662 }
663
664
665 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
666 * looking like:
667 *
668 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
669 *
670 * Ideally, we want to produce:
671 *
672 * DDX DDY
673 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
674 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
675 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
676 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
677 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
678 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
679 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
680 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
681 *
682 * and add another set of two more subspans if in 16-pixel dispatch mode.
683 *
684 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
685 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
686 * pair. But the ideal approximation may impose a huge performance cost on
687 * sample_d. On at least Haswell, sample_d instruction does some
688 * optimizations if the same LOD is used for all pixels in the subspan.
689 *
690 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
691 * appropriate swizzling.
692 */
693 void
694 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
695 struct brw_reg quality)
696 {
697 unsigned vstride, width;
698 assert(quality.file == BRW_IMMEDIATE_VALUE);
699 assert(quality.type == BRW_REGISTER_TYPE_D);
700
701 assert(stage == MESA_SHADER_FRAGMENT);
702 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
703
704 int quality_value = quality.dw1.d;
705
706 if (quality_value == BRW_DERIVATIVE_FINE ||
707 (key->high_quality_derivatives && quality_value != BRW_DERIVATIVE_COARSE)) {
708 /* produce accurate derivatives */
709 vstride = BRW_VERTICAL_STRIDE_2;
710 width = BRW_WIDTH_2;
711 }
712 else {
713 /* replicate the derivative at the top-left pixel to other pixels */
714 vstride = BRW_VERTICAL_STRIDE_4;
715 width = BRW_WIDTH_4;
716 }
717
718 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
719 BRW_REGISTER_TYPE_F,
720 vstride,
721 width,
722 BRW_HORIZONTAL_STRIDE_0,
723 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
724 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
725 BRW_REGISTER_TYPE_F,
726 vstride,
727 width,
728 BRW_HORIZONTAL_STRIDE_0,
729 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
730 brw_ADD(p, dst, src0, negate(src1));
731 }
732
733 /* The negate_value boolean is used to negate the derivative computation for
734 * FBOs, since they place the origin at the upper left instead of the lower
735 * left.
736 */
737 void
738 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
739 struct brw_reg quality, bool negate_value)
740 {
741 assert(quality.file == BRW_IMMEDIATE_VALUE);
742 assert(quality.type == BRW_REGISTER_TYPE_D);
743
744 assert(stage == MESA_SHADER_FRAGMENT);
745 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
746
747 int quality_value = quality.dw1.d;
748
749 if (quality_value == BRW_DERIVATIVE_FINE ||
750 (key->high_quality_derivatives && quality_value != BRW_DERIVATIVE_COARSE)) {
751 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
752 * Region Restrictions):
753 *
754 * In Align16 access mode, SIMD16 is not allowed for DW operations
755 * and SIMD8 is not allowed for DF operations.
756 *
757 * In this context, "DW operations" means "operations acting on 32-bit
758 * values", so it includes operations on floats.
759 *
760 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
761 * (Instruction Compression -> Rules and Restrictions):
762 *
763 * A compressed instruction must be in Align1 access mode. Align16
764 * mode instructions cannot be compressed.
765 *
766 * Similar text exists in the g45 PRM.
767 *
768 * On these platforms, if we're building a SIMD16 shader, we need to
769 * manually unroll to a pair of SIMD8 instructions.
770 */
771 bool unroll_to_simd8 =
772 (dispatch_width == 16 &&
773 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
774
775 /* produce accurate derivatives */
776 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
777 BRW_REGISTER_TYPE_F,
778 BRW_VERTICAL_STRIDE_4,
779 BRW_WIDTH_4,
780 BRW_HORIZONTAL_STRIDE_1,
781 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
782 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
783 BRW_REGISTER_TYPE_F,
784 BRW_VERTICAL_STRIDE_4,
785 BRW_WIDTH_4,
786 BRW_HORIZONTAL_STRIDE_1,
787 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
788 brw_push_insn_state(p);
789 brw_set_default_access_mode(p, BRW_ALIGN_16);
790 if (unroll_to_simd8)
791 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
792 if (negate_value)
793 brw_ADD(p, dst, src1, negate(src0));
794 else
795 brw_ADD(p, dst, src0, negate(src1));
796 if (unroll_to_simd8) {
797 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
798 src0 = sechalf(src0);
799 src1 = sechalf(src1);
800 dst = sechalf(dst);
801 if (negate_value)
802 brw_ADD(p, dst, src1, negate(src0));
803 else
804 brw_ADD(p, dst, src0, negate(src1));
805 }
806 brw_pop_insn_state(p);
807 } else {
808 /* replicate the derivative at the top-left pixel to other pixels */
809 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
810 BRW_REGISTER_TYPE_F,
811 BRW_VERTICAL_STRIDE_4,
812 BRW_WIDTH_4,
813 BRW_HORIZONTAL_STRIDE_0,
814 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
815 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
816 BRW_REGISTER_TYPE_F,
817 BRW_VERTICAL_STRIDE_4,
818 BRW_WIDTH_4,
819 BRW_HORIZONTAL_STRIDE_0,
820 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
821 if (negate_value)
822 brw_ADD(p, dst, src1, negate(src0));
823 else
824 brw_ADD(p, dst, src0, negate(src1));
825 }
826 }
827
828 void
829 fs_generator::generate_discard_jump(fs_inst *inst)
830 {
831 assert(brw->gen >= 6);
832
833 /* This HALT will be patched up at FB write time to point UIP at the end of
834 * the program, and at brw_uip_jip() JIP will be set to the end of the
835 * current block (or the program).
836 */
837 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
838
839 brw_push_insn_state(p);
840 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
841 gen6_HALT(p);
842 brw_pop_insn_state(p);
843 }
844
845 void
846 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
847 {
848 assert(inst->mlen != 0);
849
850 brw_MOV(p,
851 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
852 retype(src, BRW_REGISTER_TYPE_UD));
853 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
854 dispatch_width / 8, inst->offset);
855 }
856
857 void
858 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
859 {
860 assert(inst->mlen != 0);
861
862 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
863 dispatch_width / 8, inst->offset);
864 }
865
866 void
867 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
868 {
869 gen7_block_read_scratch(p, dst, dispatch_width / 8, inst->offset);
870 }
871
872 void
873 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
874 struct brw_reg dst,
875 struct brw_reg index,
876 struct brw_reg offset)
877 {
878 assert(inst->mlen != 0);
879
880 assert(index.file == BRW_IMMEDIATE_VALUE &&
881 index.type == BRW_REGISTER_TYPE_UD);
882 uint32_t surf_index = index.dw1.ud;
883
884 assert(offset.file == BRW_IMMEDIATE_VALUE &&
885 offset.type == BRW_REGISTER_TYPE_UD);
886 uint32_t read_offset = offset.dw1.ud;
887
888 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
889 read_offset, surf_index);
890
891 brw_mark_surface_used(prog_data, surf_index);
892 }
893
894 void
895 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
896 struct brw_reg dst,
897 struct brw_reg index,
898 struct brw_reg offset)
899 {
900 assert(inst->mlen == 0);
901 assert(index.type == BRW_REGISTER_TYPE_UD);
902
903 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
904 /* Reference just the dword we need, to avoid angering validate_reg(). */
905 offset = brw_vec1_grf(offset.nr, 0);
906
907 /* We use the SIMD4x2 mode because we want to end up with 4 components in
908 * the destination loaded consecutively from the same offset (which appears
909 * in the first component, and the rest are ignored).
910 */
911 dst.width = BRW_WIDTH_4;
912
913 if (index.file == BRW_IMMEDIATE_VALUE) {
914
915 uint32_t surf_index = index.dw1.ud;
916
917 brw_push_insn_state(p);
918 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
919 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
920 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
921 brw_pop_insn_state(p);
922
923 brw_set_dest(p, send, dst);
924 brw_set_src0(p, send, offset);
925 brw_set_sampler_message(p, send,
926 surf_index,
927 0, /* LD message ignores sampler unit */
928 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
929 1, /* rlen */
930 1, /* mlen */
931 false, /* no header */
932 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
933 0);
934
935 brw_mark_surface_used(prog_data, surf_index);
936
937 } else {
938
939 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
940
941 brw_push_insn_state(p);
942 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
943 brw_set_default_access_mode(p, BRW_ALIGN_1);
944
945 /* a0.0 = surf_index & 0xff */
946 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
947 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
948 brw_set_dest(p, insn_and, addr);
949 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
950 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
951
952
953 /* a0.0 |= <descriptor> */
954 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
955 brw_set_sampler_message(p, insn_or,
956 0 /* surface */,
957 0 /* sampler */,
958 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
959 1 /* rlen */,
960 1 /* mlen */,
961 false /* header */,
962 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
963 0);
964 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
965 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
966 brw_set_src0(p, insn_or, addr);
967 brw_set_dest(p, insn_or, addr);
968
969
970 /* dst = send(offset, a0.0) */
971 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
972 brw_set_dest(p, insn_send, dst);
973 brw_set_src0(p, insn_send, offset);
974 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
975
976 brw_pop_insn_state(p);
977
978 /* visitor knows more than we do about the surface limit required,
979 * so has already done marking.
980 */
981
982 }
983 }
984
985 void
986 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
987 struct brw_reg dst,
988 struct brw_reg index,
989 struct brw_reg offset)
990 {
991 assert(brw->gen < 7); /* Should use the gen7 variant. */
992 assert(inst->header_present);
993 assert(inst->mlen);
994
995 assert(index.file == BRW_IMMEDIATE_VALUE &&
996 index.type == BRW_REGISTER_TYPE_UD);
997 uint32_t surf_index = index.dw1.ud;
998
999 uint32_t simd_mode, rlen, msg_type;
1000 if (dispatch_width == 16) {
1001 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1002 rlen = 8;
1003 } else {
1004 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1005 rlen = 4;
1006 }
1007
1008 if (brw->gen >= 5)
1009 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1010 else {
1011 /* We always use the SIMD16 message so that we only have to load U, and
1012 * not V or R.
1013 */
1014 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1015 assert(inst->mlen == 3);
1016 assert(inst->regs_written == 8);
1017 rlen = 8;
1018 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1019 }
1020
1021 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1022 BRW_REGISTER_TYPE_D);
1023 brw_MOV(p, offset_mrf, offset);
1024
1025 struct brw_reg header = brw_vec8_grf(0, 0);
1026 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1027
1028 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1029 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
1030 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1031 brw_set_src0(p, send, header);
1032 if (brw->gen < 6)
1033 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
1034
1035 /* Our surface is set up as floats, regardless of what actual data is
1036 * stored in it.
1037 */
1038 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1039 brw_set_sampler_message(p, send,
1040 surf_index,
1041 0, /* sampler (unused) */
1042 msg_type,
1043 rlen,
1044 inst->mlen,
1045 inst->header_present,
1046 simd_mode,
1047 return_format);
1048
1049 brw_mark_surface_used(prog_data, surf_index);
1050 }
1051
1052 void
1053 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1054 struct brw_reg dst,
1055 struct brw_reg index,
1056 struct brw_reg offset)
1057 {
1058 assert(brw->gen >= 7);
1059 /* Varying-offset pull constant loads are treated as a normal expression on
1060 * gen7, so the fact that it's a send message is hidden at the IR level.
1061 */
1062 assert(!inst->header_present);
1063 assert(!inst->mlen);
1064 assert(index.type == BRW_REGISTER_TYPE_UD);
1065
1066 uint32_t simd_mode, rlen, mlen;
1067 if (dispatch_width == 16) {
1068 mlen = 2;
1069 rlen = 8;
1070 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1071 } else {
1072 mlen = 1;
1073 rlen = 4;
1074 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1075 }
1076
1077 if (index.file == BRW_IMMEDIATE_VALUE) {
1078
1079 uint32_t surf_index = index.dw1.ud;
1080
1081 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1082 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1083 brw_set_src0(p, send, offset);
1084 brw_set_sampler_message(p, send,
1085 surf_index,
1086 0, /* LD message ignores sampler unit */
1087 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1088 rlen,
1089 mlen,
1090 false, /* no header */
1091 simd_mode,
1092 0);
1093
1094 brw_mark_surface_used(prog_data, surf_index);
1095
1096 } else {
1097
1098 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1099
1100 brw_push_insn_state(p);
1101 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1102 brw_set_default_access_mode(p, BRW_ALIGN_1);
1103
1104 /* a0.0 = surf_index & 0xff */
1105 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1106 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1107 brw_set_dest(p, insn_and, addr);
1108 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1109 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1110
1111
1112 /* a0.0 |= <descriptor> */
1113 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1114 brw_set_sampler_message(p, insn_or,
1115 0 /* surface */,
1116 0 /* sampler */,
1117 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1118 rlen /* rlen */,
1119 mlen /* mlen */,
1120 false /* header */,
1121 simd_mode,
1122 0);
1123 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1124 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1125 brw_set_src0(p, insn_or, addr);
1126 brw_set_dest(p, insn_or, addr);
1127
1128
1129 /* dst = send(offset, a0.0) */
1130 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1131 brw_set_dest(p, insn_send, retype(dst, BRW_REGISTER_TYPE_UW));
1132 brw_set_src0(p, insn_send, offset);
1133 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1134
1135 brw_pop_insn_state(p);
1136
1137 /* visitor knows more than we do about the surface limit required,
1138 * so has already done marking.
1139 */
1140 }
1141 }
1142
1143 /**
1144 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1145 * into the flags register (f0.0).
1146 *
1147 * Used only on Gen6 and above.
1148 */
1149 void
1150 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1151 {
1152 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1153 struct brw_reg dispatch_mask;
1154
1155 if (brw->gen >= 6)
1156 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1157 else
1158 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1159
1160 brw_push_insn_state(p);
1161 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1162 brw_MOV(p, flags, dispatch_mask);
1163 brw_pop_insn_state(p);
1164 }
1165
1166 void
1167 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1168 struct brw_reg dst,
1169 struct brw_reg src,
1170 struct brw_reg msg_data,
1171 unsigned msg_type)
1172 {
1173 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1174 msg_data.type == BRW_REGISTER_TYPE_UD);
1175
1176 brw_pixel_interpolator_query(p,
1177 retype(dst, BRW_REGISTER_TYPE_UW),
1178 src,
1179 inst->pi_noperspective,
1180 msg_type,
1181 msg_data.dw1.ud,
1182 inst->mlen,
1183 inst->regs_written);
1184 }
1185
1186
1187 static uint32_t brw_file_from_reg(fs_reg *reg)
1188 {
1189 switch (reg->file) {
1190 case GRF:
1191 return BRW_GENERAL_REGISTER_FILE;
1192 case MRF:
1193 return BRW_MESSAGE_REGISTER_FILE;
1194 case IMM:
1195 return BRW_IMMEDIATE_VALUE;
1196 default:
1197 unreachable("not reached");
1198 }
1199 }
1200
1201 struct brw_reg
1202 brw_reg_from_fs_reg(fs_reg *reg)
1203 {
1204 struct brw_reg brw_reg;
1205
1206 switch (reg->file) {
1207 case GRF:
1208 case MRF:
1209 if (reg->stride == 0) {
1210 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
1211 } else {
1212 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1213 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
1214 }
1215
1216 brw_reg = retype(brw_reg, reg->type);
1217 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
1218 break;
1219 case IMM:
1220 switch (reg->type) {
1221 case BRW_REGISTER_TYPE_F:
1222 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
1223 break;
1224 case BRW_REGISTER_TYPE_D:
1225 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
1226 break;
1227 case BRW_REGISTER_TYPE_UD:
1228 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
1229 break;
1230 default:
1231 unreachable("not reached");
1232 }
1233 break;
1234 case HW_REG:
1235 assert(reg->type == reg->fixed_hw_reg.type);
1236 brw_reg = reg->fixed_hw_reg;
1237 break;
1238 case BAD_FILE:
1239 /* Probably unused. */
1240 brw_reg = brw_null_reg();
1241 break;
1242 case UNIFORM:
1243 unreachable("not reached");
1244 default:
1245 unreachable("not reached");
1246 }
1247 if (reg->abs)
1248 brw_reg = brw_abs(brw_reg);
1249 if (reg->negate)
1250 brw_reg = negate(brw_reg);
1251
1252 return brw_reg;
1253 }
1254
1255 /**
1256 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1257 * sampler LD messages.
1258 *
1259 * We don't want to bake it into the send message's code generation because
1260 * that means we don't get a chance to schedule the instructions.
1261 */
1262 void
1263 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1264 struct brw_reg dst,
1265 struct brw_reg value)
1266 {
1267 assert(value.file == BRW_IMMEDIATE_VALUE);
1268
1269 brw_push_insn_state(p);
1270 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1271 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1272 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1273 brw_pop_insn_state(p);
1274 }
1275
1276 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1277 * (when mask is passed as a uniform) of register mask before moving it
1278 * to register dst.
1279 */
1280 void
1281 fs_generator::generate_set_omask(fs_inst *inst,
1282 struct brw_reg dst,
1283 struct brw_reg mask)
1284 {
1285 bool stride_8_8_1 =
1286 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1287 mask.width == BRW_WIDTH_8 &&
1288 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1289
1290 bool stride_0_1_0 =
1291 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1292 mask.width == BRW_WIDTH_1 &&
1293 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1294
1295 assert(stride_8_8_1 || stride_0_1_0);
1296 assert(dst.type == BRW_REGISTER_TYPE_UW);
1297
1298 if (dispatch_width == 16)
1299 dst = vec16(dst);
1300 brw_push_insn_state(p);
1301 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1302 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1303
1304 if (stride_8_8_1) {
1305 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1306 } else if (stride_0_1_0) {
1307 brw_MOV(p, dst, retype(mask, dst.type));
1308 }
1309 brw_pop_insn_state(p);
1310 }
1311
1312 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1313 * the ADD instruction.
1314 */
1315 void
1316 fs_generator::generate_set_sample_id(fs_inst *inst,
1317 struct brw_reg dst,
1318 struct brw_reg src0,
1319 struct brw_reg src1)
1320 {
1321 assert(dst.type == BRW_REGISTER_TYPE_D ||
1322 dst.type == BRW_REGISTER_TYPE_UD);
1323 assert(src0.type == BRW_REGISTER_TYPE_D ||
1324 src0.type == BRW_REGISTER_TYPE_UD);
1325
1326 brw_push_insn_state(p);
1327 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1328 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1329 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1330 brw_ADD(p, dst, src0, reg);
1331 if (dispatch_width == 16)
1332 brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
1333 brw_pop_insn_state(p);
1334 }
1335
1336 /**
1337 * Change the register's data type from UD to W, doubling the strides in order
1338 * to compensate for halving the data type width.
1339 */
1340 static struct brw_reg
1341 ud_reg_to_w(struct brw_reg r)
1342 {
1343 assert(r.type == BRW_REGISTER_TYPE_UD);
1344 r.type = BRW_REGISTER_TYPE_W;
1345
1346 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1347 * doubles the real stride.
1348 */
1349 if (r.hstride != 0)
1350 ++r.hstride;
1351 if (r.vstride != 0)
1352 ++r.vstride;
1353
1354 return r;
1355 }
1356
1357 void
1358 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1359 struct brw_reg dst,
1360 struct brw_reg x,
1361 struct brw_reg y)
1362 {
1363 assert(brw->gen >= 7);
1364 assert(dst.type == BRW_REGISTER_TYPE_UD);
1365 assert(x.type == BRW_REGISTER_TYPE_F);
1366 assert(y.type == BRW_REGISTER_TYPE_F);
1367
1368 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1369 *
1370 * Because this instruction does not have a 16-bit floating-point type,
1371 * the destination data type must be Word (W).
1372 *
1373 * The destination must be DWord-aligned and specify a horizontal stride
1374 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1375 * each destination channel and the upper word is not modified.
1376 */
1377 struct brw_reg dst_w = ud_reg_to_w(dst);
1378
1379 /* Give each 32-bit channel of dst the form below , where "." means
1380 * unchanged.
1381 * 0x....hhhh
1382 */
1383 brw_F32TO16(p, dst_w, y);
1384
1385 /* Now the form:
1386 * 0xhhhh0000
1387 */
1388 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1389
1390 /* And, finally the form of packHalf2x16's output:
1391 * 0xhhhhllll
1392 */
1393 brw_F32TO16(p, dst_w, x);
1394 }
1395
1396 void
1397 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1398 struct brw_reg dst,
1399 struct brw_reg src)
1400 {
1401 assert(brw->gen >= 7);
1402 assert(dst.type == BRW_REGISTER_TYPE_F);
1403 assert(src.type == BRW_REGISTER_TYPE_UD);
1404
1405 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1406 *
1407 * Because this instruction does not have a 16-bit floating-point type,
1408 * the source data type must be Word (W). The destination type must be
1409 * F (Float).
1410 */
1411 struct brw_reg src_w = ud_reg_to_w(src);
1412
1413 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1414 * For the Y case, we wish to access only the upper word; therefore
1415 * a 16-bit subregister offset is needed.
1416 */
1417 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1418 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1419 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1420 src_w.subnr += 2;
1421
1422 brw_F16TO32(p, dst, src_w);
1423 }
1424
1425 void
1426 fs_generator::generate_shader_time_add(fs_inst *inst,
1427 struct brw_reg payload,
1428 struct brw_reg offset,
1429 struct brw_reg value)
1430 {
1431 assert(brw->gen >= 7);
1432 brw_push_insn_state(p);
1433 brw_set_default_mask_control(p, true);
1434
1435 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1436 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1437 offset.type);
1438 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1439 value.type);
1440
1441 assert(offset.file == BRW_IMMEDIATE_VALUE);
1442 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1443 value.width = BRW_WIDTH_1;
1444 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1445 value.vstride = BRW_VERTICAL_STRIDE_0;
1446 } else {
1447 assert(value.file == BRW_IMMEDIATE_VALUE);
1448 }
1449
1450 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1451 * case, and we don't really care about squeezing every bit of performance
1452 * out of this path, so we just emit the MOVs from here.
1453 */
1454 brw_MOV(p, payload_offset, offset);
1455 brw_MOV(p, payload_value, value);
1456 brw_shader_time_add(p, payload,
1457 prog_data->binding_table.shader_time_start);
1458 brw_pop_insn_state(p);
1459
1460 brw_mark_surface_used(prog_data,
1461 prog_data->binding_table.shader_time_start);
1462 }
1463
1464 void
1465 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1466 struct brw_reg atomic_op,
1467 struct brw_reg surf_index)
1468 {
1469 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1470 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1471 surf_index.file == BRW_IMMEDIATE_VALUE &&
1472 surf_index.type == BRW_REGISTER_TYPE_UD);
1473
1474 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1475 atomic_op.dw1.ud, surf_index.dw1.ud,
1476 inst->mlen, dispatch_width / 8);
1477
1478 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1479 }
1480
1481 void
1482 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1483 struct brw_reg surf_index)
1484 {
1485 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1486 surf_index.type == BRW_REGISTER_TYPE_UD);
1487
1488 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1489 surf_index.dw1.ud,
1490 inst->mlen, dispatch_width / 8);
1491
1492 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1493 }
1494
1495 void
1496 fs_generator::generate_code(const cfg_t *cfg)
1497 {
1498 int start_offset = p->next_insn_offset;
1499 int loop_count = 0;
1500
1501 struct annotation_info annotation;
1502 memset(&annotation, 0, sizeof(annotation));
1503
1504 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1505 struct brw_reg src[3], dst;
1506 unsigned int last_insn_offset = p->next_insn_offset;
1507
1508 if (unlikely(debug_flag))
1509 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1510
1511 for (unsigned int i = 0; i < inst->sources; i++) {
1512 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1513
1514 /* The accumulator result appears to get used for the
1515 * conditional modifier generation. When negating a UD
1516 * value, there is a 33rd bit generated for the sign in the
1517 * accumulator value, so now you can't check, for example,
1518 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1519 */
1520 assert(!inst->conditional_mod ||
1521 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1522 !inst->src[i].negate);
1523 }
1524 dst = brw_reg_from_fs_reg(&inst->dst);
1525
1526 brw_set_default_predicate_control(p, inst->predicate);
1527 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1528 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1529 brw_set_default_saturate(p, inst->saturate);
1530 brw_set_default_mask_control(p, inst->force_writemask_all);
1531 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1532
1533 if (inst->force_uncompressed || dispatch_width == 8) {
1534 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1535 } else if (inst->force_sechalf) {
1536 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1537 } else {
1538 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1539 }
1540
1541 switch (inst->opcode) {
1542 case BRW_OPCODE_MOV:
1543 brw_MOV(p, dst, src[0]);
1544 break;
1545 case BRW_OPCODE_ADD:
1546 brw_ADD(p, dst, src[0], src[1]);
1547 break;
1548 case BRW_OPCODE_MUL:
1549 brw_MUL(p, dst, src[0], src[1]);
1550 break;
1551 case BRW_OPCODE_AVG:
1552 brw_AVG(p, dst, src[0], src[1]);
1553 break;
1554 case BRW_OPCODE_MACH:
1555 brw_MACH(p, dst, src[0], src[1]);
1556 break;
1557
1558 case BRW_OPCODE_MAD:
1559 assert(brw->gen >= 6);
1560 brw_set_default_access_mode(p, BRW_ALIGN_16);
1561 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1562 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1563 brw_MAD(p, dst, src[0], src[1], src[2]);
1564 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1565 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1566 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1567 } else {
1568 brw_MAD(p, dst, src[0], src[1], src[2]);
1569 }
1570 brw_set_default_access_mode(p, BRW_ALIGN_1);
1571 break;
1572
1573 case BRW_OPCODE_LRP:
1574 assert(brw->gen >= 6);
1575 brw_set_default_access_mode(p, BRW_ALIGN_16);
1576 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1577 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1578 brw_LRP(p, dst, src[0], src[1], src[2]);
1579 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1580 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1581 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1582 } else {
1583 brw_LRP(p, dst, src[0], src[1], src[2]);
1584 }
1585 brw_set_default_access_mode(p, BRW_ALIGN_1);
1586 break;
1587
1588 case BRW_OPCODE_FRC:
1589 brw_FRC(p, dst, src[0]);
1590 break;
1591 case BRW_OPCODE_RNDD:
1592 brw_RNDD(p, dst, src[0]);
1593 break;
1594 case BRW_OPCODE_RNDE:
1595 brw_RNDE(p, dst, src[0]);
1596 break;
1597 case BRW_OPCODE_RNDZ:
1598 brw_RNDZ(p, dst, src[0]);
1599 break;
1600
1601 case BRW_OPCODE_AND:
1602 brw_AND(p, dst, src[0], src[1]);
1603 break;
1604 case BRW_OPCODE_OR:
1605 brw_OR(p, dst, src[0], src[1]);
1606 break;
1607 case BRW_OPCODE_XOR:
1608 brw_XOR(p, dst, src[0], src[1]);
1609 break;
1610 case BRW_OPCODE_NOT:
1611 brw_NOT(p, dst, src[0]);
1612 break;
1613 case BRW_OPCODE_ASR:
1614 brw_ASR(p, dst, src[0], src[1]);
1615 break;
1616 case BRW_OPCODE_SHR:
1617 brw_SHR(p, dst, src[0], src[1]);
1618 break;
1619 case BRW_OPCODE_SHL:
1620 brw_SHL(p, dst, src[0], src[1]);
1621 break;
1622 case BRW_OPCODE_F32TO16:
1623 assert(brw->gen >= 7);
1624 brw_F32TO16(p, dst, src[0]);
1625 break;
1626 case BRW_OPCODE_F16TO32:
1627 assert(brw->gen >= 7);
1628 brw_F16TO32(p, dst, src[0]);
1629 break;
1630 case BRW_OPCODE_CMP:
1631 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1632 break;
1633 case BRW_OPCODE_SEL:
1634 brw_SEL(p, dst, src[0], src[1]);
1635 break;
1636 case BRW_OPCODE_BFREV:
1637 assert(brw->gen >= 7);
1638 /* BFREV only supports UD type for src and dst. */
1639 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1640 retype(src[0], BRW_REGISTER_TYPE_UD));
1641 break;
1642 case BRW_OPCODE_FBH:
1643 assert(brw->gen >= 7);
1644 /* FBH only supports UD type for dst. */
1645 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1646 break;
1647 case BRW_OPCODE_FBL:
1648 assert(brw->gen >= 7);
1649 /* FBL only supports UD type for dst. */
1650 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1651 break;
1652 case BRW_OPCODE_CBIT:
1653 assert(brw->gen >= 7);
1654 /* CBIT only supports UD type for dst. */
1655 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1656 break;
1657 case BRW_OPCODE_ADDC:
1658 assert(brw->gen >= 7);
1659 brw_ADDC(p, dst, src[0], src[1]);
1660 break;
1661 case BRW_OPCODE_SUBB:
1662 assert(brw->gen >= 7);
1663 brw_SUBB(p, dst, src[0], src[1]);
1664 break;
1665 case BRW_OPCODE_MAC:
1666 brw_MAC(p, dst, src[0], src[1]);
1667 break;
1668
1669 case BRW_OPCODE_BFE:
1670 assert(brw->gen >= 7);
1671 brw_set_default_access_mode(p, BRW_ALIGN_16);
1672 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1673 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1674 brw_BFE(p, dst, src[0], src[1], src[2]);
1675 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1676 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1677 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1678 } else {
1679 brw_BFE(p, dst, src[0], src[1], src[2]);
1680 }
1681 brw_set_default_access_mode(p, BRW_ALIGN_1);
1682 break;
1683
1684 case BRW_OPCODE_BFI1:
1685 assert(brw->gen >= 7);
1686 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1687 * should
1688 *
1689 * "Force BFI instructions to be executed always in SIMD8."
1690 */
1691 if (dispatch_width == 16 && brw->is_haswell) {
1692 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1693 brw_BFI1(p, dst, src[0], src[1]);
1694 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1695 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1696 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1697 } else {
1698 brw_BFI1(p, dst, src[0], src[1]);
1699 }
1700 break;
1701 case BRW_OPCODE_BFI2:
1702 assert(brw->gen >= 7);
1703 brw_set_default_access_mode(p, BRW_ALIGN_16);
1704 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1705 * should
1706 *
1707 * "Force BFI instructions to be executed always in SIMD8."
1708 *
1709 * Otherwise we would be able to emit compressed instructions like we
1710 * do for the other three-source instructions.
1711 */
1712 if (dispatch_width == 16) {
1713 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1714 brw_BFI2(p, dst, src[0], src[1], src[2]);
1715 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1716 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1717 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1718 } else {
1719 brw_BFI2(p, dst, src[0], src[1], src[2]);
1720 }
1721 brw_set_default_access_mode(p, BRW_ALIGN_1);
1722 break;
1723
1724 case BRW_OPCODE_IF:
1725 if (inst->src[0].file != BAD_FILE) {
1726 /* The instruction has an embedded compare (only allowed on gen6) */
1727 assert(brw->gen == 6);
1728 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1729 } else {
1730 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1731 }
1732 break;
1733
1734 case BRW_OPCODE_ELSE:
1735 brw_ELSE(p);
1736 break;
1737 case BRW_OPCODE_ENDIF:
1738 brw_ENDIF(p);
1739 break;
1740
1741 case BRW_OPCODE_DO:
1742 brw_DO(p, BRW_EXECUTE_8);
1743 break;
1744
1745 case BRW_OPCODE_BREAK:
1746 brw_BREAK(p);
1747 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1748 break;
1749 case BRW_OPCODE_CONTINUE:
1750 brw_CONT(p);
1751 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1752 break;
1753
1754 case BRW_OPCODE_WHILE:
1755 brw_WHILE(p);
1756 loop_count++;
1757 break;
1758
1759 case SHADER_OPCODE_RCP:
1760 case SHADER_OPCODE_RSQ:
1761 case SHADER_OPCODE_SQRT:
1762 case SHADER_OPCODE_EXP2:
1763 case SHADER_OPCODE_LOG2:
1764 case SHADER_OPCODE_SIN:
1765 case SHADER_OPCODE_COS:
1766 assert(brw->gen < 6 || inst->mlen == 0);
1767 if (brw->gen >= 7) {
1768 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1769 brw_null_reg());
1770 } else if (brw->gen == 6) {
1771 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1772 } else if (brw->gen == 5 || brw->is_g4x) {
1773 generate_math_g45(inst, dst, src[0]);
1774 } else {
1775 generate_math_gen4(inst, dst, src[0]);
1776 }
1777 break;
1778 case SHADER_OPCODE_INT_QUOTIENT:
1779 case SHADER_OPCODE_INT_REMAINDER:
1780 case SHADER_OPCODE_POW:
1781 assert(brw->gen < 6 || inst->mlen == 0);
1782 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1783 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1784 } else if (brw->gen >= 6) {
1785 generate_math_gen6(inst, dst, src[0], src[1]);
1786 } else {
1787 generate_math_gen4(inst, dst, src[0]);
1788 }
1789 break;
1790 case FS_OPCODE_PIXEL_X:
1791 generate_pixel_xy(dst, true);
1792 break;
1793 case FS_OPCODE_PIXEL_Y:
1794 generate_pixel_xy(dst, false);
1795 break;
1796 case FS_OPCODE_CINTERP:
1797 brw_MOV(p, dst, src[0]);
1798 break;
1799 case FS_OPCODE_LINTERP:
1800 generate_linterp(inst, dst, src);
1801 break;
1802 case SHADER_OPCODE_TEX:
1803 case FS_OPCODE_TXB:
1804 case SHADER_OPCODE_TXD:
1805 case SHADER_OPCODE_TXF:
1806 case SHADER_OPCODE_TXF_CMS:
1807 case SHADER_OPCODE_TXF_UMS:
1808 case SHADER_OPCODE_TXF_MCS:
1809 case SHADER_OPCODE_TXL:
1810 case SHADER_OPCODE_TXS:
1811 case SHADER_OPCODE_LOD:
1812 case SHADER_OPCODE_TG4:
1813 case SHADER_OPCODE_TG4_OFFSET:
1814 generate_tex(inst, dst, src[0], src[1]);
1815 break;
1816 case FS_OPCODE_DDX:
1817 generate_ddx(inst, dst, src[0], src[1]);
1818 break;
1819 case FS_OPCODE_DDY:
1820 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1821 * guarantee that key->render_to_fbo is set).
1822 */
1823 assert(stage == MESA_SHADER_FRAGMENT &&
1824 ((gl_fragment_program *) prog)->UsesDFdy);
1825 generate_ddy(inst, dst, src[0], src[1],
1826 ((brw_wm_prog_key * const) this->key)->render_to_fbo);
1827 break;
1828
1829 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1830 generate_scratch_write(inst, src[0]);
1831 break;
1832
1833 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1834 generate_scratch_read(inst, dst);
1835 break;
1836
1837 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1838 generate_scratch_read_gen7(inst, dst);
1839 break;
1840
1841 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1842 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1843 break;
1844
1845 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1846 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1847 break;
1848
1849 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1850 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1851 break;
1852
1853 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1854 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1855 break;
1856
1857 case FS_OPCODE_REP_FB_WRITE:
1858 case FS_OPCODE_FB_WRITE:
1859 generate_fb_write(inst);
1860 break;
1861
1862 case FS_OPCODE_BLORP_FB_WRITE:
1863 generate_blorp_fb_write(inst);
1864 break;
1865
1866 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1867 generate_mov_dispatch_to_flags(inst);
1868 break;
1869
1870 case FS_OPCODE_DISCARD_JUMP:
1871 generate_discard_jump(inst);
1872 break;
1873
1874 case SHADER_OPCODE_SHADER_TIME_ADD:
1875 generate_shader_time_add(inst, src[0], src[1], src[2]);
1876 break;
1877
1878 case SHADER_OPCODE_UNTYPED_ATOMIC:
1879 generate_untyped_atomic(inst, dst, src[0], src[1]);
1880 break;
1881
1882 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1883 generate_untyped_surface_read(inst, dst, src[0]);
1884 break;
1885
1886 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1887 generate_set_simd4x2_offset(inst, dst, src[0]);
1888 break;
1889
1890 case FS_OPCODE_SET_OMASK:
1891 generate_set_omask(inst, dst, src[0]);
1892 break;
1893
1894 case FS_OPCODE_SET_SAMPLE_ID:
1895 generate_set_sample_id(inst, dst, src[0], src[1]);
1896 break;
1897
1898 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1899 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1900 break;
1901
1902 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1903 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1904 generate_unpack_half_2x16_split(inst, dst, src[0]);
1905 break;
1906
1907 case FS_OPCODE_PLACEHOLDER_HALT:
1908 /* This is the place where the final HALT needs to be inserted if
1909 * we've emitted any discards. If not, this will emit no code.
1910 */
1911 if (!patch_discard_jumps_to_fb_writes()) {
1912 if (unlikely(debug_flag)) {
1913 annotation.ann_count--;
1914 }
1915 }
1916 break;
1917
1918 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
1919 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1920 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
1921 break;
1922
1923 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
1924 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1925 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
1926 break;
1927
1928 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
1929 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1930 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
1931 break;
1932
1933 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
1934 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1935 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
1936 break;
1937
1938 default:
1939 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1940 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1941 opcode_descs[inst->opcode].name);
1942 } else {
1943 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1944 }
1945 abort();
1946
1947 case SHADER_OPCODE_LOAD_PAYLOAD:
1948 unreachable("Should be lowered by lower_load_payload()");
1949 }
1950
1951 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1952 assert(p->next_insn_offset == last_insn_offset + 16 ||
1953 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1954 "emitting more than 1 instruction");
1955
1956 brw_inst *last = &p->store[last_insn_offset / 16];
1957
1958 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
1959 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
1960 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
1961 }
1962 }
1963
1964 brw_set_uip_jip(p);
1965 annotation_finalize(&annotation, p->next_insn_offset);
1966
1967 int before_size = p->next_insn_offset - start_offset;
1968 brw_compact_instructions(p, start_offset, annotation.ann_count,
1969 annotation.ann);
1970 int after_size = p->next_insn_offset - start_offset;
1971
1972 if (unlikely(debug_flag)) {
1973 if (shader_prog) {
1974 fprintf(stderr,
1975 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
1976 shader_prog->Label ? shader_prog->Label : "unnamed",
1977 shader_prog->Name, dispatch_width);
1978 } else if (prog) {
1979 fprintf(stderr,
1980 "Native code for fragment program %d (SIMD%d dispatch):\n",
1981 prog->Id, dispatch_width);
1982 } else {
1983 fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
1984 dispatch_width);
1985 }
1986 fprintf(stderr, "SIMD%d shader: %d instructions. %d loops. Compacted %d to %d"
1987 " bytes (%.0f%%)\n",
1988 dispatch_width, before_size / 16, loop_count, before_size, after_size,
1989 100.0f * (before_size - after_size) / before_size);
1990
1991 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
1992 ralloc_free(annotation.ann);
1993 }
1994 }
1995
1996 const unsigned *
1997 fs_generator::generate_assembly(const cfg_t *simd8_cfg,
1998 const cfg_t *simd16_cfg,
1999 unsigned *assembly_size)
2000 {
2001 assert(simd8_cfg || simd16_cfg);
2002
2003 if (simd8_cfg) {
2004 dispatch_width = 8;
2005 generate_code(simd8_cfg);
2006 }
2007
2008 if (simd16_cfg) {
2009 /* align to 64 byte boundary. */
2010 while (p->next_insn_offset % 64) {
2011 brw_NOP(p);
2012 }
2013
2014 assert(stage == MESA_SHADER_FRAGMENT);
2015 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
2016
2017 /* Save off the start of this SIMD16 program */
2018 prog_data->prog_offset_16 = p->next_insn_offset;
2019
2020 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
2021
2022 dispatch_width = 16;
2023 generate_code(simd16_cfg);
2024 }
2025
2026 return brw_get_program(p, assembly_size);
2027 }