2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
33 #include "brw_program.h"
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg
*reg
)
40 return BRW_ARCHITECTURE_REGISTER_FILE
;
43 return BRW_GENERAL_REGISTER_FILE
;
45 return BRW_MESSAGE_REGISTER_FILE
;
47 return BRW_IMMEDIATE_VALUE
;
51 unreachable("not reached");
53 return BRW_ARCHITECTURE_REGISTER_FILE
;
57 brw_reg_from_fs_reg(fs_inst
*inst
, fs_reg
*reg
, unsigned gen
)
59 struct brw_reg brw_reg
;
63 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(gen
));
66 if (reg
->stride
== 0) {
67 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
68 } else if (inst
->exec_size
< 8) {
69 brw_reg
= brw_vec8_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
70 brw_reg
= stride(brw_reg
, inst
->exec_size
* reg
->stride
,
71 inst
->exec_size
, reg
->stride
);
73 /* From the Haswell PRM:
75 * VertStride must be used to cross GRF register boundaries. This
76 * rule implies that elements within a 'Width' cannot cross GRF
79 * So, for registers with width > 8, we have to use a width of 8
80 * and trust the compression state to sort out the exec size.
82 brw_reg
= brw_vec8_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
83 brw_reg
= stride(brw_reg
, 8 * reg
->stride
, 8, reg
->stride
);
86 brw_reg
= retype(brw_reg
, reg
->type
);
87 brw_reg
= byte_offset(brw_reg
, reg
->subreg_offset
);
88 brw_reg
.abs
= reg
->abs
;
89 brw_reg
.negate
= reg
->negate
;
94 brw_reg
= reg
->as_brw_reg();
97 /* Probably unused. */
98 brw_reg
= brw_null_reg();
102 unreachable("not reached");
108 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
111 struct brw_stage_prog_data
*prog_data
,
112 unsigned promoted_constants
,
113 bool runtime_check_aads_emit
,
114 gl_shader_stage stage
)
116 : compiler(compiler
), log_data(log_data
),
117 devinfo(compiler
->devinfo
), key(key
),
118 prog_data(prog_data
),
119 promoted_constants(promoted_constants
),
120 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
121 stage(stage
), mem_ctx(mem_ctx
)
123 p
= rzalloc(mem_ctx
, struct brw_codegen
);
124 brw_init_codegen(devinfo
, p
, mem_ctx
);
127 fs_generator::~fs_generator()
131 class ip_record
: public exec_node
{
133 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
144 fs_generator::patch_discard_jumps_to_fb_writes()
146 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
149 int scale
= brw_jump_scale(p
->devinfo
);
151 /* There is a somewhat strange undocumented requirement of using
152 * HALT, according to the simulator. If some channel has HALTed to
153 * a particular UIP, then by the end of the program, every channel
154 * must have HALTed to that UIP. Furthermore, the tracking is a
155 * stack, so you can't do the final halt of a UIP after starting
156 * halting to a new UIP.
158 * Symptoms of not emitting this instruction on actual hardware
159 * included GPU hangs and sparkly rendering on the piglit discard
162 brw_inst
*last_halt
= gen6_HALT(p
);
163 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
164 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
168 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
169 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
171 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
172 /* HALT takes a half-instruction distance from the pre-incremented IP. */
173 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
176 this->discard_halt_patches
.make_empty();
181 fs_generator::fire_fb_write(fs_inst
*inst
,
182 struct brw_reg payload
,
183 struct brw_reg implied_header
,
186 uint32_t msg_control
;
188 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
190 if (devinfo
->gen
< 6) {
191 brw_push_insn_state(p
);
192 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
193 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
194 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
195 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
196 brw_MOV(p
, offset(payload
, 1), brw_vec8_grf(1, 0));
197 brw_pop_insn_state(p
);
200 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
)
201 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
202 else if (prog_data
->dual_src_blend
) {
203 if (!inst
->force_sechalf
)
204 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
206 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
207 } else if (inst
->exec_size
== 16)
208 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
210 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
212 uint32_t surf_index
=
213 prog_data
->binding_table
.render_target_start
+ inst
->target
;
215 bool last_render_target
= inst
->eot
||
216 (prog_data
->dual_src_blend
&& dispatch_width
== 16);
229 inst
->header_size
!= 0);
231 brw_mark_surface_used(&prog_data
->base
, surf_index
);
235 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
237 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
238 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
239 struct brw_reg implied_header
;
241 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
242 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
245 if (inst
->base_mrf
>= 0)
246 payload
= brw_message_reg(inst
->base_mrf
);
248 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
251 if (inst
->header_size
!= 0) {
252 brw_push_insn_state(p
);
253 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
254 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
255 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
256 brw_set_default_flag_reg(p
, 0, 0);
258 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
261 if (prog_data
->uses_kill
) {
262 struct brw_reg pixel_mask
;
264 if (devinfo
->gen
>= 6)
265 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
267 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
269 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
272 if (devinfo
->gen
>= 6) {
273 brw_push_insn_state(p
);
274 brw_set_default_exec_size(p
, BRW_EXECUTE_16
);
275 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
277 retype(payload
, BRW_REGISTER_TYPE_UD
),
278 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
279 brw_pop_insn_state(p
);
281 if (inst
->target
> 0 && key
->replicate_alpha
) {
282 /* Set "Source0 Alpha Present to RenderTarget" bit in message
286 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
287 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
288 brw_imm_ud(0x1 << 11));
291 if (inst
->target
> 0) {
292 /* Set the render target index for choosing BLEND_STATE. */
293 brw_MOV(p
, retype(vec1(suboffset(payload
, 2)),
294 BRW_REGISTER_TYPE_UD
),
295 brw_imm_ud(inst
->target
));
298 /* Set computes stencil to render target */
299 if (prog_data
->computed_stencil
) {
301 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
302 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
303 brw_imm_ud(0x1 << 14));
306 implied_header
= brw_null_reg();
308 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
311 brw_pop_insn_state(p
);
313 implied_header
= brw_null_reg();
316 if (!runtime_check_aads_emit
) {
317 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
319 /* This can only happen in gen < 6 */
320 assert(devinfo
->gen
< 6);
322 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
324 /* Check runtime bit to detect if we have to send AA data or not */
325 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
328 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
330 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
332 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
333 brw_inst_set_exec_size(p
->devinfo
, brw_last_inst
, BRW_EXECUTE_1
);
335 /* Don't send AA data */
336 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
338 brw_land_fwd_jump(p
, jmp
);
339 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
344 fs_generator::generate_mov_indirect(fs_inst
*inst
,
347 struct brw_reg indirect_byte_offset
)
349 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
350 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
352 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
354 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
355 imm_byte_offset
+= indirect_byte_offset
.ud
;
357 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
358 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
359 brw_MOV(p
, dst
, reg
);
361 /* Prior to Broadwell, there are only 8 address registers. */
362 assert(inst
->exec_size
== 8 || devinfo
->gen
>= 8);
364 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
365 struct brw_reg addr
= vec8(brw_address_reg(0));
367 /* The destination stride of an instruction (in bytes) must be greater
368 * than or equal to the size of the rest of the instruction. Since the
369 * address register is of type UW, we can't use a D-type instruction.
370 * In order to get around this, re retype to UW and use a stride.
372 indirect_byte_offset
=
373 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
375 struct brw_reg ind_src
;
376 if (devinfo
->gen
< 8) {
377 /* From the Haswell PRM section "Register Region Restrictions":
379 * "The lower bits of the AddressImmediate must not overflow to
380 * change the register address. The lower 5 bits of Address
381 * Immediate when added to lower 5 bits of address register gives
382 * the sub-register offset. The upper bits of Address Immediate
383 * when added to upper bits of address register gives the register
384 * address. Any overflow from sub-register offset is dropped."
386 * This restriction is only listed in the Haswell PRM but emperical
387 * testing indicates that it applies on all older generations and is
388 * lifted on Broadwell.
390 * Since the indirect may cause us to cross a register boundary, this
391 * makes the base offset almost useless. We could try and do
392 * something clever where we use a actual base offset if
393 * base_offset % 32 == 0 but that would mean we were generating
394 * different code depending on the base offset. Instead, for the
395 * sake of consistency, we'll just do the add ourselves.
397 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
398 ind_src
= brw_VxH_indirect(0, 0);
400 brw_MOV(p
, addr
, indirect_byte_offset
);
401 ind_src
= brw_VxH_indirect(0, imm_byte_offset
);
404 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, dst
.type
));
406 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
407 !inst
->get_next()->is_tail_sentinel() &&
408 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
409 /* From the Sandybridge PRM:
411 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
412 * instruction that “indexed/indirect” source AND is followed by a
413 * send, the instruction requires a “Switch”. This is to avoid
414 * race condition where send may dispatch before MRF is updated."
416 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
422 fs_generator::generate_urb_read(fs_inst
*inst
,
424 struct brw_reg header
)
426 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
427 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
429 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
430 brw_set_dest(p
, send
, dst
);
431 brw_set_src0(p
, send
, header
);
432 brw_set_src1(p
, send
, brw_imm_ud(0u));
434 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
435 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
437 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
438 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
440 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
441 brw_inst_set_rlen(p
->devinfo
, send
, inst
->regs_written
);
442 brw_inst_set_header_present(p
->devinfo
, send
, true);
443 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
447 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
451 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
453 brw_set_dest(p
, insn
, brw_null_reg());
454 brw_set_src0(p
, insn
, payload
);
455 brw_set_src1(p
, insn
, brw_imm_d(0));
457 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
458 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
460 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
461 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
462 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
464 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
465 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
466 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
468 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
469 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
470 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
471 brw_inst_set_header_present(p
->devinfo
, insn
, true);
472 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
476 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
478 struct brw_inst
*insn
;
480 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
482 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
483 brw_set_src0(p
, insn
, payload
);
484 brw_set_src1(p
, insn
, brw_imm_d(0));
486 /* Terminate a compute shader by sending a message to the thread spawner.
488 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
489 brw_inst_set_mlen(devinfo
, insn
, 1);
490 brw_inst_set_rlen(devinfo
, insn
, 0);
491 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
492 brw_inst_set_header_present(devinfo
, insn
, false);
494 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
495 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
497 /* Note that even though the thread has a URB resource associated with it,
498 * we set the "do not dereference URB" bit, because the URB resource is
499 * managed by the fixed-function unit, so it will free it automatically.
501 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
503 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
507 fs_generator::generate_stencil_ref_packing(fs_inst
*inst
,
511 assert(dispatch_width
== 8);
512 assert(devinfo
->gen
>= 9);
514 /* Stencil value updates are provided in 8 slots of 1 byte per slot.
515 * Presumably, in order to save memory bandwidth, the stencil reference
516 * values written from the FS need to be packed into 2 dwords (this makes
517 * sense because the stencil values are limited to 1 byte each and a SIMD8
518 * send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
520 * The spec is confusing here because in the payload definition of MDP_RTW_S8
521 * (Message Data Payload for Render Target Writes with Stencil 8b) the
522 * stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
523 * dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
524 * packed values specified above and diagrammed below:
527 * --------------------------------
531 * --------------------------------
532 * DW1 | STC | STC | STC | STC |
533 * | slot7 | slot6 | slot5 | slot4|
534 * --------------------------------
535 * DW0 | STC | STC | STC | STC |
536 * | slot3 | slot2 | slot1 | slot0|
537 * --------------------------------
540 src
.vstride
= BRW_VERTICAL_STRIDE_4
;
541 src
.width
= BRW_WIDTH_1
;
542 src
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
543 assert(src
.type
== BRW_REGISTER_TYPE_UB
);
544 brw_MOV(p
, retype(dst
, BRW_REGISTER_TYPE_UB
), src
);
548 fs_generator::generate_barrier(fs_inst
*inst
, struct brw_reg src
)
555 fs_generator::generate_blorp_fb_write(fs_inst
*inst
, struct brw_reg payload
)
558 16 /* dispatch_width */,
559 inst
->base_mrf
>= 0 ?
560 brw_message_reg(inst
->base_mrf
) : payload
,
562 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
,
568 inst
->header_size
!= 0);
572 fs_generator::generate_linterp(fs_inst
*inst
,
573 struct brw_reg dst
, struct brw_reg
*src
)
577 * -----------------------------------
578 * | src1+0 | src1+1 | src1+2 | src1+3 |
579 * |-----------------------------------|
580 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
581 * -----------------------------------
583 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
585 * -----------------------------------
586 * | src1+0 | src1+1 | src1+2 | src1+3 |
587 * |-----------------------------------|
588 * |(x0, x1)|(y0, y1)| | | in SIMD8
589 * |-----------------------------------|
590 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
591 * -----------------------------------
593 * See also: emit_interpolation_setup_gen4().
595 struct brw_reg delta_x
= src
[0];
596 struct brw_reg delta_y
= offset(src
[0], dispatch_width
/ 8);
597 struct brw_reg interp
= src
[1];
599 if (devinfo
->has_pln
&&
600 (devinfo
->gen
>= 7 || (delta_x
.nr
& 1) == 0)) {
601 brw_PLN(p
, dst
, interp
, delta_x
);
603 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
604 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
609 fs_generator::generate_math_gen6(fs_inst
*inst
,
614 int op
= brw_math_function(inst
->opcode
);
615 bool binop
= src1
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
;
617 if (dispatch_width
== 8) {
618 gen6_math(p
, dst
, op
, src0
, src1
);
619 } else if (dispatch_width
== 16) {
620 brw_push_insn_state(p
);
621 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
622 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
623 gen6_math(p
, firsthalf(dst
), op
, firsthalf(src0
), firsthalf(src1
));
624 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
625 gen6_math(p
, sechalf(dst
), op
, sechalf(src0
),
626 binop
? sechalf(src1
) : brw_null_reg());
627 brw_pop_insn_state(p
);
632 fs_generator::generate_math_gen4(fs_inst
*inst
,
636 int op
= brw_math_function(inst
->opcode
);
638 assert(inst
->mlen
>= 1);
640 if (dispatch_width
== 8) {
644 BRW_MATH_PRECISION_FULL
);
645 } else if (dispatch_width
== 16) {
646 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
647 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
648 gen4_math(p
, firsthalf(dst
),
650 inst
->base_mrf
, firsthalf(src
),
651 BRW_MATH_PRECISION_FULL
);
652 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
653 gen4_math(p
, sechalf(dst
),
655 inst
->base_mrf
+ 1, sechalf(src
),
656 BRW_MATH_PRECISION_FULL
);
658 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
663 fs_generator::generate_math_g45(fs_inst
*inst
,
667 if (inst
->opcode
== SHADER_OPCODE_POW
||
668 inst
->opcode
== SHADER_OPCODE_INT_QUOTIENT
||
669 inst
->opcode
== SHADER_OPCODE_INT_REMAINDER
) {
670 generate_math_gen4(inst
, dst
, src
);
674 int op
= brw_math_function(inst
->opcode
);
676 assert(inst
->mlen
>= 1);
681 BRW_MATH_PRECISION_FULL
);
685 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
688 struct brw_reg surf_index
)
690 assert(devinfo
->gen
>= 7);
691 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
696 switch (inst
->exec_size
) {
698 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
701 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
704 unreachable("Invalid width for texture instruction");
707 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
713 retype(dst
, BRW_REGISTER_TYPE_UW
),
718 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
719 rlen
, /* response length */
721 inst
->header_size
> 0,
723 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
725 brw_mark_surface_used(prog_data
, surf_index
.ud
);
729 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
730 struct brw_reg surface_index
,
731 struct brw_reg sampler_index
)
736 uint32_t return_format
;
737 bool is_combined_send
= inst
->eot
;
740 case BRW_REGISTER_TYPE_D
:
741 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
743 case BRW_REGISTER_TYPE_UD
:
744 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
747 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
751 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
752 * is set as part of the message descriptor. On gen4, the PRM seems to
753 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
754 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
755 * gone from the message descriptor entirely and you just get UINT32 all
756 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
757 * just stomp it to UINT32 all the time.
759 if (inst
->opcode
== SHADER_OPCODE_TXS
)
760 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
762 switch (inst
->exec_size
) {
764 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
767 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
770 unreachable("Invalid width for texture instruction");
773 if (devinfo
->gen
>= 5) {
774 switch (inst
->opcode
) {
775 case SHADER_OPCODE_TEX
:
776 if (inst
->shadow_compare
) {
777 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
779 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
783 if (inst
->shadow_compare
) {
784 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
786 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
789 case SHADER_OPCODE_TXL
:
790 if (inst
->shadow_compare
) {
791 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
793 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
796 case SHADER_OPCODE_TXS
:
797 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
799 case SHADER_OPCODE_TXD
:
800 if (inst
->shadow_compare
) {
801 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
802 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
803 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
805 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
808 case SHADER_OPCODE_TXF
:
809 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
811 case SHADER_OPCODE_TXF_CMS_W
:
812 assert(devinfo
->gen
>= 9);
813 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
815 case SHADER_OPCODE_TXF_CMS
:
816 if (devinfo
->gen
>= 7)
817 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
819 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
821 case SHADER_OPCODE_TXF_UMS
:
822 assert(devinfo
->gen
>= 7);
823 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
825 case SHADER_OPCODE_TXF_MCS
:
826 assert(devinfo
->gen
>= 7);
827 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
829 case SHADER_OPCODE_LOD
:
830 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
832 case SHADER_OPCODE_TG4
:
833 if (inst
->shadow_compare
) {
834 assert(devinfo
->gen
>= 7);
835 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
837 assert(devinfo
->gen
>= 6);
838 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
841 case SHADER_OPCODE_TG4_OFFSET
:
842 assert(devinfo
->gen
>= 7);
843 if (inst
->shadow_compare
) {
844 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
846 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
849 case SHADER_OPCODE_SAMPLEINFO
:
850 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
853 unreachable("not reached");
856 switch (inst
->opcode
) {
857 case SHADER_OPCODE_TEX
:
858 /* Note that G45 and older determines shadow compare and dispatch width
859 * from message length for most messages.
861 if (inst
->exec_size
== 8) {
862 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
863 if (inst
->shadow_compare
) {
864 assert(inst
->mlen
== 6);
866 assert(inst
->mlen
<= 4);
869 if (inst
->shadow_compare
) {
870 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
871 assert(inst
->mlen
== 9);
873 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
874 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
879 if (inst
->shadow_compare
) {
880 assert(inst
->exec_size
== 8);
881 assert(inst
->mlen
== 6);
882 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
884 assert(inst
->mlen
== 9);
885 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
886 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
889 case SHADER_OPCODE_TXL
:
890 if (inst
->shadow_compare
) {
891 assert(inst
->exec_size
== 8);
892 assert(inst
->mlen
== 6);
893 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
895 assert(inst
->mlen
== 9);
896 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
897 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
900 case SHADER_OPCODE_TXD
:
901 /* There is no sample_d_c message; comparisons are done manually */
902 assert(inst
->exec_size
== 8);
903 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
904 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
906 case SHADER_OPCODE_TXF
:
907 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
908 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
909 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
911 case SHADER_OPCODE_TXS
:
912 assert(inst
->mlen
== 3);
913 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
914 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
917 unreachable("not reached");
920 assert(msg_type
!= -1);
922 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
927 if (is_combined_send
) {
928 assert(devinfo
->gen
>= 9 || devinfo
->is_cherryview
);
932 assert(devinfo
->gen
< 7 || inst
->header_size
== 0 ||
933 src
.file
== BRW_GENERAL_REGISTER_FILE
);
935 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
937 /* Load the message header if present. If there's a texture offset,
938 * we need to set it up explicitly and load the offset bitfield.
939 * Otherwise, we can use an implied move from g0 to the first message reg.
941 if (inst
->header_size
!= 0) {
942 if (devinfo
->gen
< 6 && !inst
->offset
) {
943 /* Set up an implied move from g0 to the MRF. */
944 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
946 struct brw_reg header_reg
;
948 if (devinfo
->gen
>= 7) {
951 assert(inst
->base_mrf
!= -1);
952 header_reg
= brw_message_reg(inst
->base_mrf
);
955 brw_push_insn_state(p
);
956 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
957 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
958 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
959 /* Explicitly set up the message header by copying g0 to the MRF. */
960 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
963 /* Set the offset bits in DWord 2. */
964 brw_MOV(p
, get_element_ud(header_reg
, 2),
965 brw_imm_ud(inst
->offset
));
966 } else if (stage
!= MESA_SHADER_VERTEX
&&
967 stage
!= MESA_SHADER_FRAGMENT
) {
968 /* The vertex and fragment stages have g0.2 set to 0, so
969 * header0.2 is 0 when g0 is copied. Other stages may not, so we
970 * must set it to 0 to avoid setting undesirable bits in the
973 brw_MOV(p
, get_element_ud(header_reg
, 2), brw_imm_ud(0));
976 brw_adjust_sampler_state_pointer(p
, header_reg
, sampler_index
);
977 brw_pop_insn_state(p
);
981 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
982 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
983 ? prog_data
->binding_table
.gather_texture_start
984 : prog_data
->binding_table
.texture_start
;
986 if (surface_index
.file
== BRW_IMMEDIATE_VALUE
&&
987 sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
988 uint32_t surface
= surface_index
.ud
;
989 uint32_t sampler
= sampler_index
.ud
;
992 retype(dst
, BRW_REGISTER_TYPE_UW
),
995 surface
+ base_binding_table_index
,
1000 inst
->header_size
!= 0,
1004 brw_mark_surface_used(prog_data
, surface
+ base_binding_table_index
);
1006 /* Non-const sampler index */
1008 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1009 struct brw_reg surface_reg
= vec1(retype(surface_index
, BRW_REGISTER_TYPE_UD
));
1010 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
1012 brw_push_insn_state(p
);
1013 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1014 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1016 if (memcmp(&surface_reg
, &sampler_reg
, sizeof(surface_reg
)) == 0) {
1017 brw_MUL(p
, addr
, sampler_reg
, brw_imm_uw(0x101));
1019 brw_SHL(p
, addr
, sampler_reg
, brw_imm_ud(8));
1020 brw_OR(p
, addr
, addr
, surface_reg
);
1022 if (base_binding_table_index
)
1023 brw_ADD(p
, addr
, addr
, brw_imm_ud(base_binding_table_index
));
1024 brw_AND(p
, addr
, addr
, brw_imm_ud(0xfff));
1026 brw_pop_insn_state(p
);
1028 /* dst = send(offset, a0.0 | <descriptor>) */
1029 brw_inst
*insn
= brw_send_indirect_message(
1030 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
1031 brw_set_sampler_message(p
, insn
,
1036 inst
->mlen
/* mlen */,
1037 inst
->header_size
!= 0 /* header */,
1041 /* visitor knows more than we do about the surface limit required,
1042 * so has already done marking.
1046 if (is_combined_send
) {
1047 brw_inst_set_eot(p
->devinfo
, brw_last_inst
, true);
1048 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
1053 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1056 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1058 * Ideally, we want to produce:
1061 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1062 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1063 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1064 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1065 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1066 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1067 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1068 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1070 * and add another set of two more subspans if in 16-pixel dispatch mode.
1072 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1073 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1074 * pair. But the ideal approximation may impose a huge performance cost on
1075 * sample_d. On at least Haswell, sample_d instruction does some
1076 * optimizations if the same LOD is used for all pixels in the subspan.
1078 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1079 * appropriate swizzling.
1082 fs_generator::generate_ddx(enum opcode opcode
,
1083 struct brw_reg dst
, struct brw_reg src
)
1085 unsigned vstride
, width
;
1087 if (opcode
== FS_OPCODE_DDX_FINE
) {
1088 /* produce accurate derivatives */
1089 vstride
= BRW_VERTICAL_STRIDE_2
;
1090 width
= BRW_WIDTH_2
;
1092 /* replicate the derivative at the top-left pixel to other pixels */
1093 vstride
= BRW_VERTICAL_STRIDE_4
;
1094 width
= BRW_WIDTH_4
;
1097 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
1098 src
.negate
, src
.abs
,
1099 BRW_REGISTER_TYPE_F
,
1102 BRW_HORIZONTAL_STRIDE_0
,
1103 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1104 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
1105 src
.negate
, src
.abs
,
1106 BRW_REGISTER_TYPE_F
,
1109 BRW_HORIZONTAL_STRIDE_0
,
1110 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1111 brw_ADD(p
, dst
, src0
, negate(src1
));
1114 /* The negate_value boolean is used to negate the derivative computation for
1115 * FBOs, since they place the origin at the upper left instead of the lower
1119 fs_generator::generate_ddy(enum opcode opcode
,
1120 struct brw_reg dst
, struct brw_reg src
,
1123 if (opcode
== FS_OPCODE_DDY_FINE
) {
1124 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
1125 * Region Restrictions):
1127 * In Align16 access mode, SIMD16 is not allowed for DW operations
1128 * and SIMD8 is not allowed for DF operations.
1130 * In this context, "DW operations" means "operations acting on 32-bit
1131 * values", so it includes operations on floats.
1133 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
1134 * (Instruction Compression -> Rules and Restrictions):
1136 * A compressed instruction must be in Align1 access mode. Align16
1137 * mode instructions cannot be compressed.
1139 * Similar text exists in the g45 PRM.
1141 * Empirically, compressed align16 instructions using odd register
1142 * numbers don't appear to work on Sandybridge either.
1144 * On these platforms, if we're building a SIMD16 shader, we need to
1145 * manually unroll to a pair of SIMD8 instructions.
1147 bool unroll_to_simd8
=
1148 (dispatch_width
== 16 &&
1149 (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
1150 (devinfo
->gen
== 7 && !devinfo
->is_haswell
)));
1152 /* produce accurate derivatives */
1153 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1154 src
.negate
, src
.abs
,
1155 BRW_REGISTER_TYPE_F
,
1156 BRW_VERTICAL_STRIDE_4
,
1158 BRW_HORIZONTAL_STRIDE_1
,
1159 BRW_SWIZZLE_XYXY
, WRITEMASK_XYZW
);
1160 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
1161 src
.negate
, src
.abs
,
1162 BRW_REGISTER_TYPE_F
,
1163 BRW_VERTICAL_STRIDE_4
,
1165 BRW_HORIZONTAL_STRIDE_1
,
1166 BRW_SWIZZLE_ZWZW
, WRITEMASK_XYZW
);
1167 brw_push_insn_state(p
);
1168 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1169 if (unroll_to_simd8
) {
1170 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1171 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1173 brw_ADD(p
, firsthalf(dst
), firsthalf(src1
), negate(firsthalf(src0
)));
1174 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1175 brw_ADD(p
, sechalf(dst
), sechalf(src1
), negate(sechalf(src0
)));
1177 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), negate(firsthalf(src1
)));
1178 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1179 brw_ADD(p
, sechalf(dst
), sechalf(src0
), negate(sechalf(src1
)));
1183 brw_ADD(p
, dst
, src1
, negate(src0
));
1185 brw_ADD(p
, dst
, src0
, negate(src1
));
1187 brw_pop_insn_state(p
);
1189 /* replicate the derivative at the top-left pixel to other pixels */
1190 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1191 src
.negate
, src
.abs
,
1192 BRW_REGISTER_TYPE_F
,
1193 BRW_VERTICAL_STRIDE_4
,
1195 BRW_HORIZONTAL_STRIDE_0
,
1196 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1197 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
1198 src
.negate
, src
.abs
,
1199 BRW_REGISTER_TYPE_F
,
1200 BRW_VERTICAL_STRIDE_4
,
1202 BRW_HORIZONTAL_STRIDE_0
,
1203 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1205 brw_ADD(p
, dst
, src1
, negate(src0
));
1207 brw_ADD(p
, dst
, src0
, negate(src1
));
1212 fs_generator::generate_discard_jump(fs_inst
*inst
)
1214 assert(devinfo
->gen
>= 6);
1216 /* This HALT will be patched up at FB write time to point UIP at the end of
1217 * the program, and at brw_uip_jip() JIP will be set to the end of the
1218 * current block (or the program).
1220 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1222 brw_push_insn_state(p
);
1223 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1225 brw_pop_insn_state(p
);
1229 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1231 assert(inst
->mlen
!= 0);
1234 brw_uvec_mrf(inst
->exec_size
, (inst
->base_mrf
+ 1), 0),
1235 retype(src
, BRW_REGISTER_TYPE_UD
));
1236 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1237 inst
->exec_size
/ 8, inst
->offset
);
1241 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1243 assert(inst
->mlen
!= 0);
1245 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1246 inst
->exec_size
/ 8, inst
->offset
);
1250 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1252 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1256 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1258 struct brw_reg index
,
1259 struct brw_reg offset
)
1261 assert(inst
->mlen
!= 0);
1263 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1264 index
.type
== BRW_REGISTER_TYPE_UD
);
1265 uint32_t surf_index
= index
.ud
;
1267 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1268 offset
.type
== BRW_REGISTER_TYPE_UD
);
1269 uint32_t read_offset
= offset
.ud
;
1271 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1272 read_offset
, surf_index
);
1276 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1278 struct brw_reg index
,
1279 struct brw_reg offset
)
1281 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1283 assert(offset
.file
== BRW_GENERAL_REGISTER_FILE
);
1284 /* Reference just the dword we need, to avoid angering validate_reg(). */
1285 offset
= brw_vec1_grf(offset
.nr
, 0);
1287 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1288 * the destination loaded consecutively from the same offset (which appears
1289 * in the first component, and the rest are ignored).
1291 dst
.width
= BRW_WIDTH_4
;
1293 struct brw_reg src
= offset
;
1294 bool header_present
= false;
1296 if (devinfo
->gen
>= 9) {
1297 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1298 src
= retype(brw_vec4_grf(offset
.nr
, 0), BRW_REGISTER_TYPE_UD
);
1299 header_present
= true;
1301 brw_push_insn_state(p
);
1302 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1303 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1304 brw_MOV(p
, vec8(src
), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1305 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1307 brw_MOV(p
, get_element_ud(src
, 2),
1308 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
));
1309 brw_pop_insn_state(p
);
1312 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1314 uint32_t surf_index
= index
.ud
;
1316 brw_push_insn_state(p
);
1317 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1318 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1319 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1320 brw_inst_set_exec_size(devinfo
, send
, BRW_EXECUTE_4
);
1321 brw_pop_insn_state(p
);
1323 brw_set_dest(p
, send
, dst
);
1324 brw_set_src0(p
, send
, src
);
1325 brw_set_sampler_message(p
, send
,
1327 0, /* LD message ignores sampler unit */
1328 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1332 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1336 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1338 brw_push_insn_state(p
);
1339 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1340 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1342 /* a0.0 = surf_index & 0xff */
1343 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1344 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1345 brw_set_dest(p
, insn_and
, addr
);
1346 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1347 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1349 /* dst = send(payload, a0.0 | <descriptor>) */
1350 brw_inst
*insn
= brw_send_indirect_message(
1351 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
1352 brw_set_sampler_message(p
, insn
,
1354 0, /* LD message ignores sampler unit */
1355 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1359 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1362 brw_pop_insn_state(p
);
1367 fs_generator::generate_varying_pull_constant_load(fs_inst
*inst
,
1369 struct brw_reg index
,
1370 struct brw_reg offset
)
1372 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1373 assert(inst
->header_size
!= 0);
1376 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1377 index
.type
== BRW_REGISTER_TYPE_UD
);
1378 uint32_t surf_index
= index
.ud
;
1380 uint32_t simd_mode
, rlen
, msg_type
;
1381 if (dispatch_width
== 16) {
1382 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1385 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1389 if (devinfo
->gen
>= 5)
1390 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1392 /* We always use the SIMD16 message so that we only have to load U, and
1395 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1396 assert(inst
->mlen
== 3);
1397 assert(inst
->regs_written
== 8);
1399 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1402 struct brw_reg offset_mrf
= retype(brw_message_reg(inst
->base_mrf
+ 1),
1403 BRW_REGISTER_TYPE_D
);
1404 brw_MOV(p
, offset_mrf
, offset
);
1406 struct brw_reg header
= brw_vec8_grf(0, 0);
1407 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1409 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1410 brw_inst_set_qtr_control(p
->devinfo
, send
, BRW_COMPRESSION_NONE
);
1411 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1412 brw_set_src0(p
, send
, header
);
1413 if (devinfo
->gen
< 6)
1414 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1416 /* Our surface is set up as floats, regardless of what actual data is
1419 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1420 brw_set_sampler_message(p
, send
,
1422 0, /* sampler (unused) */
1426 inst
->header_size
!= 0,
1432 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1434 struct brw_reg index
,
1435 struct brw_reg offset
)
1437 assert(devinfo
->gen
>= 7);
1438 /* Varying-offset pull constant loads are treated as a normal expression on
1439 * gen7, so the fact that it's a send message is hidden at the IR level.
1441 assert(inst
->header_size
== 0);
1442 assert(!inst
->mlen
);
1443 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1445 uint32_t simd_mode
, rlen
, mlen
;
1446 if (dispatch_width
== 16) {
1449 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1453 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1456 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1458 uint32_t surf_index
= index
.ud
;
1460 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1461 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1462 brw_set_src0(p
, send
, offset
);
1463 brw_set_sampler_message(p
, send
,
1465 0, /* LD message ignores sampler unit */
1466 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1469 false, /* no header */
1475 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1477 brw_push_insn_state(p
);
1478 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1479 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1481 /* a0.0 = surf_index & 0xff */
1482 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1483 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1484 brw_set_dest(p
, insn_and
, addr
);
1485 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1486 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1488 brw_pop_insn_state(p
);
1490 /* dst = send(offset, a0.0 | <descriptor>) */
1491 brw_inst
*insn
= brw_send_indirect_message(
1492 p
, BRW_SFID_SAMPLER
, retype(dst
, BRW_REGISTER_TYPE_UW
),
1494 brw_set_sampler_message(p
, insn
,
1497 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1507 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1508 * into the flags register (f0.0).
1510 * Used only on Gen6 and above.
1513 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
1515 struct brw_reg flags
= brw_flag_reg(0, inst
->flag_subreg
);
1516 struct brw_reg dispatch_mask
;
1518 if (devinfo
->gen
>= 6)
1519 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1521 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1523 brw_push_insn_state(p
);
1524 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1525 brw_MOV(p
, flags
, dispatch_mask
);
1526 brw_pop_insn_state(p
);
1530 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1533 struct brw_reg msg_data
,
1536 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1538 brw_pixel_interpolator_query(p
,
1539 retype(dst
, BRW_REGISTER_TYPE_UW
),
1541 inst
->pi_noperspective
,
1545 inst
->regs_written
);
1550 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1551 * sampler LD messages.
1553 * We don't want to bake it into the send message's code generation because
1554 * that means we don't get a chance to schedule the instructions.
1557 fs_generator::generate_set_simd4x2_offset(fs_inst
*inst
,
1559 struct brw_reg value
)
1561 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1563 brw_push_insn_state(p
);
1564 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1565 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1566 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1567 brw_MOV(p
, retype(brw_vec1_reg(dst
.file
, dst
.nr
, 0), value
.type
), value
);
1568 brw_pop_insn_state(p
);
1571 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1572 * the ADD instruction.
1575 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1577 struct brw_reg src0
,
1578 struct brw_reg src1
)
1580 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1581 dst
.type
== BRW_REGISTER_TYPE_UD
);
1582 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1583 src0
.type
== BRW_REGISTER_TYPE_UD
);
1585 struct brw_reg reg
= stride(src1
, 1, 4, 0);
1586 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
1587 brw_ADD(p
, dst
, src0
, reg
);
1588 } else if (dispatch_width
== 16) {
1589 brw_push_insn_state(p
);
1590 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1591 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1592 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), reg
);
1593 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1594 brw_ADD(p
, sechalf(dst
), sechalf(src0
), suboffset(reg
, 2));
1595 brw_pop_insn_state(p
);
1600 fs_generator::generate_pack_half_2x16_split(fs_inst
*inst
,
1605 assert(devinfo
->gen
>= 7);
1606 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1607 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1608 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1610 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1612 * Because this instruction does not have a 16-bit floating-point type,
1613 * the destination data type must be Word (W).
1615 * The destination must be DWord-aligned and specify a horizontal stride
1616 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1617 * each destination channel and the upper word is not modified.
1619 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1621 /* Give each 32-bit channel of dst the form below, where "." means
1625 brw_F32TO16(p
, dst_w
, y
);
1630 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1632 /* And, finally the form of packHalf2x16's output:
1635 brw_F32TO16(p
, dst_w
, x
);
1639 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
1643 assert(devinfo
->gen
>= 7);
1644 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1645 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1647 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1649 * Because this instruction does not have a 16-bit floating-point type,
1650 * the source data type must be Word (W). The destination type must be
1653 struct brw_reg src_w
= spread(retype(src
, BRW_REGISTER_TYPE_W
), 2);
1655 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1656 * For the Y case, we wish to access only the upper word; therefore
1657 * a 16-bit subregister offset is needed.
1659 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1660 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1661 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1664 brw_F16TO32(p
, dst
, src_w
);
1668 fs_generator::generate_shader_time_add(fs_inst
*inst
,
1669 struct brw_reg payload
,
1670 struct brw_reg offset
,
1671 struct brw_reg value
)
1673 assert(devinfo
->gen
>= 7);
1674 brw_push_insn_state(p
);
1675 brw_set_default_mask_control(p
, true);
1677 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1678 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1680 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1683 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1684 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1685 value
.width
= BRW_WIDTH_1
;
1686 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1687 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1689 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1692 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1693 * case, and we don't really care about squeezing every bit of performance
1694 * out of this path, so we just emit the MOVs from here.
1696 brw_MOV(p
, payload_offset
, offset
);
1697 brw_MOV(p
, payload_value
, value
);
1698 brw_shader_time_add(p
, payload
,
1699 prog_data
->binding_table
.shader_time_start
);
1700 brw_pop_insn_state(p
);
1702 brw_mark_surface_used(prog_data
,
1703 prog_data
->binding_table
.shader_time_start
);
1707 fs_generator::enable_debug(const char *shader_name
)
1710 this->shader_name
= shader_name
;
1714 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1716 /* align to 64 byte boundary. */
1717 while (p
->next_insn_offset
% 64)
1720 this->dispatch_width
= dispatch_width
;
1721 if (dispatch_width
== 16)
1722 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1724 int start_offset
= p
->next_insn_offset
;
1725 int spill_count
= 0, fill_count
= 0;
1728 struct annotation_info annotation
;
1729 memset(&annotation
, 0, sizeof(annotation
));
1731 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1732 struct brw_reg src
[3], dst
;
1733 unsigned int last_insn_offset
= p
->next_insn_offset
;
1734 bool multiple_instructions_emitted
= false;
1736 if (unlikely(debug_flag
))
1737 annotate(p
->devinfo
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1739 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1740 src
[i
] = brw_reg_from_fs_reg(inst
, &inst
->src
[i
], devinfo
->gen
);
1742 /* The accumulator result appears to get used for the
1743 * conditional modifier generation. When negating a UD
1744 * value, there is a 33rd bit generated for the sign in the
1745 * accumulator value, so now you can't check, for example,
1746 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1748 assert(!inst
->conditional_mod
||
1749 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1750 !inst
->src
[i
].negate
);
1752 dst
= brw_reg_from_fs_reg(inst
, &inst
->dst
, devinfo
->gen
);
1754 brw_set_default_predicate_control(p
, inst
->predicate
);
1755 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1756 brw_set_default_flag_reg(p
, 0, inst
->flag_subreg
);
1757 brw_set_default_saturate(p
, inst
->saturate
);
1758 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1759 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1760 brw_set_default_exec_size(p
, cvt(inst
->exec_size
) - 1);
1762 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1763 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1765 switch (inst
->exec_size
) {
1769 assert(inst
->force_writemask_all
);
1770 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1773 if (inst
->force_sechalf
) {
1774 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1776 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1781 /* If the instruction writes to more than one register, it needs to
1782 * be a "compressed" instruction on Gen <= 5.
1784 if (inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
)
1785 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1787 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1790 unreachable("Invalid instruction width");
1793 switch (inst
->opcode
) {
1794 case BRW_OPCODE_MOV
:
1795 brw_MOV(p
, dst
, src
[0]);
1797 case BRW_OPCODE_ADD
:
1798 brw_ADD(p
, dst
, src
[0], src
[1]);
1800 case BRW_OPCODE_MUL
:
1801 brw_MUL(p
, dst
, src
[0], src
[1]);
1803 case BRW_OPCODE_AVG
:
1804 brw_AVG(p
, dst
, src
[0], src
[1]);
1806 case BRW_OPCODE_MACH
:
1807 brw_MACH(p
, dst
, src
[0], src
[1]);
1810 case BRW_OPCODE_LINE
:
1811 brw_LINE(p
, dst
, src
[0], src
[1]);
1814 case BRW_OPCODE_MAD
:
1815 assert(devinfo
->gen
>= 6);
1816 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1817 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1818 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1819 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1820 brw_inst
*f
= brw_MAD(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1821 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1822 brw_inst
*s
= brw_MAD(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1823 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1825 if (inst
->conditional_mod
) {
1826 brw_inst_set_cond_modifier(p
->devinfo
, f
, inst
->conditional_mod
);
1827 brw_inst_set_cond_modifier(p
->devinfo
, s
, inst
->conditional_mod
);
1828 multiple_instructions_emitted
= true;
1831 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1833 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1836 case BRW_OPCODE_LRP
:
1837 assert(devinfo
->gen
>= 6);
1838 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1839 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1840 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1841 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1842 brw_inst
*f
= brw_LRP(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1843 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1844 brw_inst
*s
= brw_LRP(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1845 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1847 if (inst
->conditional_mod
) {
1848 brw_inst_set_cond_modifier(p
->devinfo
, f
, inst
->conditional_mod
);
1849 brw_inst_set_cond_modifier(p
->devinfo
, s
, inst
->conditional_mod
);
1850 multiple_instructions_emitted
= true;
1853 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1855 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1858 case BRW_OPCODE_FRC
:
1859 brw_FRC(p
, dst
, src
[0]);
1861 case BRW_OPCODE_RNDD
:
1862 brw_RNDD(p
, dst
, src
[0]);
1864 case BRW_OPCODE_RNDE
:
1865 brw_RNDE(p
, dst
, src
[0]);
1867 case BRW_OPCODE_RNDZ
:
1868 brw_RNDZ(p
, dst
, src
[0]);
1871 case BRW_OPCODE_AND
:
1872 brw_AND(p
, dst
, src
[0], src
[1]);
1875 brw_OR(p
, dst
, src
[0], src
[1]);
1877 case BRW_OPCODE_XOR
:
1878 brw_XOR(p
, dst
, src
[0], src
[1]);
1880 case BRW_OPCODE_NOT
:
1881 brw_NOT(p
, dst
, src
[0]);
1883 case BRW_OPCODE_ASR
:
1884 brw_ASR(p
, dst
, src
[0], src
[1]);
1886 case BRW_OPCODE_SHR
:
1887 brw_SHR(p
, dst
, src
[0], src
[1]);
1889 case BRW_OPCODE_SHL
:
1890 brw_SHL(p
, dst
, src
[0], src
[1]);
1892 case BRW_OPCODE_F32TO16
:
1893 assert(devinfo
->gen
>= 7);
1894 brw_F32TO16(p
, dst
, src
[0]);
1896 case BRW_OPCODE_F16TO32
:
1897 assert(devinfo
->gen
>= 7);
1898 brw_F16TO32(p
, dst
, src
[0]);
1900 case BRW_OPCODE_CMP
:
1901 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1902 * that when the destination is a GRF that the dependency-clear bit on
1903 * the flag register is cleared early.
1905 * Suggested workarounds are to disable coissuing CMP instructions
1906 * or to split CMP(16) instructions into two CMP(8) instructions.
1908 * We choose to split into CMP(8) instructions since disabling
1909 * coissuing would affect CMP instructions not otherwise affected by
1912 if (dispatch_width
== 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1913 if (dst
.file
== BRW_GENERAL_REGISTER_FILE
) {
1914 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1915 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1916 brw_CMP(p
, firsthalf(dst
), inst
->conditional_mod
,
1917 firsthalf(src
[0]), firsthalf(src
[1]));
1918 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1919 brw_CMP(p
, sechalf(dst
), inst
->conditional_mod
,
1920 sechalf(src
[0]), sechalf(src
[1]));
1921 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1923 multiple_instructions_emitted
= true;
1924 } else if (dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1925 /* For unknown reasons, the aforementioned workaround is not
1926 * sufficient. Overriding the type when the destination is the
1927 * null register is necessary but not sufficient by itself.
1929 assert(dst
.nr
== BRW_ARF_NULL
);
1930 dst
.type
= BRW_REGISTER_TYPE_D
;
1931 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1933 unreachable("not reached");
1936 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1939 case BRW_OPCODE_SEL
:
1940 brw_SEL(p
, dst
, src
[0], src
[1]);
1942 case BRW_OPCODE_BFREV
:
1943 assert(devinfo
->gen
>= 7);
1944 /* BFREV only supports UD type for src and dst. */
1945 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1946 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1948 case BRW_OPCODE_FBH
:
1949 assert(devinfo
->gen
>= 7);
1950 /* FBH only supports UD type for dst. */
1951 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1953 case BRW_OPCODE_FBL
:
1954 assert(devinfo
->gen
>= 7);
1955 /* FBL only supports UD type for dst. */
1956 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1958 case BRW_OPCODE_CBIT
:
1959 assert(devinfo
->gen
>= 7);
1960 /* CBIT only supports UD type for dst. */
1961 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1963 case BRW_OPCODE_ADDC
:
1964 assert(devinfo
->gen
>= 7);
1965 brw_ADDC(p
, dst
, src
[0], src
[1]);
1967 case BRW_OPCODE_SUBB
:
1968 assert(devinfo
->gen
>= 7);
1969 brw_SUBB(p
, dst
, src
[0], src
[1]);
1971 case BRW_OPCODE_MAC
:
1972 brw_MAC(p
, dst
, src
[0], src
[1]);
1975 case BRW_OPCODE_BFE
:
1976 assert(devinfo
->gen
>= 7);
1977 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1978 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1979 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1980 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1981 brw_BFE(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1982 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1983 brw_BFE(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1984 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1986 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1988 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1991 case BRW_OPCODE_BFI1
:
1992 assert(devinfo
->gen
>= 7);
1993 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1996 * "Force BFI instructions to be executed always in SIMD8."
1998 if (dispatch_width
== 16 && devinfo
->is_haswell
) {
1999 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
2000 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
2001 brw_BFI1(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]));
2002 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
2003 brw_BFI1(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]));
2004 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
2006 brw_BFI1(p
, dst
, src
[0], src
[1]);
2009 case BRW_OPCODE_BFI2
:
2010 assert(devinfo
->gen
>= 7);
2011 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2012 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
2015 * "Force BFI instructions to be executed always in SIMD8."
2017 * Otherwise we would be able to emit compressed instructions like we
2018 * do for the other three-source instructions.
2020 if (dispatch_width
== 16 &&
2021 (devinfo
->is_haswell
|| !devinfo
->supports_simd16_3src
)) {
2022 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
2023 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
2024 brw_BFI2(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
2025 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
2026 brw_BFI2(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
2027 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
2029 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
2031 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
2035 if (inst
->src
[0].file
!= BAD_FILE
) {
2036 /* The instruction has an embedded compare (only allowed on gen6) */
2037 assert(devinfo
->gen
== 6);
2038 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
2040 brw_IF(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
2044 case BRW_OPCODE_ELSE
:
2047 case BRW_OPCODE_ENDIF
:
2052 brw_DO(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
2055 case BRW_OPCODE_BREAK
:
2057 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
2059 case BRW_OPCODE_CONTINUE
:
2061 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
2064 case BRW_OPCODE_WHILE
:
2069 case SHADER_OPCODE_RCP
:
2070 case SHADER_OPCODE_RSQ
:
2071 case SHADER_OPCODE_SQRT
:
2072 case SHADER_OPCODE_EXP2
:
2073 case SHADER_OPCODE_LOG2
:
2074 case SHADER_OPCODE_SIN
:
2075 case SHADER_OPCODE_COS
:
2076 assert(devinfo
->gen
< 6 || inst
->mlen
== 0);
2077 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2078 if (devinfo
->gen
>= 7) {
2079 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
2081 } else if (devinfo
->gen
== 6) {
2082 generate_math_gen6(inst
, dst
, src
[0], brw_null_reg());
2083 } else if (devinfo
->gen
== 5 || devinfo
->is_g4x
) {
2084 generate_math_g45(inst
, dst
, src
[0]);
2086 generate_math_gen4(inst
, dst
, src
[0]);
2089 case SHADER_OPCODE_INT_QUOTIENT
:
2090 case SHADER_OPCODE_INT_REMAINDER
:
2091 case SHADER_OPCODE_POW
:
2092 assert(devinfo
->gen
< 6 || inst
->mlen
== 0);
2093 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2094 if (devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) {
2095 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
2096 } else if (devinfo
->gen
>= 6) {
2097 generate_math_gen6(inst
, dst
, src
[0], src
[1]);
2099 generate_math_gen4(inst
, dst
, src
[0]);
2102 case FS_OPCODE_CINTERP
:
2103 brw_MOV(p
, dst
, src
[0]);
2105 case FS_OPCODE_LINTERP
:
2106 generate_linterp(inst
, dst
, src
);
2108 case FS_OPCODE_PIXEL_X
:
2109 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2110 src
[0].subnr
= 0 * type_sz(src
[0].type
);
2111 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2113 case FS_OPCODE_PIXEL_Y
:
2114 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2115 src
[0].subnr
= 4 * type_sz(src
[0].type
);
2116 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2118 case FS_OPCODE_GET_BUFFER_SIZE
:
2119 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2121 case SHADER_OPCODE_TEX
:
2123 case SHADER_OPCODE_TXD
:
2124 case SHADER_OPCODE_TXF
:
2125 case SHADER_OPCODE_TXF_CMS
:
2126 case SHADER_OPCODE_TXF_CMS_W
:
2127 case SHADER_OPCODE_TXF_UMS
:
2128 case SHADER_OPCODE_TXF_MCS
:
2129 case SHADER_OPCODE_TXL
:
2130 case SHADER_OPCODE_TXS
:
2131 case SHADER_OPCODE_LOD
:
2132 case SHADER_OPCODE_TG4
:
2133 case SHADER_OPCODE_TG4_OFFSET
:
2134 case SHADER_OPCODE_SAMPLEINFO
:
2135 generate_tex(inst
, dst
, src
[0], src
[1], src
[2]);
2137 case FS_OPCODE_DDX_COARSE
:
2138 case FS_OPCODE_DDX_FINE
:
2139 generate_ddx(inst
->opcode
, dst
, src
[0]);
2141 case FS_OPCODE_DDY_COARSE
:
2142 case FS_OPCODE_DDY_FINE
:
2143 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2144 generate_ddy(inst
->opcode
, dst
, src
[0], src
[1].ud
);
2147 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2148 generate_scratch_write(inst
, src
[0]);
2152 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2153 generate_scratch_read(inst
, dst
);
2157 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2158 generate_scratch_read_gen7(inst
, dst
);
2162 case SHADER_OPCODE_MOV_INDIRECT
:
2163 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2166 case SHADER_OPCODE_URB_READ_SIMD8
:
2167 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2168 generate_urb_read(inst
, dst
, src
[0]);
2171 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2172 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2173 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2174 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2175 generate_urb_write(inst
, src
[0]);
2178 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2179 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2182 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2183 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2186 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
2187 generate_varying_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2190 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
2191 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2194 case FS_OPCODE_REP_FB_WRITE
:
2195 case FS_OPCODE_FB_WRITE
:
2196 generate_fb_write(inst
, src
[0]);
2199 case FS_OPCODE_BLORP_FB_WRITE
:
2200 generate_blorp_fb_write(inst
, src
[0]);
2203 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
2204 generate_mov_dispatch_to_flags(inst
);
2207 case FS_OPCODE_DISCARD_JUMP
:
2208 generate_discard_jump(inst
);
2211 case SHADER_OPCODE_SHADER_TIME_ADD
:
2212 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2215 case SHADER_OPCODE_UNTYPED_ATOMIC
:
2216 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2217 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
,
2218 inst
->mlen
, !inst
->dst
.is_null());
2221 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
2222 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2223 brw_untyped_surface_read(p
, dst
, src
[0], src
[1],
2224 inst
->mlen
, src
[2].ud
);
2227 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
2228 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2229 brw_untyped_surface_write(p
, src
[0], src
[1],
2230 inst
->mlen
, src
[2].ud
);
2233 case SHADER_OPCODE_TYPED_ATOMIC
:
2234 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2235 brw_typed_atomic(p
, dst
, src
[0], src
[1],
2236 src
[2].ud
, inst
->mlen
, !inst
->dst
.is_null());
2239 case SHADER_OPCODE_TYPED_SURFACE_READ
:
2240 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2241 brw_typed_surface_read(p
, dst
, src
[0], src
[1],
2242 inst
->mlen
, src
[2].ud
);
2245 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
2246 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2247 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
, src
[2].ud
);
2250 case SHADER_OPCODE_MEMORY_FENCE
:
2251 brw_memory_fence(p
, dst
);
2254 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
2255 generate_set_simd4x2_offset(inst
, dst
, src
[0]);
2258 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2259 brw_find_live_channel(p
, dst
);
2262 case SHADER_OPCODE_BROADCAST
:
2263 brw_broadcast(p
, dst
, src
[0], src
[1]);
2266 case SHADER_OPCODE_EXTRACT_BYTE
: {
2267 assert(src
[0].type
== BRW_REGISTER_TYPE_D
||
2268 src
[0].type
== BRW_REGISTER_TYPE_UD
);
2270 enum brw_reg_type type
=
2271 src
[0].type
== BRW_REGISTER_TYPE_D
? BRW_REGISTER_TYPE_B
2272 : BRW_REGISTER_TYPE_UB
;
2273 brw_MOV(p
, dst
, spread(suboffset(retype(src
[0], type
), src
[1].ud
), 4));
2277 case SHADER_OPCODE_EXTRACT_WORD
: {
2278 assert(src
[0].type
== BRW_REGISTER_TYPE_D
||
2279 src
[0].type
== BRW_REGISTER_TYPE_UD
);
2281 enum brw_reg_type type
=
2282 src
[0].type
== BRW_REGISTER_TYPE_D
? BRW_REGISTER_TYPE_W
2283 : BRW_REGISTER_TYPE_UW
;
2284 brw_MOV(p
, dst
, spread(suboffset(retype(src
[0], type
), src
[1].ud
), 2));
2288 case FS_OPCODE_SET_SAMPLE_ID
:
2289 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2292 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2293 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2296 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
2297 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
2298 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
2301 case FS_OPCODE_PLACEHOLDER_HALT
:
2302 /* This is the place where the final HALT needs to be inserted if
2303 * we've emitted any discards. If not, this will emit no code.
2305 if (!patch_discard_jumps_to_fb_writes()) {
2306 if (unlikely(debug_flag
)) {
2307 annotation
.ann_count
--;
2312 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
2313 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2314 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID
);
2317 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2318 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2319 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2322 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2323 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2324 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2327 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2328 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2329 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2332 case CS_OPCODE_CS_TERMINATE
:
2333 generate_cs_terminate(inst
, src
[0]);
2336 case SHADER_OPCODE_BARRIER
:
2337 generate_barrier(inst
, src
[0]);
2340 case FS_OPCODE_PACK_STENCIL_REF
:
2341 generate_stencil_ref_packing(inst
, dst
, src
[0]);
2345 unreachable("Unsupported opcode");
2347 case SHADER_OPCODE_LOAD_PAYLOAD
:
2348 unreachable("Should be lowered by lower_load_payload()");
2351 if (multiple_instructions_emitted
)
2354 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2355 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2356 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2357 "emitting more than 1 instruction");
2359 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2361 if (inst
->conditional_mod
)
2362 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2363 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2364 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2369 annotation_finalize(&annotation
, p
->next_insn_offset
);
2372 bool validated
= brw_validate_instructions(p
, start_offset
, &annotation
);
2374 if (unlikely(debug_flag
))
2375 brw_validate_instructions(p
, start_offset
, &annotation
);
2378 int before_size
= p
->next_insn_offset
- start_offset
;
2379 brw_compact_instructions(p
, start_offset
, annotation
.ann_count
,
2381 int after_size
= p
->next_insn_offset
- start_offset
;
2383 if (unlikely(debug_flag
)) {
2384 fprintf(stderr
, "Native code for %s\n"
2385 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2386 " bytes (%.0f%%)\n",
2387 shader_name
, dispatch_width
, before_size
/ 16, loop_count
, cfg
->cycle_count
,
2388 spill_count
, fill_count
, promoted_constants
, before_size
, after_size
,
2389 100.0f
* (before_size
- after_size
) / before_size
);
2391 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
,
2393 ralloc_free(annotation
.mem_ctx
);
2397 compiler
->shader_debug_log(log_data
,
2398 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2399 "%d:%d spills:fills, Promoted %u constants, "
2400 "compacted %d to %d bytes.",
2401 _mesa_shader_stage_to_abbrev(stage
),
2402 dispatch_width
, before_size
/ 16,
2403 loop_count
, cfg
->cycle_count
, spill_count
,
2404 fill_count
, promoted_constants
, before_size
,
2407 return start_offset
;
2411 fs_generator::get_assembly(unsigned int *assembly_size
)
2413 return brw_get_program(p
, assembly_size
);