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i965/cfg: Clean up cfg_t constructors.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 fs_generator::fs_generator(struct brw_context *brw,
40 struct brw_wm_compile *c,
41 struct gl_shader_program *prog,
42 struct gl_fragment_program *fp,
43 bool dual_source_output)
44
45 : brw(brw), c(c), prog(prog), fp(fp), dual_source_output(dual_source_output)
46 {
47 ctx = &brw->ctx;
48
49 shader = prog ? prog->_LinkedShaders[MESA_SHADER_FRAGMENT] : NULL;
50
51 mem_ctx = c;
52
53 p = rzalloc(mem_ctx, struct brw_compile);
54 brw_init_compile(brw, p, mem_ctx);
55 }
56
57 fs_generator::~fs_generator()
58 {
59 }
60
61 void
62 fs_generator::mark_surface_used(unsigned surf_index)
63 {
64 assert(surf_index < BRW_MAX_SURFACES);
65
66 c->prog_data.base.binding_table.size_bytes =
67 MAX2(c->prog_data.base.binding_table.size_bytes, (surf_index + 1) * 4);
68 }
69
70 void
71 fs_generator::patch_discard_jumps_to_fb_writes()
72 {
73 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
74 return;
75
76 /* There is a somewhat strange undocumented requirement of using
77 * HALT, according to the simulator. If some channel has HALTed to
78 * a particular UIP, then by the end of the program, every channel
79 * must have HALTed to that UIP. Furthermore, the tracking is a
80 * stack, so you can't do the final halt of a UIP after starting
81 * halting to a new UIP.
82 *
83 * Symptoms of not emitting this instruction on actual hardware
84 * included GPU hangs and sparkly rendering on the piglit discard
85 * tests.
86 */
87 struct brw_instruction *last_halt = gen6_HALT(p);
88 last_halt->bits3.break_cont.uip = 2;
89 last_halt->bits3.break_cont.jip = 2;
90
91 int ip = p->nr_insn;
92
93 foreach_list(node, &this->discard_halt_patches) {
94 ip_record *patch_ip = (ip_record *)node;
95 struct brw_instruction *patch = &p->store[patch_ip->ip];
96
97 assert(patch->header.opcode == BRW_OPCODE_HALT);
98 /* HALT takes a half-instruction distance from the pre-incremented IP. */
99 patch->bits3.break_cont.uip = (ip - patch_ip->ip) * 2;
100 }
101
102 this->discard_halt_patches.make_empty();
103 }
104
105 void
106 fs_generator::generate_fb_write(fs_inst *inst)
107 {
108 bool eot = inst->eot;
109 struct brw_reg implied_header;
110 uint32_t msg_control;
111
112 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
113 * move, here's g1.
114 */
115 brw_push_insn_state(p);
116 brw_set_mask_control(p, BRW_MASK_DISABLE);
117 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
118
119 if (fp->UsesKill || c->key.alpha_test_func) {
120 struct brw_reg pixel_mask;
121
122 if (brw->gen >= 6)
123 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
124 else
125 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
126
127 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
128 }
129
130 if (inst->header_present) {
131 if (brw->gen >= 6) {
132 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
133 brw_MOV(p,
134 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
135 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
136 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
137
138 if (inst->target > 0 && c->key.replicate_alpha) {
139 /* Set "Source0 Alpha Present to RenderTarget" bit in message
140 * header.
141 */
142 brw_OR(p,
143 vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)),
144 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
145 brw_imm_ud(0x1 << 11));
146 }
147
148 if (inst->target > 0) {
149 /* Set the render target index for choosing BLEND_STATE. */
150 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
151 inst->base_mrf, 2),
152 BRW_REGISTER_TYPE_UD),
153 brw_imm_ud(inst->target));
154 }
155
156 implied_header = brw_null_reg();
157 } else {
158 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
159
160 brw_MOV(p,
161 brw_message_reg(inst->base_mrf + 1),
162 brw_vec8_grf(1, 0));
163 }
164 } else {
165 implied_header = brw_null_reg();
166 }
167
168 if (this->dual_source_output)
169 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
170 else if (dispatch_width == 16)
171 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
172 else
173 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
174
175 brw_pop_insn_state(p);
176
177 uint32_t surf_index =
178 c->prog_data.binding_table.render_target_start + inst->target;
179 brw_fb_WRITE(p,
180 dispatch_width,
181 inst->base_mrf,
182 implied_header,
183 msg_control,
184 surf_index,
185 inst->mlen,
186 0,
187 eot,
188 inst->header_present);
189
190 mark_surface_used(surf_index);
191 }
192
193 /* Computes the integer pixel x,y values from the origin.
194 *
195 * This is the basis of gl_FragCoord computation, but is also used
196 * pre-gen6 for computing the deltas from v0 for computing
197 * interpolation.
198 */
199 void
200 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
201 {
202 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
203 struct brw_reg src;
204 struct brw_reg deltas;
205
206 if (is_x) {
207 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
208 deltas = brw_imm_v(0x10101010);
209 } else {
210 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
211 deltas = brw_imm_v(0x11001100);
212 }
213
214 if (dispatch_width == 16) {
215 dst = vec16(dst);
216 }
217
218 /* We do this 8 or 16-wide, but since the destination is UW we
219 * don't do compression in the 16-wide case.
220 */
221 brw_push_insn_state(p);
222 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
223 brw_ADD(p, dst, src, deltas);
224 brw_pop_insn_state(p);
225 }
226
227 void
228 fs_generator::generate_linterp(fs_inst *inst,
229 struct brw_reg dst, struct brw_reg *src)
230 {
231 struct brw_reg delta_x = src[0];
232 struct brw_reg delta_y = src[1];
233 struct brw_reg interp = src[2];
234
235 if (brw->has_pln &&
236 delta_y.nr == delta_x.nr + 1 &&
237 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
238 brw_PLN(p, dst, interp, delta_x);
239 } else {
240 brw_LINE(p, brw_null_reg(), interp, delta_x);
241 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
242 }
243 }
244
245 void
246 fs_generator::generate_math1_gen7(fs_inst *inst,
247 struct brw_reg dst,
248 struct brw_reg src0)
249 {
250 assert(inst->mlen == 0);
251 brw_math(p, dst,
252 brw_math_function(inst->opcode),
253 0, src0,
254 BRW_MATH_DATA_VECTOR,
255 BRW_MATH_PRECISION_FULL);
256 }
257
258 void
259 fs_generator::generate_math2_gen7(fs_inst *inst,
260 struct brw_reg dst,
261 struct brw_reg src0,
262 struct brw_reg src1)
263 {
264 assert(inst->mlen == 0);
265 brw_math2(p, dst, brw_math_function(inst->opcode), src0, src1);
266 }
267
268 void
269 fs_generator::generate_math1_gen6(fs_inst *inst,
270 struct brw_reg dst,
271 struct brw_reg src0)
272 {
273 int op = brw_math_function(inst->opcode);
274
275 assert(inst->mlen == 0);
276
277 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
278 brw_math(p, dst,
279 op,
280 0, src0,
281 BRW_MATH_DATA_VECTOR,
282 BRW_MATH_PRECISION_FULL);
283
284 if (dispatch_width == 16) {
285 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
286 brw_math(p, sechalf(dst),
287 op,
288 0, sechalf(src0),
289 BRW_MATH_DATA_VECTOR,
290 BRW_MATH_PRECISION_FULL);
291 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
292 }
293 }
294
295 void
296 fs_generator::generate_math2_gen6(fs_inst *inst,
297 struct brw_reg dst,
298 struct brw_reg src0,
299 struct brw_reg src1)
300 {
301 int op = brw_math_function(inst->opcode);
302
303 assert(inst->mlen == 0);
304
305 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
306 brw_math2(p, dst, op, src0, src1);
307
308 if (dispatch_width == 16) {
309 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
310 brw_math2(p, sechalf(dst), op, sechalf(src0), sechalf(src1));
311 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
312 }
313 }
314
315 void
316 fs_generator::generate_math_gen4(fs_inst *inst,
317 struct brw_reg dst,
318 struct brw_reg src)
319 {
320 int op = brw_math_function(inst->opcode);
321
322 assert(inst->mlen >= 1);
323
324 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
325 brw_math(p, dst,
326 op,
327 inst->base_mrf, src,
328 BRW_MATH_DATA_VECTOR,
329 BRW_MATH_PRECISION_FULL);
330
331 if (dispatch_width == 16) {
332 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
333 brw_math(p, sechalf(dst),
334 op,
335 inst->base_mrf + 1, sechalf(src),
336 BRW_MATH_DATA_VECTOR,
337 BRW_MATH_PRECISION_FULL);
338
339 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
340 }
341 }
342
343 void
344 fs_generator::generate_math_g45(fs_inst *inst,
345 struct brw_reg dst,
346 struct brw_reg src)
347 {
348 if (inst->opcode == SHADER_OPCODE_POW ||
349 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
350 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
351 generate_math_gen4(inst, dst, src);
352 return;
353 }
354
355 int op = brw_math_function(inst->opcode);
356
357 assert(inst->mlen >= 1);
358
359 brw_math(p, dst,
360 op,
361 inst->base_mrf, src,
362 BRW_MATH_DATA_VECTOR,
363 BRW_MATH_PRECISION_FULL);
364 }
365
366 void
367 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
368 {
369 int msg_type = -1;
370 int rlen = 4;
371 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
372 uint32_t return_format;
373
374 switch (dst.type) {
375 case BRW_REGISTER_TYPE_D:
376 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
377 break;
378 case BRW_REGISTER_TYPE_UD:
379 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
380 break;
381 default:
382 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
383 break;
384 }
385
386 if (dispatch_width == 16 &&
387 !inst->force_uncompressed && !inst->force_sechalf)
388 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
389
390 if (brw->gen >= 5) {
391 switch (inst->opcode) {
392 case SHADER_OPCODE_TEX:
393 if (inst->shadow_compare) {
394 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
395 } else {
396 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
397 }
398 break;
399 case FS_OPCODE_TXB:
400 if (inst->shadow_compare) {
401 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
402 } else {
403 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
404 }
405 break;
406 case SHADER_OPCODE_TXL:
407 if (inst->shadow_compare) {
408 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
409 } else {
410 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
411 }
412 break;
413 case SHADER_OPCODE_TXS:
414 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
415 break;
416 case SHADER_OPCODE_TXD:
417 if (inst->shadow_compare) {
418 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
419 assert(brw->is_haswell);
420 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
421 } else {
422 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
423 }
424 break;
425 case SHADER_OPCODE_TXF:
426 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
427 break;
428 case SHADER_OPCODE_TXF_MS:
429 if (brw->gen >= 7)
430 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
431 else
432 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
433 break;
434 case SHADER_OPCODE_LOD:
435 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
436 break;
437 case SHADER_OPCODE_TG4:
438 if (inst->shadow_compare) {
439 assert(brw->gen >= 7);
440 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
441 } else {
442 assert(brw->gen >= 6);
443 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
444 }
445 break;
446 case SHADER_OPCODE_TG4_OFFSET:
447 assert(brw->gen >= 7);
448 if (inst->shadow_compare) {
449 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
450 } else {
451 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
452 }
453 break;
454 default:
455 assert(!"not reached");
456 break;
457 }
458 } else {
459 switch (inst->opcode) {
460 case SHADER_OPCODE_TEX:
461 /* Note that G45 and older determines shadow compare and dispatch width
462 * from message length for most messages.
463 */
464 assert(dispatch_width == 8);
465 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
466 if (inst->shadow_compare) {
467 assert(inst->mlen == 6);
468 } else {
469 assert(inst->mlen <= 4);
470 }
471 break;
472 case FS_OPCODE_TXB:
473 if (inst->shadow_compare) {
474 assert(inst->mlen == 6);
475 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
476 } else {
477 assert(inst->mlen == 9);
478 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
479 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
480 }
481 break;
482 case SHADER_OPCODE_TXL:
483 if (inst->shadow_compare) {
484 assert(inst->mlen == 6);
485 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
486 } else {
487 assert(inst->mlen == 9);
488 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
489 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
490 }
491 break;
492 case SHADER_OPCODE_TXD:
493 /* There is no sample_d_c message; comparisons are done manually */
494 assert(inst->mlen == 7 || inst->mlen == 10);
495 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
496 break;
497 case SHADER_OPCODE_TXF:
498 assert(inst->mlen == 9);
499 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
500 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
501 break;
502 case SHADER_OPCODE_TXS:
503 assert(inst->mlen == 3);
504 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
505 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
506 break;
507 default:
508 assert(!"not reached");
509 break;
510 }
511 }
512 assert(msg_type != -1);
513
514 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
515 rlen = 8;
516 dst = vec16(dst);
517 }
518
519 if (brw->gen >= 7 && inst->header_present && dispatch_width == 16) {
520 /* The send-from-GRF for 16-wide texturing with a header has an extra
521 * hardware register allocated to it, which we need to skip over (since
522 * our coordinates in the payload are in the even-numbered registers,
523 * and the header comes right before the first one).
524 */
525 assert(src.file == BRW_GENERAL_REGISTER_FILE);
526 src.nr++;
527 }
528
529 /* Load the message header if present. If there's a texture offset,
530 * we need to set it up explicitly and load the offset bitfield.
531 * Otherwise, we can use an implied move from g0 to the first message reg.
532 */
533 if (inst->texture_offset) {
534 struct brw_reg header_reg;
535
536 if (brw->gen >= 7) {
537 header_reg = src;
538 } else {
539 assert(inst->base_mrf != -1);
540 header_reg = brw_message_reg(inst->base_mrf);
541 }
542 brw_push_insn_state(p);
543 brw_set_mask_control(p, BRW_MASK_DISABLE);
544 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
545 /* Explicitly set up the message header by copying g0 to the MRF. */
546 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
547
548 /* Then set the offset bits in DWord 2. */
549 brw_MOV(p, retype(brw_vec1_reg(header_reg.file,
550 header_reg.nr, 2), BRW_REGISTER_TYPE_UD),
551 brw_imm_ud(inst->texture_offset));
552 brw_pop_insn_state(p);
553 } else if (inst->header_present) {
554 if (brw->gen >= 7) {
555 /* Explicitly set up the message header by copying g0 to the MRF. */
556 brw_push_insn_state(p);
557 brw_set_mask_control(p, BRW_MASK_DISABLE);
558 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
559 brw_MOV(p, src, brw_vec8_grf(0, 0));
560 brw_pop_insn_state(p);
561 } else {
562 /* Set up an implied move from g0 to the MRF. */
563 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
564 }
565 }
566
567 uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
568 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
569 ? c->prog_data.base.binding_table.gather_texture_start
570 : c->prog_data.base.binding_table.texture_start) + inst->sampler;
571
572 brw_SAMPLE(p,
573 retype(dst, BRW_REGISTER_TYPE_UW),
574 inst->base_mrf,
575 src,
576 surface_index,
577 inst->sampler,
578 msg_type,
579 rlen,
580 inst->mlen,
581 inst->header_present,
582 simd_mode,
583 return_format);
584
585 mark_surface_used(surface_index);
586 }
587
588
589 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
590 * looking like:
591 *
592 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
593 *
594 * Ideally, we want to produce:
595 *
596 * DDX DDY
597 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
598 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
599 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
600 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
601 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
602 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
603 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
604 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
605 *
606 * and add another set of two more subspans if in 16-pixel dispatch mode.
607 *
608 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
609 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
610 * pair. But the ideal approximation may impose a huge performance cost on
611 * sample_d. On at least Haswell, sample_d instruction does some
612 * optimizations if the same LOD is used for all pixels in the subspan.
613 *
614 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
615 * appropriate swizzling.
616 */
617 void
618 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
619 {
620 unsigned vstride, width;
621
622 if (c->key.high_quality_derivatives) {
623 /* produce accurate derivatives */
624 vstride = BRW_VERTICAL_STRIDE_2;
625 width = BRW_WIDTH_2;
626 }
627 else {
628 /* replicate the derivative at the top-left pixel to other pixels */
629 vstride = BRW_VERTICAL_STRIDE_4;
630 width = BRW_WIDTH_4;
631 }
632
633 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
634 BRW_REGISTER_TYPE_F,
635 vstride,
636 width,
637 BRW_HORIZONTAL_STRIDE_0,
638 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
639 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
640 BRW_REGISTER_TYPE_F,
641 vstride,
642 width,
643 BRW_HORIZONTAL_STRIDE_0,
644 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
645 brw_ADD(p, dst, src0, negate(src1));
646 }
647
648 /* The negate_value boolean is used to negate the derivative computation for
649 * FBOs, since they place the origin at the upper left instead of the lower
650 * left.
651 */
652 void
653 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
654 bool negate_value)
655 {
656 if (c->key.high_quality_derivatives) {
657 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
658 * Region Restrictions):
659 *
660 * In Align16 access mode, SIMD16 is not allowed for DW operations
661 * and SIMD8 is not allowed for DF operations.
662 *
663 * In this context, "DW operations" means "operations acting on 32-bit
664 * values", so it includes operations on floats.
665 *
666 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
667 * (Instruction Compression -> Rules and Restrictions):
668 *
669 * A compressed instruction must be in Align1 access mode. Align16
670 * mode instructions cannot be compressed.
671 *
672 * Similar text exists in the g45 PRM.
673 *
674 * On these platforms, if we're building a SIMD16 shader, we need to
675 * manually unroll to a pair of SIMD8 instructions.
676 */
677 bool unroll_to_simd8 =
678 (dispatch_width == 16 &&
679 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
680
681 /* produce accurate derivatives */
682 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
683 BRW_REGISTER_TYPE_F,
684 BRW_VERTICAL_STRIDE_4,
685 BRW_WIDTH_4,
686 BRW_HORIZONTAL_STRIDE_1,
687 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
688 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
689 BRW_REGISTER_TYPE_F,
690 BRW_VERTICAL_STRIDE_4,
691 BRW_WIDTH_4,
692 BRW_HORIZONTAL_STRIDE_1,
693 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
694 brw_push_insn_state(p);
695 brw_set_access_mode(p, BRW_ALIGN_16);
696 if (unroll_to_simd8)
697 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
698 if (negate_value)
699 brw_ADD(p, dst, src1, negate(src0));
700 else
701 brw_ADD(p, dst, src0, negate(src1));
702 if (unroll_to_simd8) {
703 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
704 src0 = sechalf(src0);
705 src1 = sechalf(src1);
706 dst = sechalf(dst);
707 if (negate_value)
708 brw_ADD(p, dst, src1, negate(src0));
709 else
710 brw_ADD(p, dst, src0, negate(src1));
711 }
712 brw_pop_insn_state(p);
713 } else {
714 /* replicate the derivative at the top-left pixel to other pixels */
715 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
716 BRW_REGISTER_TYPE_F,
717 BRW_VERTICAL_STRIDE_4,
718 BRW_WIDTH_4,
719 BRW_HORIZONTAL_STRIDE_0,
720 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
721 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
722 BRW_REGISTER_TYPE_F,
723 BRW_VERTICAL_STRIDE_4,
724 BRW_WIDTH_4,
725 BRW_HORIZONTAL_STRIDE_0,
726 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
727 if (negate_value)
728 brw_ADD(p, dst, src1, negate(src0));
729 else
730 brw_ADD(p, dst, src0, negate(src1));
731 }
732 }
733
734 void
735 fs_generator::generate_discard_jump(fs_inst *inst)
736 {
737 assert(brw->gen >= 6);
738
739 /* This HALT will be patched up at FB write time to point UIP at the end of
740 * the program, and at brw_uip_jip() JIP will be set to the end of the
741 * current block (or the program).
742 */
743 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
744
745 brw_push_insn_state(p);
746 brw_set_mask_control(p, BRW_MASK_DISABLE);
747 gen6_HALT(p);
748 brw_pop_insn_state(p);
749 }
750
751 void
752 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
753 {
754 assert(inst->mlen != 0);
755
756 brw_MOV(p,
757 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
758 retype(src, BRW_REGISTER_TYPE_UD));
759 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
760 dispatch_width / 8, inst->offset);
761 }
762
763 void
764 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
765 {
766 assert(inst->mlen != 0);
767
768 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
769 dispatch_width / 8, inst->offset);
770 }
771
772 void
773 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
774 {
775 gen7_block_read_scratch(p, dst, dispatch_width / 8, inst->offset);
776 }
777
778 void
779 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
780 struct brw_reg dst,
781 struct brw_reg index,
782 struct brw_reg offset)
783 {
784 assert(inst->mlen != 0);
785
786 assert(index.file == BRW_IMMEDIATE_VALUE &&
787 index.type == BRW_REGISTER_TYPE_UD);
788 uint32_t surf_index = index.dw1.ud;
789
790 assert(offset.file == BRW_IMMEDIATE_VALUE &&
791 offset.type == BRW_REGISTER_TYPE_UD);
792 uint32_t read_offset = offset.dw1.ud;
793
794 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
795 read_offset, surf_index);
796
797 mark_surface_used(surf_index);
798 }
799
800 void
801 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
802 struct brw_reg dst,
803 struct brw_reg index,
804 struct brw_reg offset)
805 {
806 assert(inst->mlen == 0);
807
808 assert(index.file == BRW_IMMEDIATE_VALUE &&
809 index.type == BRW_REGISTER_TYPE_UD);
810 uint32_t surf_index = index.dw1.ud;
811
812 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
813 /* Reference just the dword we need, to avoid angering validate_reg(). */
814 offset = brw_vec1_grf(offset.nr, 0);
815
816 brw_push_insn_state(p);
817 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
818 brw_set_mask_control(p, BRW_MASK_DISABLE);
819 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
820 brw_pop_insn_state(p);
821
822 /* We use the SIMD4x2 mode because we want to end up with 4 components in
823 * the destination loaded consecutively from the same offset (which appears
824 * in the first component, and the rest are ignored).
825 */
826 dst.width = BRW_WIDTH_4;
827 brw_set_dest(p, send, dst);
828 brw_set_src0(p, send, offset);
829 brw_set_sampler_message(p, send,
830 surf_index,
831 0, /* LD message ignores sampler unit */
832 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
833 1, /* rlen */
834 1, /* mlen */
835 false, /* no header */
836 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
837 0);
838
839 mark_surface_used(surf_index);
840 }
841
842 void
843 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
844 struct brw_reg dst,
845 struct brw_reg index,
846 struct brw_reg offset)
847 {
848 assert(brw->gen < 7); /* Should use the gen7 variant. */
849 assert(inst->header_present);
850 assert(inst->mlen);
851
852 assert(index.file == BRW_IMMEDIATE_VALUE &&
853 index.type == BRW_REGISTER_TYPE_UD);
854 uint32_t surf_index = index.dw1.ud;
855
856 uint32_t simd_mode, rlen, msg_type;
857 if (dispatch_width == 16) {
858 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
859 rlen = 8;
860 } else {
861 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
862 rlen = 4;
863 }
864
865 if (brw->gen >= 5)
866 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
867 else {
868 /* We always use the SIMD16 message so that we only have to load U, and
869 * not V or R.
870 */
871 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
872 assert(inst->mlen == 3);
873 assert(inst->regs_written == 8);
874 rlen = 8;
875 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
876 }
877
878 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
879 BRW_REGISTER_TYPE_D);
880 brw_MOV(p, offset_mrf, offset);
881
882 struct brw_reg header = brw_vec8_grf(0, 0);
883 gen6_resolve_implied_move(p, &header, inst->base_mrf);
884
885 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
886 send->header.compression_control = BRW_COMPRESSION_NONE;
887 brw_set_dest(p, send, dst);
888 brw_set_src0(p, send, header);
889 if (brw->gen < 6)
890 send->header.destreg__conditionalmod = inst->base_mrf;
891
892 /* Our surface is set up as floats, regardless of what actual data is
893 * stored in it.
894 */
895 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
896 brw_set_sampler_message(p, send,
897 surf_index,
898 0, /* sampler (unused) */
899 msg_type,
900 rlen,
901 inst->mlen,
902 inst->header_present,
903 simd_mode,
904 return_format);
905
906 mark_surface_used(surf_index);
907 }
908
909 void
910 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
911 struct brw_reg dst,
912 struct brw_reg index,
913 struct brw_reg offset)
914 {
915 assert(brw->gen >= 7);
916 /* Varying-offset pull constant loads are treated as a normal expression on
917 * gen7, so the fact that it's a send message is hidden at the IR level.
918 */
919 assert(!inst->header_present);
920 assert(!inst->mlen);
921
922 assert(index.file == BRW_IMMEDIATE_VALUE &&
923 index.type == BRW_REGISTER_TYPE_UD);
924 uint32_t surf_index = index.dw1.ud;
925
926 uint32_t simd_mode, rlen, mlen;
927 if (dispatch_width == 16) {
928 mlen = 2;
929 rlen = 8;
930 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
931 } else {
932 mlen = 1;
933 rlen = 4;
934 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
935 }
936
937 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
938 brw_set_dest(p, send, dst);
939 brw_set_src0(p, send, offset);
940 brw_set_sampler_message(p, send,
941 surf_index,
942 0, /* LD message ignores sampler unit */
943 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
944 rlen,
945 mlen,
946 false, /* no header */
947 simd_mode,
948 0);
949
950 mark_surface_used(surf_index);
951 }
952
953 /**
954 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
955 * into the flags register (f0.0).
956 *
957 * Used only on Gen6 and above.
958 */
959 void
960 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
961 {
962 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
963 struct brw_reg dispatch_mask;
964
965 if (brw->gen >= 6)
966 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
967 else
968 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
969
970 brw_push_insn_state(p);
971 brw_set_mask_control(p, BRW_MASK_DISABLE);
972 brw_MOV(p, flags, dispatch_mask);
973 brw_pop_insn_state(p);
974 }
975
976
977 static uint32_t brw_file_from_reg(fs_reg *reg)
978 {
979 switch (reg->file) {
980 case GRF:
981 return BRW_GENERAL_REGISTER_FILE;
982 case MRF:
983 return BRW_MESSAGE_REGISTER_FILE;
984 case IMM:
985 return BRW_IMMEDIATE_VALUE;
986 default:
987 assert(!"not reached");
988 return BRW_GENERAL_REGISTER_FILE;
989 }
990 }
991
992 struct brw_reg
993 brw_reg_from_fs_reg(fs_reg *reg)
994 {
995 struct brw_reg brw_reg;
996
997 switch (reg->file) {
998 case GRF:
999 case MRF:
1000 if (reg->smear == -1) {
1001 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1002 } else {
1003 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, reg->smear);
1004 }
1005 brw_reg = retype(brw_reg, reg->type);
1006 if (reg->sechalf)
1007 brw_reg = sechalf(brw_reg);
1008 break;
1009 case IMM:
1010 switch (reg->type) {
1011 case BRW_REGISTER_TYPE_F:
1012 brw_reg = brw_imm_f(reg->imm.f);
1013 break;
1014 case BRW_REGISTER_TYPE_D:
1015 brw_reg = brw_imm_d(reg->imm.i);
1016 break;
1017 case BRW_REGISTER_TYPE_UD:
1018 brw_reg = brw_imm_ud(reg->imm.u);
1019 break;
1020 default:
1021 assert(!"not reached");
1022 brw_reg = brw_null_reg();
1023 break;
1024 }
1025 break;
1026 case HW_REG:
1027 brw_reg = reg->fixed_hw_reg;
1028 break;
1029 case BAD_FILE:
1030 /* Probably unused. */
1031 brw_reg = brw_null_reg();
1032 break;
1033 case UNIFORM:
1034 assert(!"not reached");
1035 brw_reg = brw_null_reg();
1036 break;
1037 default:
1038 assert(!"not reached");
1039 brw_reg = brw_null_reg();
1040 break;
1041 }
1042 if (reg->abs)
1043 brw_reg = brw_abs(brw_reg);
1044 if (reg->negate)
1045 brw_reg = negate(brw_reg);
1046
1047 return brw_reg;
1048 }
1049
1050 /**
1051 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1052 * sampler LD messages.
1053 *
1054 * We don't want to bake it into the send message's code generation because
1055 * that means we don't get a chance to schedule the instructions.
1056 */
1057 void
1058 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1059 struct brw_reg dst,
1060 struct brw_reg value)
1061 {
1062 assert(value.file == BRW_IMMEDIATE_VALUE);
1063
1064 brw_push_insn_state(p);
1065 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1066 brw_set_mask_control(p, BRW_MASK_DISABLE);
1067 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1068 brw_pop_insn_state(p);
1069 }
1070
1071 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1072 * (when mask is passed as a uniform) of register mask before moving it
1073 * to register dst.
1074 */
1075 void
1076 fs_generator::generate_set_omask(fs_inst *inst,
1077 struct brw_reg dst,
1078 struct brw_reg mask)
1079 {
1080 bool stride_8_8_1 =
1081 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1082 mask.width == BRW_WIDTH_8 &&
1083 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1084
1085 bool stride_0_1_0 =
1086 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1087 mask.width == BRW_WIDTH_1 &&
1088 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1089
1090 assert(stride_8_8_1 || stride_0_1_0);
1091 assert(dst.type == BRW_REGISTER_TYPE_UW);
1092
1093 if (dispatch_width == 16)
1094 dst = vec16(dst);
1095 brw_push_insn_state(p);
1096 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1097 brw_set_mask_control(p, BRW_MASK_DISABLE);
1098
1099 if (stride_8_8_1) {
1100 brw_MOV(p, dst, stride(retype(brw_vec1_reg(mask.file, mask.nr, 0),
1101 dst.type), 16, 8, 2));
1102 } else if (stride_0_1_0) {
1103 brw_MOV(p, dst, stride(retype(brw_vec1_reg(mask.file, mask.nr, 0),
1104 dst.type), 0, 1, 0));
1105 }
1106 brw_pop_insn_state(p);
1107 }
1108
1109 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1110 * the ADD instruction.
1111 */
1112 void
1113 fs_generator::generate_set_sample_id(fs_inst *inst,
1114 struct brw_reg dst,
1115 struct brw_reg src0,
1116 struct brw_reg src1)
1117 {
1118 assert(dst.type == BRW_REGISTER_TYPE_D ||
1119 dst.type == BRW_REGISTER_TYPE_UD);
1120 assert(src0.type == BRW_REGISTER_TYPE_D ||
1121 src0.type == BRW_REGISTER_TYPE_UD);
1122
1123 brw_push_insn_state(p);
1124 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1125 brw_set_mask_control(p, BRW_MASK_DISABLE);
1126 struct brw_reg reg = stride(retype(brw_vec1_reg(src1.file, src1.nr, 0),
1127 BRW_REGISTER_TYPE_UW), 1, 4, 0);
1128 brw_ADD(p, dst, src0, reg);
1129 if (dispatch_width == 16)
1130 brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
1131 brw_pop_insn_state(p);
1132 }
1133
1134 /**
1135 * Change the register's data type from UD to W, doubling the strides in order
1136 * to compensate for halving the data type width.
1137 */
1138 static struct brw_reg
1139 ud_reg_to_w(struct brw_reg r)
1140 {
1141 assert(r.type == BRW_REGISTER_TYPE_UD);
1142 r.type = BRW_REGISTER_TYPE_W;
1143
1144 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1145 * doubles the real stride.
1146 */
1147 if (r.hstride != 0)
1148 ++r.hstride;
1149 if (r.vstride != 0)
1150 ++r.vstride;
1151
1152 return r;
1153 }
1154
1155 void
1156 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1157 struct brw_reg dst,
1158 struct brw_reg x,
1159 struct brw_reg y)
1160 {
1161 assert(brw->gen >= 7);
1162 assert(dst.type == BRW_REGISTER_TYPE_UD);
1163 assert(x.type == BRW_REGISTER_TYPE_F);
1164 assert(y.type == BRW_REGISTER_TYPE_F);
1165
1166 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1167 *
1168 * Because this instruction does not have a 16-bit floating-point type,
1169 * the destination data type must be Word (W).
1170 *
1171 * The destination must be DWord-aligned and specify a horizontal stride
1172 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1173 * each destination channel and the upper word is not modified.
1174 */
1175 struct brw_reg dst_w = ud_reg_to_w(dst);
1176
1177 /* Give each 32-bit channel of dst the form below , where "." means
1178 * unchanged.
1179 * 0x....hhhh
1180 */
1181 brw_F32TO16(p, dst_w, y);
1182
1183 /* Now the form:
1184 * 0xhhhh0000
1185 */
1186 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1187
1188 /* And, finally the form of packHalf2x16's output:
1189 * 0xhhhhllll
1190 */
1191 brw_F32TO16(p, dst_w, x);
1192 }
1193
1194 void
1195 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1196 struct brw_reg dst,
1197 struct brw_reg src)
1198 {
1199 assert(brw->gen >= 7);
1200 assert(dst.type == BRW_REGISTER_TYPE_F);
1201 assert(src.type == BRW_REGISTER_TYPE_UD);
1202
1203 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1204 *
1205 * Because this instruction does not have a 16-bit floating-point type,
1206 * the source data type must be Word (W). The destination type must be
1207 * F (Float).
1208 */
1209 struct brw_reg src_w = ud_reg_to_w(src);
1210
1211 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1212 * For the Y case, we wish to access only the upper word; therefore
1213 * a 16-bit subregister offset is needed.
1214 */
1215 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1216 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1217 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1218 src_w.subnr += 2;
1219
1220 brw_F16TO32(p, dst, src_w);
1221 }
1222
1223 void
1224 fs_generator::generate_shader_time_add(fs_inst *inst,
1225 struct brw_reg payload,
1226 struct brw_reg offset,
1227 struct brw_reg value)
1228 {
1229 assert(brw->gen >= 7);
1230 brw_push_insn_state(p);
1231 brw_set_mask_control(p, true);
1232
1233 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1234 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1235 offset.type);
1236 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1237 value.type);
1238
1239 assert(offset.file == BRW_IMMEDIATE_VALUE);
1240 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1241 value.width = BRW_WIDTH_1;
1242 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1243 value.vstride = BRW_VERTICAL_STRIDE_0;
1244 } else {
1245 assert(value.file == BRW_IMMEDIATE_VALUE);
1246 }
1247
1248 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1249 * case, and we don't really care about squeezing every bit of performance
1250 * out of this path, so we just emit the MOVs from here.
1251 */
1252 brw_MOV(p, payload_offset, offset);
1253 brw_MOV(p, payload_value, value);
1254 brw_shader_time_add(p, payload,
1255 c->prog_data.base.binding_table.shader_time_start);
1256 brw_pop_insn_state(p);
1257
1258 mark_surface_used(c->prog_data.base.binding_table.shader_time_start);
1259 }
1260
1261 void
1262 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1263 struct brw_reg atomic_op,
1264 struct brw_reg surf_index)
1265 {
1266 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1267 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1268 surf_index.file == BRW_IMMEDIATE_VALUE &&
1269 surf_index.type == BRW_REGISTER_TYPE_UD);
1270
1271 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1272 atomic_op.dw1.ud, surf_index.dw1.ud,
1273 inst->mlen, dispatch_width / 8);
1274
1275 mark_surface_used(surf_index.dw1.ud);
1276 }
1277
1278 void
1279 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1280 struct brw_reg surf_index)
1281 {
1282 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1283 surf_index.type == BRW_REGISTER_TYPE_UD);
1284
1285 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1286 surf_index.dw1.ud,
1287 inst->mlen, dispatch_width / 8);
1288
1289 mark_surface_used(surf_index.dw1.ud);
1290 }
1291
1292 void
1293 fs_generator::generate_code(exec_list *instructions)
1294 {
1295 int last_native_insn_offset = p->next_insn_offset;
1296 const char *last_annotation_string = NULL;
1297 const void *last_annotation_ir = NULL;
1298
1299 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1300 if (shader) {
1301 printf("Native code for fragment shader %d (%d-wide dispatch):\n",
1302 prog->Name, dispatch_width);
1303 } else {
1304 printf("Native code for fragment program %d (%d-wide dispatch):\n",
1305 fp->Base.Id, dispatch_width);
1306 }
1307 }
1308
1309 cfg_t *cfg = NULL;
1310 if (unlikely(INTEL_DEBUG & DEBUG_WM))
1311 cfg = new(mem_ctx) cfg_t(instructions);
1312
1313 foreach_list(node, instructions) {
1314 fs_inst *inst = (fs_inst *)node;
1315 struct brw_reg src[3], dst;
1316
1317 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1318 foreach_list(node, &cfg->block_list) {
1319 bblock_link *link = (bblock_link *)node;
1320 bblock_t *block = link->block;
1321
1322 if (block->start == inst) {
1323 printf(" START B%d", block->block_num);
1324 foreach_list(predecessor_node, &block->parents) {
1325 bblock_link *predecessor_link =
1326 (bblock_link *)predecessor_node;
1327 bblock_t *predecessor_block = predecessor_link->block;
1328 printf(" <-B%d", predecessor_block->block_num);
1329 }
1330 printf("\n");
1331 }
1332 }
1333
1334 if (last_annotation_ir != inst->ir) {
1335 last_annotation_ir = inst->ir;
1336 if (last_annotation_ir) {
1337 printf(" ");
1338 if (shader)
1339 ((ir_instruction *)inst->ir)->print();
1340 else {
1341 const prog_instruction *fpi;
1342 fpi = (const prog_instruction *)inst->ir;
1343 printf("%d: ", (int)(fpi - fp->Base.Instructions));
1344 _mesa_fprint_instruction_opt(stdout,
1345 fpi,
1346 0, PROG_PRINT_DEBUG, NULL);
1347 }
1348 printf("\n");
1349 }
1350 }
1351 if (last_annotation_string != inst->annotation) {
1352 last_annotation_string = inst->annotation;
1353 if (last_annotation_string)
1354 printf(" %s\n", last_annotation_string);
1355 }
1356 }
1357
1358 for (unsigned int i = 0; i < 3; i++) {
1359 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1360
1361 /* The accumulator result appears to get used for the
1362 * conditional modifier generation. When negating a UD
1363 * value, there is a 33rd bit generated for the sign in the
1364 * accumulator value, so now you can't check, for example,
1365 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1366 */
1367 assert(!inst->conditional_mod ||
1368 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1369 !inst->src[i].negate);
1370 }
1371 dst = brw_reg_from_fs_reg(&inst->dst);
1372
1373 brw_set_conditionalmod(p, inst->conditional_mod);
1374 brw_set_predicate_control(p, inst->predicate);
1375 brw_set_predicate_inverse(p, inst->predicate_inverse);
1376 brw_set_flag_reg(p, 0, inst->flag_subreg);
1377 brw_set_saturate(p, inst->saturate);
1378 brw_set_mask_control(p, inst->force_writemask_all);
1379
1380 if (inst->force_uncompressed || dispatch_width == 8) {
1381 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1382 } else if (inst->force_sechalf) {
1383 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1384 } else {
1385 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1386 }
1387
1388 switch (inst->opcode) {
1389 case BRW_OPCODE_MOV:
1390 brw_MOV(p, dst, src[0]);
1391 break;
1392 case BRW_OPCODE_ADD:
1393 brw_ADD(p, dst, src[0], src[1]);
1394 break;
1395 case BRW_OPCODE_MUL:
1396 brw_MUL(p, dst, src[0], src[1]);
1397 break;
1398 case BRW_OPCODE_MACH:
1399 brw_set_acc_write_control(p, 1);
1400 brw_MACH(p, dst, src[0], src[1]);
1401 brw_set_acc_write_control(p, 0);
1402 break;
1403
1404 case BRW_OPCODE_MAD:
1405 assert(brw->gen >= 6);
1406 brw_set_access_mode(p, BRW_ALIGN_16);
1407 if (dispatch_width == 16 && !brw->is_haswell) {
1408 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1409 brw_MAD(p, dst, src[0], src[1], src[2]);
1410 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1411 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1412 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1413 } else {
1414 brw_MAD(p, dst, src[0], src[1], src[2]);
1415 }
1416 brw_set_access_mode(p, BRW_ALIGN_1);
1417 break;
1418
1419 case BRW_OPCODE_LRP:
1420 assert(brw->gen >= 6);
1421 brw_set_access_mode(p, BRW_ALIGN_16);
1422 if (dispatch_width == 16 && !brw->is_haswell) {
1423 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1424 brw_LRP(p, dst, src[0], src[1], src[2]);
1425 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1426 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1427 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1428 } else {
1429 brw_LRP(p, dst, src[0], src[1], src[2]);
1430 }
1431 brw_set_access_mode(p, BRW_ALIGN_1);
1432 break;
1433
1434 case BRW_OPCODE_FRC:
1435 brw_FRC(p, dst, src[0]);
1436 break;
1437 case BRW_OPCODE_RNDD:
1438 brw_RNDD(p, dst, src[0]);
1439 break;
1440 case BRW_OPCODE_RNDE:
1441 brw_RNDE(p, dst, src[0]);
1442 break;
1443 case BRW_OPCODE_RNDZ:
1444 brw_RNDZ(p, dst, src[0]);
1445 break;
1446
1447 case BRW_OPCODE_AND:
1448 brw_AND(p, dst, src[0], src[1]);
1449 break;
1450 case BRW_OPCODE_OR:
1451 brw_OR(p, dst, src[0], src[1]);
1452 break;
1453 case BRW_OPCODE_XOR:
1454 brw_XOR(p, dst, src[0], src[1]);
1455 break;
1456 case BRW_OPCODE_NOT:
1457 brw_NOT(p, dst, src[0]);
1458 break;
1459 case BRW_OPCODE_ASR:
1460 brw_ASR(p, dst, src[0], src[1]);
1461 break;
1462 case BRW_OPCODE_SHR:
1463 brw_SHR(p, dst, src[0], src[1]);
1464 break;
1465 case BRW_OPCODE_SHL:
1466 brw_SHL(p, dst, src[0], src[1]);
1467 break;
1468 case BRW_OPCODE_F32TO16:
1469 assert(brw->gen >= 7);
1470 brw_F32TO16(p, dst, src[0]);
1471 break;
1472 case BRW_OPCODE_F16TO32:
1473 assert(brw->gen >= 7);
1474 brw_F16TO32(p, dst, src[0]);
1475 break;
1476 case BRW_OPCODE_CMP:
1477 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1478 break;
1479 case BRW_OPCODE_SEL:
1480 brw_SEL(p, dst, src[0], src[1]);
1481 break;
1482 case BRW_OPCODE_BFREV:
1483 assert(brw->gen >= 7);
1484 /* BFREV only supports UD type for src and dst. */
1485 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1486 retype(src[0], BRW_REGISTER_TYPE_UD));
1487 break;
1488 case BRW_OPCODE_FBH:
1489 assert(brw->gen >= 7);
1490 /* FBH only supports UD type for dst. */
1491 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1492 break;
1493 case BRW_OPCODE_FBL:
1494 assert(brw->gen >= 7);
1495 /* FBL only supports UD type for dst. */
1496 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1497 break;
1498 case BRW_OPCODE_CBIT:
1499 assert(brw->gen >= 7);
1500 /* CBIT only supports UD type for dst. */
1501 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1502 break;
1503 case BRW_OPCODE_ADDC:
1504 assert(brw->gen >= 7);
1505 brw_set_acc_write_control(p, 1);
1506 brw_ADDC(p, dst, src[0], src[1]);
1507 brw_set_acc_write_control(p, 0);
1508 break;
1509 case BRW_OPCODE_SUBB:
1510 assert(brw->gen >= 7);
1511 brw_set_acc_write_control(p, 1);
1512 brw_SUBB(p, dst, src[0], src[1]);
1513 brw_set_acc_write_control(p, 0);
1514 break;
1515
1516 case BRW_OPCODE_BFE:
1517 assert(brw->gen >= 7);
1518 brw_set_access_mode(p, BRW_ALIGN_16);
1519 if (dispatch_width == 16 && !brw->is_haswell) {
1520 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1521 brw_BFE(p, dst, src[0], src[1], src[2]);
1522 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1523 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1524 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1525 } else {
1526 brw_BFE(p, dst, src[0], src[1], src[2]);
1527 }
1528 brw_set_access_mode(p, BRW_ALIGN_1);
1529 break;
1530
1531 case BRW_OPCODE_BFI1:
1532 assert(brw->gen >= 7);
1533 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1534 * should
1535 *
1536 * "Force BFI instructions to be executed always in SIMD8."
1537 */
1538 if (dispatch_width == 16 && brw->is_haswell) {
1539 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1540 brw_BFI1(p, dst, src[0], src[1]);
1541 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1542 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1543 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1544 } else {
1545 brw_BFI1(p, dst, src[0], src[1]);
1546 }
1547 break;
1548 case BRW_OPCODE_BFI2:
1549 assert(brw->gen >= 7);
1550 brw_set_access_mode(p, BRW_ALIGN_16);
1551 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1552 * should
1553 *
1554 * "Force BFI instructions to be executed always in SIMD8."
1555 *
1556 * Otherwise we would be able to emit compressed instructions like we
1557 * do for the other three-source instructions.
1558 */
1559 if (dispatch_width == 16) {
1560 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1561 brw_BFI2(p, dst, src[0], src[1], src[2]);
1562 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1563 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1564 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1565 } else {
1566 brw_BFI2(p, dst, src[0], src[1], src[2]);
1567 }
1568 brw_set_access_mode(p, BRW_ALIGN_1);
1569 break;
1570
1571 case BRW_OPCODE_IF:
1572 if (inst->src[0].file != BAD_FILE) {
1573 /* The instruction has an embedded compare (only allowed on gen6) */
1574 assert(brw->gen == 6);
1575 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1576 } else {
1577 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1578 }
1579 break;
1580
1581 case BRW_OPCODE_ELSE:
1582 brw_ELSE(p);
1583 break;
1584 case BRW_OPCODE_ENDIF:
1585 brw_ENDIF(p);
1586 break;
1587
1588 case BRW_OPCODE_DO:
1589 brw_DO(p, BRW_EXECUTE_8);
1590 break;
1591
1592 case BRW_OPCODE_BREAK:
1593 brw_BREAK(p);
1594 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1595 break;
1596 case BRW_OPCODE_CONTINUE:
1597 /* FINISHME: We need to write the loop instruction support still. */
1598 if (brw->gen >= 6)
1599 gen6_CONT(p);
1600 else
1601 brw_CONT(p);
1602 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1603 break;
1604
1605 case BRW_OPCODE_WHILE:
1606 brw_WHILE(p);
1607 break;
1608
1609 case SHADER_OPCODE_RCP:
1610 case SHADER_OPCODE_RSQ:
1611 case SHADER_OPCODE_SQRT:
1612 case SHADER_OPCODE_EXP2:
1613 case SHADER_OPCODE_LOG2:
1614 case SHADER_OPCODE_SIN:
1615 case SHADER_OPCODE_COS:
1616 if (brw->gen >= 7) {
1617 generate_math1_gen7(inst, dst, src[0]);
1618 } else if (brw->gen == 6) {
1619 generate_math1_gen6(inst, dst, src[0]);
1620 } else if (brw->gen == 5 || brw->is_g4x) {
1621 generate_math_g45(inst, dst, src[0]);
1622 } else {
1623 generate_math_gen4(inst, dst, src[0]);
1624 }
1625 break;
1626 case SHADER_OPCODE_INT_QUOTIENT:
1627 case SHADER_OPCODE_INT_REMAINDER:
1628 case SHADER_OPCODE_POW:
1629 if (brw->gen >= 7) {
1630 generate_math2_gen7(inst, dst, src[0], src[1]);
1631 } else if (brw->gen == 6) {
1632 generate_math2_gen6(inst, dst, src[0], src[1]);
1633 } else {
1634 generate_math_gen4(inst, dst, src[0]);
1635 }
1636 break;
1637 case FS_OPCODE_PIXEL_X:
1638 generate_pixel_xy(dst, true);
1639 break;
1640 case FS_OPCODE_PIXEL_Y:
1641 generate_pixel_xy(dst, false);
1642 break;
1643 case FS_OPCODE_CINTERP:
1644 brw_MOV(p, dst, src[0]);
1645 break;
1646 case FS_OPCODE_LINTERP:
1647 generate_linterp(inst, dst, src);
1648 break;
1649 case SHADER_OPCODE_TEX:
1650 case FS_OPCODE_TXB:
1651 case SHADER_OPCODE_TXD:
1652 case SHADER_OPCODE_TXF:
1653 case SHADER_OPCODE_TXF_MS:
1654 case SHADER_OPCODE_TXL:
1655 case SHADER_OPCODE_TXS:
1656 case SHADER_OPCODE_LOD:
1657 case SHADER_OPCODE_TG4:
1658 case SHADER_OPCODE_TG4_OFFSET:
1659 generate_tex(inst, dst, src[0]);
1660 break;
1661 case FS_OPCODE_DDX:
1662 generate_ddx(inst, dst, src[0]);
1663 break;
1664 case FS_OPCODE_DDY:
1665 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1666 * guarantee that c->key.render_to_fbo is set).
1667 */
1668 assert(fp->UsesDFdy);
1669 generate_ddy(inst, dst, src[0], c->key.render_to_fbo);
1670 break;
1671
1672 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1673 generate_scratch_write(inst, src[0]);
1674 break;
1675
1676 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1677 generate_scratch_read(inst, dst);
1678 break;
1679
1680 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1681 generate_scratch_read_gen7(inst, dst);
1682 break;
1683
1684 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1685 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1686 break;
1687
1688 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1689 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1690 break;
1691
1692 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1693 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1694 break;
1695
1696 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1697 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1698 break;
1699
1700 case FS_OPCODE_FB_WRITE:
1701 generate_fb_write(inst);
1702 break;
1703
1704 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1705 generate_mov_dispatch_to_flags(inst);
1706 break;
1707
1708 case FS_OPCODE_DISCARD_JUMP:
1709 generate_discard_jump(inst);
1710 break;
1711
1712 case SHADER_OPCODE_SHADER_TIME_ADD:
1713 generate_shader_time_add(inst, src[0], src[1], src[2]);
1714 break;
1715
1716 case SHADER_OPCODE_UNTYPED_ATOMIC:
1717 generate_untyped_atomic(inst, dst, src[0], src[1]);
1718 break;
1719
1720 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1721 generate_untyped_surface_read(inst, dst, src[0]);
1722 break;
1723
1724 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1725 generate_set_simd4x2_offset(inst, dst, src[0]);
1726 break;
1727
1728 case FS_OPCODE_SET_OMASK:
1729 generate_set_omask(inst, dst, src[0]);
1730 break;
1731
1732 case FS_OPCODE_SET_SAMPLE_ID:
1733 generate_set_sample_id(inst, dst, src[0], src[1]);
1734 break;
1735
1736 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1737 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1738 break;
1739
1740 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1741 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1742 generate_unpack_half_2x16_split(inst, dst, src[0]);
1743 break;
1744
1745 case FS_OPCODE_PLACEHOLDER_HALT:
1746 /* This is the place where the final HALT needs to be inserted if
1747 * we've emitted any discards. If not, this will emit no code.
1748 */
1749 patch_discard_jumps_to_fb_writes();
1750 break;
1751
1752 default:
1753 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1754 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1755 opcode_descs[inst->opcode].name);
1756 } else {
1757 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1758 }
1759 abort();
1760 }
1761
1762 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1763 brw_dump_compile(p, stdout,
1764 last_native_insn_offset, p->next_insn_offset);
1765
1766 foreach_list(node, &cfg->block_list) {
1767 bblock_link *link = (bblock_link *)node;
1768 bblock_t *block = link->block;
1769
1770 if (block->end == inst) {
1771 printf(" END B%d", block->block_num);
1772 foreach_list(successor_node, &block->children) {
1773 bblock_link *successor_link =
1774 (bblock_link *)successor_node;
1775 bblock_t *successor_block = successor_link->block;
1776 printf(" ->B%d", successor_block->block_num);
1777 }
1778 printf("\n");
1779 }
1780 }
1781 }
1782
1783 last_native_insn_offset = p->next_insn_offset;
1784 }
1785
1786 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1787 printf("\n");
1788 }
1789
1790 brw_set_uip_jip(p);
1791
1792 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
1793 * emit issues, it doesn't get the jump distances into the output,
1794 * which is often something we want to debug. So this is here in
1795 * case you're doing that.
1796 */
1797 if (0) {
1798 brw_dump_compile(p, stdout, 0, p->next_insn_offset);
1799 }
1800 }
1801
1802 const unsigned *
1803 fs_generator::generate_assembly(exec_list *simd8_instructions,
1804 exec_list *simd16_instructions,
1805 unsigned *assembly_size)
1806 {
1807 dispatch_width = 8;
1808 generate_code(simd8_instructions);
1809
1810 if (simd16_instructions) {
1811 /* We have to do a compaction pass now, or the one at the end of
1812 * execution will squash down where our prog_offset start needs
1813 * to be.
1814 */
1815 brw_compact_instructions(p);
1816
1817 /* align to 64 byte boundary. */
1818 while ((p->nr_insn * sizeof(struct brw_instruction)) % 64) {
1819 brw_NOP(p);
1820 }
1821
1822 /* Save off the start of this 16-wide program */
1823 c->prog_data.prog_offset_16 = p->nr_insn * sizeof(struct brw_instruction);
1824
1825 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1826
1827 dispatch_width = 16;
1828 generate_code(simd16_instructions);
1829 }
1830
1831 return brw_get_program(p, assembly_size);
1832 }