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i965/fs: Drop "do dual source blending" generator parameter.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 fs_generator::fs_generator(struct brw_context *brw,
40 void *mem_ctx,
41 const struct brw_wm_prog_key *key,
42 struct brw_wm_prog_data *prog_data,
43 struct gl_shader_program *prog,
44 struct gl_fragment_program *fp,
45 bool runtime_check_aads_emit,
46 bool debug_flag)
47
48 : brw(brw), key(key), prog_data(prog_data), prog(prog), fp(fp),
49 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(debug_flag),
50 mem_ctx(mem_ctx)
51 {
52 ctx = &brw->ctx;
53
54 p = rzalloc(mem_ctx, struct brw_compile);
55 brw_init_compile(brw, p, mem_ctx);
56 }
57
58 fs_generator::~fs_generator()
59 {
60 }
61
62 bool
63 fs_generator::patch_discard_jumps_to_fb_writes()
64 {
65 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
66 return false;
67
68 int scale = brw_jump_scale(brw);
69
70 /* There is a somewhat strange undocumented requirement of using
71 * HALT, according to the simulator. If some channel has HALTed to
72 * a particular UIP, then by the end of the program, every channel
73 * must have HALTed to that UIP. Furthermore, the tracking is a
74 * stack, so you can't do the final halt of a UIP after starting
75 * halting to a new UIP.
76 *
77 * Symptoms of not emitting this instruction on actual hardware
78 * included GPU hangs and sparkly rendering on the piglit discard
79 * tests.
80 */
81 brw_inst *last_halt = gen6_HALT(p);
82 brw_inst_set_uip(brw, last_halt, 1 * scale);
83 brw_inst_set_jip(brw, last_halt, 1 * scale);
84
85 int ip = p->nr_insn;
86
87 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
88 brw_inst *patch = &p->store[patch_ip->ip];
89
90 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
91 /* HALT takes a half-instruction distance from the pre-incremented IP. */
92 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
93 }
94
95 this->discard_halt_patches.make_empty();
96 return true;
97 }
98
99 void
100 fs_generator::fire_fb_write(fs_inst *inst,
101 GLuint base_reg,
102 struct brw_reg implied_header,
103 GLuint nr)
104 {
105 uint32_t msg_control;
106
107 if (brw->gen < 6) {
108 brw_push_insn_state(p);
109 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
110 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
111 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
112 brw_MOV(p,
113 brw_message_reg(base_reg + 1),
114 brw_vec8_grf(1, 0));
115 brw_pop_insn_state(p);
116 }
117
118 if (prog_data->dual_src_blend)
119 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
120 else if (dispatch_width == 16)
121 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
122 else
123 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
124
125 uint32_t surf_index =
126 prog_data->binding_table.render_target_start + inst->target;
127
128 brw_fb_WRITE(p,
129 dispatch_width,
130 base_reg,
131 implied_header,
132 msg_control,
133 surf_index,
134 nr,
135 0,
136 inst->eot,
137 inst->header_present);
138
139 brw_mark_surface_used(&prog_data->base, surf_index);
140 }
141
142 void
143 fs_generator::generate_fb_write(fs_inst *inst)
144 {
145 struct brw_reg implied_header;
146
147 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
148 * move, here's g1.
149 */
150 if (inst->header_present) {
151 brw_push_insn_state(p);
152 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
153 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
154 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
155 brw_set_default_flag_reg(p, 0, 0);
156
157 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
158 * present.
159 */
160 if ((fp && fp->UsesKill) || key->alpha_test_func) {
161 struct brw_reg pixel_mask;
162
163 if (brw->gen >= 6)
164 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
165 else
166 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
167
168 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
169 }
170
171 if (brw->gen >= 6) {
172 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
173 brw_MOV(p,
174 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
175 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
176 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
177
178 if (inst->target > 0 && key->replicate_alpha) {
179 /* Set "Source0 Alpha Present to RenderTarget" bit in message
180 * header.
181 */
182 brw_OR(p,
183 vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)),
184 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
185 brw_imm_ud(0x1 << 11));
186 }
187
188 if (inst->target > 0) {
189 /* Set the render target index for choosing BLEND_STATE. */
190 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
191 inst->base_mrf, 2),
192 BRW_REGISTER_TYPE_UD),
193 brw_imm_ud(inst->target));
194 }
195
196 implied_header = brw_null_reg();
197 } else {
198 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
199 }
200
201 brw_pop_insn_state(p);
202 } else {
203 implied_header = brw_null_reg();
204 }
205
206 if (!runtime_check_aads_emit) {
207 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
208 } else {
209 /* This can only happen in gen < 6 */
210 assert(brw->gen < 6);
211
212 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
213
214 /* Check runtime bit to detect if we have to send AA data or not */
215 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
216 brw_AND(p,
217 v1_null_ud,
218 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
219 brw_imm_ud(1<<26));
220 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
221
222 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
223 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
224 {
225 /* Don't send AA data */
226 fire_fb_write(inst, inst->base_mrf+1, implied_header, inst->mlen-1);
227 }
228 brw_land_fwd_jump(p, jmp);
229 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
230 }
231 }
232
233 void
234 fs_generator::generate_blorp_fb_write(fs_inst *inst)
235 {
236 brw_fb_WRITE(p,
237 16 /* dispatch_width */,
238 inst->base_mrf,
239 brw_reg_from_fs_reg(&inst->src[0]),
240 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
241 inst->target,
242 inst->mlen,
243 0,
244 true,
245 inst->header_present);
246 }
247
248 /* Computes the integer pixel x,y values from the origin.
249 *
250 * This is the basis of gl_FragCoord computation, but is also used
251 * pre-gen6 for computing the deltas from v0 for computing
252 * interpolation.
253 */
254 void
255 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
256 {
257 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
258 struct brw_reg src;
259 struct brw_reg deltas;
260
261 if (is_x) {
262 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
263 deltas = brw_imm_v(0x10101010);
264 } else {
265 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
266 deltas = brw_imm_v(0x11001100);
267 }
268
269 if (dispatch_width == 16) {
270 dst = vec16(dst);
271 }
272
273 /* We do this SIMD8 or SIMD16, but since the destination is UW we
274 * don't do compression in the SIMD16 case.
275 */
276 brw_push_insn_state(p);
277 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
278 brw_ADD(p, dst, src, deltas);
279 brw_pop_insn_state(p);
280 }
281
282 void
283 fs_generator::generate_linterp(fs_inst *inst,
284 struct brw_reg dst, struct brw_reg *src)
285 {
286 struct brw_reg delta_x = src[0];
287 struct brw_reg delta_y = src[1];
288 struct brw_reg interp = src[2];
289
290 if (brw->has_pln &&
291 delta_y.nr == delta_x.nr + 1 &&
292 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
293 brw_PLN(p, dst, interp, delta_x);
294 } else {
295 brw_LINE(p, brw_null_reg(), interp, delta_x);
296 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
297 }
298 }
299
300 void
301 fs_generator::generate_math_gen6(fs_inst *inst,
302 struct brw_reg dst,
303 struct brw_reg src0,
304 struct brw_reg src1)
305 {
306 int op = brw_math_function(inst->opcode);
307 bool binop = src1.file == BRW_GENERAL_REGISTER_FILE;
308
309 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
310 gen6_math(p, dst, op, src0, src1);
311
312 if (dispatch_width == 16) {
313 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
314 gen6_math(p, sechalf(dst), op, sechalf(src0),
315 binop ? sechalf(src1) : brw_null_reg());
316 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
317 }
318 }
319
320 void
321 fs_generator::generate_math_gen4(fs_inst *inst,
322 struct brw_reg dst,
323 struct brw_reg src)
324 {
325 int op = brw_math_function(inst->opcode);
326
327 assert(inst->mlen >= 1);
328
329 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
330 gen4_math(p, dst,
331 op,
332 inst->base_mrf, src,
333 BRW_MATH_DATA_VECTOR,
334 BRW_MATH_PRECISION_FULL);
335
336 if (dispatch_width == 16) {
337 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
338 gen4_math(p, sechalf(dst),
339 op,
340 inst->base_mrf + 1, sechalf(src),
341 BRW_MATH_DATA_VECTOR,
342 BRW_MATH_PRECISION_FULL);
343
344 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
345 }
346 }
347
348 void
349 fs_generator::generate_math_g45(fs_inst *inst,
350 struct brw_reg dst,
351 struct brw_reg src)
352 {
353 if (inst->opcode == SHADER_OPCODE_POW ||
354 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
355 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
356 generate_math_gen4(inst, dst, src);
357 return;
358 }
359
360 int op = brw_math_function(inst->opcode);
361
362 assert(inst->mlen >= 1);
363
364 gen4_math(p, dst,
365 op,
366 inst->base_mrf, src,
367 BRW_MATH_DATA_VECTOR,
368 BRW_MATH_PRECISION_FULL);
369 }
370
371 void
372 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
373 struct brw_reg sampler_index)
374 {
375 int msg_type = -1;
376 int rlen = 4;
377 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
378 uint32_t return_format;
379
380 switch (dst.type) {
381 case BRW_REGISTER_TYPE_D:
382 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
383 break;
384 case BRW_REGISTER_TYPE_UD:
385 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
386 break;
387 default:
388 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
389 break;
390 }
391
392 if (dispatch_width == 16 &&
393 !inst->force_uncompressed && !inst->force_sechalf)
394 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
395
396 if (brw->gen >= 5) {
397 switch (inst->opcode) {
398 case SHADER_OPCODE_TEX:
399 if (inst->shadow_compare) {
400 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
401 } else {
402 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
403 }
404 break;
405 case FS_OPCODE_TXB:
406 if (inst->shadow_compare) {
407 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
408 } else {
409 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
410 }
411 break;
412 case SHADER_OPCODE_TXL:
413 if (inst->shadow_compare) {
414 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
415 } else {
416 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
417 }
418 break;
419 case SHADER_OPCODE_TXS:
420 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
421 break;
422 case SHADER_OPCODE_TXD:
423 if (inst->shadow_compare) {
424 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
425 assert(brw->gen >= 8 || brw->is_haswell);
426 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
427 } else {
428 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
429 }
430 break;
431 case SHADER_OPCODE_TXF:
432 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
433 break;
434 case SHADER_OPCODE_TXF_CMS:
435 if (brw->gen >= 7)
436 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
437 else
438 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
439 break;
440 case SHADER_OPCODE_TXF_UMS:
441 assert(brw->gen >= 7);
442 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
443 break;
444 case SHADER_OPCODE_TXF_MCS:
445 assert(brw->gen >= 7);
446 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
447 break;
448 case SHADER_OPCODE_LOD:
449 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
450 break;
451 case SHADER_OPCODE_TG4:
452 if (inst->shadow_compare) {
453 assert(brw->gen >= 7);
454 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
455 } else {
456 assert(brw->gen >= 6);
457 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
458 }
459 break;
460 case SHADER_OPCODE_TG4_OFFSET:
461 assert(brw->gen >= 7);
462 if (inst->shadow_compare) {
463 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
464 } else {
465 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
466 }
467 break;
468 default:
469 unreachable("not reached");
470 }
471 } else {
472 switch (inst->opcode) {
473 case SHADER_OPCODE_TEX:
474 /* Note that G45 and older determines shadow compare and dispatch width
475 * from message length for most messages.
476 */
477 assert(dispatch_width == 8);
478 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
479 if (inst->shadow_compare) {
480 assert(inst->mlen == 6);
481 } else {
482 assert(inst->mlen <= 4);
483 }
484 break;
485 case FS_OPCODE_TXB:
486 if (inst->shadow_compare) {
487 assert(inst->mlen == 6);
488 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
489 } else {
490 assert(inst->mlen == 9);
491 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
492 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
493 }
494 break;
495 case SHADER_OPCODE_TXL:
496 if (inst->shadow_compare) {
497 assert(inst->mlen == 6);
498 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
499 } else {
500 assert(inst->mlen == 9);
501 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
502 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
503 }
504 break;
505 case SHADER_OPCODE_TXD:
506 /* There is no sample_d_c message; comparisons are done manually */
507 assert(inst->mlen == 7 || inst->mlen == 10);
508 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
509 break;
510 case SHADER_OPCODE_TXF:
511 assert(inst->mlen == 9);
512 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
513 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
514 break;
515 case SHADER_OPCODE_TXS:
516 assert(inst->mlen == 3);
517 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
518 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
519 break;
520 default:
521 unreachable("not reached");
522 }
523 }
524 assert(msg_type != -1);
525
526 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
527 rlen = 8;
528 dst = vec16(dst);
529 }
530
531 if (brw->gen >= 7 && inst->header_present && dispatch_width == 16) {
532 /* The send-from-GRF for SIMD16 texturing with a header has an extra
533 * hardware register allocated to it, which we need to skip over (since
534 * our coordinates in the payload are in the even-numbered registers,
535 * and the header comes right before the first one).
536 */
537 assert(src.file == BRW_GENERAL_REGISTER_FILE);
538 src.nr++;
539 }
540
541 assert(sampler_index.file == BRW_IMMEDIATE_VALUE);
542 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
543
544 uint32_t sampler = sampler_index.dw1.ud;
545
546 /* Load the message header if present. If there's a texture offset,
547 * we need to set it up explicitly and load the offset bitfield.
548 * Otherwise, we can use an implied move from g0 to the first message reg.
549 */
550 if (inst->header_present) {
551 if (brw->gen < 6 && !inst->texture_offset) {
552 /* Set up an implied move from g0 to the MRF. */
553 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
554 } else {
555 struct brw_reg header_reg;
556
557 if (brw->gen >= 7) {
558 header_reg = src;
559 } else {
560 assert(inst->base_mrf != -1);
561 header_reg = brw_message_reg(inst->base_mrf);
562 }
563
564 brw_push_insn_state(p);
565 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
566 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
567 /* Explicitly set up the message header by copying g0 to the MRF. */
568 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
569
570 if (inst->texture_offset) {
571 /* Set the offset bits in DWord 2. */
572 brw_MOV(p, get_element_ud(header_reg, 2),
573 brw_imm_ud(inst->texture_offset));
574 }
575
576 if (sampler >= 16) {
577 /* The "Sampler Index" field can only store values between 0 and 15.
578 * However, we can add an offset to the "Sampler State Pointer"
579 * field, effectively selecting a different set of 16 samplers.
580 *
581 * The "Sampler State Pointer" needs to be aligned to a 32-byte
582 * offset, and each sampler state is only 16-bytes, so we can't
583 * exclusively use the offset - we have to use both.
584 */
585 assert(brw->gen >= 8 || brw->is_haswell);
586 const int sampler_state_size = 16; /* 16 bytes */
587 brw_ADD(p,
588 get_element_ud(header_reg, 3),
589 get_element_ud(brw_vec8_grf(0, 0), 3),
590 brw_imm_ud(16 * (sampler / 16) * sampler_state_size));
591 }
592 brw_pop_insn_state(p);
593 }
594 }
595
596 uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
597 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
598 ? prog_data->base.binding_table.gather_texture_start
599 : prog_data->base.binding_table.texture_start) + sampler;
600
601 brw_SAMPLE(p,
602 retype(dst, BRW_REGISTER_TYPE_UW),
603 inst->base_mrf,
604 src,
605 surface_index,
606 sampler % 16,
607 msg_type,
608 rlen,
609 inst->mlen,
610 inst->header_present,
611 simd_mode,
612 return_format);
613
614 brw_mark_surface_used(&prog_data->base, surface_index);
615 }
616
617
618 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
619 * looking like:
620 *
621 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
622 *
623 * Ideally, we want to produce:
624 *
625 * DDX DDY
626 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
627 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
628 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
629 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
630 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
631 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
632 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
633 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
634 *
635 * and add another set of two more subspans if in 16-pixel dispatch mode.
636 *
637 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
638 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
639 * pair. But the ideal approximation may impose a huge performance cost on
640 * sample_d. On at least Haswell, sample_d instruction does some
641 * optimizations if the same LOD is used for all pixels in the subspan.
642 *
643 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
644 * appropriate swizzling.
645 */
646 void
647 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
648 {
649 unsigned vstride, width;
650
651 if (key->high_quality_derivatives) {
652 /* produce accurate derivatives */
653 vstride = BRW_VERTICAL_STRIDE_2;
654 width = BRW_WIDTH_2;
655 }
656 else {
657 /* replicate the derivative at the top-left pixel to other pixels */
658 vstride = BRW_VERTICAL_STRIDE_4;
659 width = BRW_WIDTH_4;
660 }
661
662 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
663 BRW_REGISTER_TYPE_F,
664 vstride,
665 width,
666 BRW_HORIZONTAL_STRIDE_0,
667 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
668 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
669 BRW_REGISTER_TYPE_F,
670 vstride,
671 width,
672 BRW_HORIZONTAL_STRIDE_0,
673 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
674 brw_ADD(p, dst, src0, negate(src1));
675 }
676
677 /* The negate_value boolean is used to negate the derivative computation for
678 * FBOs, since they place the origin at the upper left instead of the lower
679 * left.
680 */
681 void
682 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
683 bool negate_value)
684 {
685 if (key->high_quality_derivatives) {
686 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
687 * Region Restrictions):
688 *
689 * In Align16 access mode, SIMD16 is not allowed for DW operations
690 * and SIMD8 is not allowed for DF operations.
691 *
692 * In this context, "DW operations" means "operations acting on 32-bit
693 * values", so it includes operations on floats.
694 *
695 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
696 * (Instruction Compression -> Rules and Restrictions):
697 *
698 * A compressed instruction must be in Align1 access mode. Align16
699 * mode instructions cannot be compressed.
700 *
701 * Similar text exists in the g45 PRM.
702 *
703 * On these platforms, if we're building a SIMD16 shader, we need to
704 * manually unroll to a pair of SIMD8 instructions.
705 */
706 bool unroll_to_simd8 =
707 (dispatch_width == 16 &&
708 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
709
710 /* produce accurate derivatives */
711 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
712 BRW_REGISTER_TYPE_F,
713 BRW_VERTICAL_STRIDE_4,
714 BRW_WIDTH_4,
715 BRW_HORIZONTAL_STRIDE_1,
716 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
717 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
718 BRW_REGISTER_TYPE_F,
719 BRW_VERTICAL_STRIDE_4,
720 BRW_WIDTH_4,
721 BRW_HORIZONTAL_STRIDE_1,
722 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
723 brw_push_insn_state(p);
724 brw_set_default_access_mode(p, BRW_ALIGN_16);
725 if (unroll_to_simd8)
726 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
727 if (negate_value)
728 brw_ADD(p, dst, src1, negate(src0));
729 else
730 brw_ADD(p, dst, src0, negate(src1));
731 if (unroll_to_simd8) {
732 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
733 src0 = sechalf(src0);
734 src1 = sechalf(src1);
735 dst = sechalf(dst);
736 if (negate_value)
737 brw_ADD(p, dst, src1, negate(src0));
738 else
739 brw_ADD(p, dst, src0, negate(src1));
740 }
741 brw_pop_insn_state(p);
742 } else {
743 /* replicate the derivative at the top-left pixel to other pixels */
744 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
745 BRW_REGISTER_TYPE_F,
746 BRW_VERTICAL_STRIDE_4,
747 BRW_WIDTH_4,
748 BRW_HORIZONTAL_STRIDE_0,
749 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
750 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
751 BRW_REGISTER_TYPE_F,
752 BRW_VERTICAL_STRIDE_4,
753 BRW_WIDTH_4,
754 BRW_HORIZONTAL_STRIDE_0,
755 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
756 if (negate_value)
757 brw_ADD(p, dst, src1, negate(src0));
758 else
759 brw_ADD(p, dst, src0, negate(src1));
760 }
761 }
762
763 void
764 fs_generator::generate_discard_jump(fs_inst *inst)
765 {
766 assert(brw->gen >= 6);
767
768 /* This HALT will be patched up at FB write time to point UIP at the end of
769 * the program, and at brw_uip_jip() JIP will be set to the end of the
770 * current block (or the program).
771 */
772 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
773
774 brw_push_insn_state(p);
775 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
776 gen6_HALT(p);
777 brw_pop_insn_state(p);
778 }
779
780 void
781 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
782 {
783 assert(inst->mlen != 0);
784
785 brw_MOV(p,
786 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
787 retype(src, BRW_REGISTER_TYPE_UD));
788 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
789 dispatch_width / 8, inst->offset);
790 }
791
792 void
793 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
794 {
795 assert(inst->mlen != 0);
796
797 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
798 dispatch_width / 8, inst->offset);
799 }
800
801 void
802 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
803 {
804 gen7_block_read_scratch(p, dst, dispatch_width / 8, inst->offset);
805 }
806
807 void
808 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
809 struct brw_reg dst,
810 struct brw_reg index,
811 struct brw_reg offset)
812 {
813 assert(inst->mlen != 0);
814
815 assert(index.file == BRW_IMMEDIATE_VALUE &&
816 index.type == BRW_REGISTER_TYPE_UD);
817 uint32_t surf_index = index.dw1.ud;
818
819 assert(offset.file == BRW_IMMEDIATE_VALUE &&
820 offset.type == BRW_REGISTER_TYPE_UD);
821 uint32_t read_offset = offset.dw1.ud;
822
823 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
824 read_offset, surf_index);
825
826 brw_mark_surface_used(&prog_data->base, surf_index);
827 }
828
829 void
830 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
831 struct brw_reg dst,
832 struct brw_reg index,
833 struct brw_reg offset)
834 {
835 assert(inst->mlen == 0);
836
837 assert(index.file == BRW_IMMEDIATE_VALUE &&
838 index.type == BRW_REGISTER_TYPE_UD);
839 uint32_t surf_index = index.dw1.ud;
840
841 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
842 /* Reference just the dword we need, to avoid angering validate_reg(). */
843 offset = brw_vec1_grf(offset.nr, 0);
844
845 brw_push_insn_state(p);
846 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
847 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
848 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
849 brw_pop_insn_state(p);
850
851 /* We use the SIMD4x2 mode because we want to end up with 4 components in
852 * the destination loaded consecutively from the same offset (which appears
853 * in the first component, and the rest are ignored).
854 */
855 dst.width = BRW_WIDTH_4;
856 brw_set_dest(p, send, dst);
857 brw_set_src0(p, send, offset);
858 brw_set_sampler_message(p, send,
859 surf_index,
860 0, /* LD message ignores sampler unit */
861 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
862 1, /* rlen */
863 1, /* mlen */
864 false, /* no header */
865 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
866 0);
867
868 brw_mark_surface_used(&prog_data->base, surf_index);
869 }
870
871 void
872 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
873 struct brw_reg dst,
874 struct brw_reg index,
875 struct brw_reg offset)
876 {
877 assert(brw->gen < 7); /* Should use the gen7 variant. */
878 assert(inst->header_present);
879 assert(inst->mlen);
880
881 assert(index.file == BRW_IMMEDIATE_VALUE &&
882 index.type == BRW_REGISTER_TYPE_UD);
883 uint32_t surf_index = index.dw1.ud;
884
885 uint32_t simd_mode, rlen, msg_type;
886 if (dispatch_width == 16) {
887 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
888 rlen = 8;
889 } else {
890 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
891 rlen = 4;
892 }
893
894 if (brw->gen >= 5)
895 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
896 else {
897 /* We always use the SIMD16 message so that we only have to load U, and
898 * not V or R.
899 */
900 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
901 assert(inst->mlen == 3);
902 assert(inst->regs_written == 8);
903 rlen = 8;
904 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
905 }
906
907 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
908 BRW_REGISTER_TYPE_D);
909 brw_MOV(p, offset_mrf, offset);
910
911 struct brw_reg header = brw_vec8_grf(0, 0);
912 gen6_resolve_implied_move(p, &header, inst->base_mrf);
913
914 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
915 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
916 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
917 brw_set_src0(p, send, header);
918 if (brw->gen < 6)
919 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
920
921 /* Our surface is set up as floats, regardless of what actual data is
922 * stored in it.
923 */
924 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
925 brw_set_sampler_message(p, send,
926 surf_index,
927 0, /* sampler (unused) */
928 msg_type,
929 rlen,
930 inst->mlen,
931 inst->header_present,
932 simd_mode,
933 return_format);
934
935 brw_mark_surface_used(&prog_data->base, surf_index);
936 }
937
938 void
939 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
940 struct brw_reg dst,
941 struct brw_reg index,
942 struct brw_reg offset)
943 {
944 assert(brw->gen >= 7);
945 /* Varying-offset pull constant loads are treated as a normal expression on
946 * gen7, so the fact that it's a send message is hidden at the IR level.
947 */
948 assert(!inst->header_present);
949 assert(!inst->mlen);
950
951 assert(index.file == BRW_IMMEDIATE_VALUE &&
952 index.type == BRW_REGISTER_TYPE_UD);
953 uint32_t surf_index = index.dw1.ud;
954
955 uint32_t simd_mode, rlen, mlen;
956 if (dispatch_width == 16) {
957 mlen = 2;
958 rlen = 8;
959 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
960 } else {
961 mlen = 1;
962 rlen = 4;
963 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
964 }
965
966 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
967 brw_set_dest(p, send, dst);
968 brw_set_src0(p, send, offset);
969 brw_set_sampler_message(p, send,
970 surf_index,
971 0, /* LD message ignores sampler unit */
972 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
973 rlen,
974 mlen,
975 false, /* no header */
976 simd_mode,
977 0);
978
979 brw_mark_surface_used(&prog_data->base, surf_index);
980 }
981
982 /**
983 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
984 * into the flags register (f0.0).
985 *
986 * Used only on Gen6 and above.
987 */
988 void
989 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
990 {
991 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
992 struct brw_reg dispatch_mask;
993
994 if (brw->gen >= 6)
995 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
996 else
997 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
998
999 brw_push_insn_state(p);
1000 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1001 brw_MOV(p, flags, dispatch_mask);
1002 brw_pop_insn_state(p);
1003 }
1004
1005 void
1006 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1007 struct brw_reg dst,
1008 struct brw_reg src,
1009 struct brw_reg msg_data,
1010 unsigned msg_type)
1011 {
1012 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1013 msg_data.type == BRW_REGISTER_TYPE_UD);
1014
1015 brw_pixel_interpolator_query(p,
1016 retype(dst, BRW_REGISTER_TYPE_UW),
1017 src,
1018 inst->pi_noperspective,
1019 msg_type,
1020 msg_data.dw1.ud,
1021 inst->mlen,
1022 inst->regs_written);
1023 }
1024
1025
1026 static uint32_t brw_file_from_reg(fs_reg *reg)
1027 {
1028 switch (reg->file) {
1029 case GRF:
1030 return BRW_GENERAL_REGISTER_FILE;
1031 case MRF:
1032 return BRW_MESSAGE_REGISTER_FILE;
1033 case IMM:
1034 return BRW_IMMEDIATE_VALUE;
1035 default:
1036 unreachable("not reached");
1037 }
1038 }
1039
1040 struct brw_reg
1041 brw_reg_from_fs_reg(fs_reg *reg)
1042 {
1043 struct brw_reg brw_reg;
1044
1045 switch (reg->file) {
1046 case GRF:
1047 case MRF:
1048 if (reg->stride == 0) {
1049 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
1050 } else {
1051 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1052 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
1053 }
1054
1055 brw_reg = retype(brw_reg, reg->type);
1056 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
1057 break;
1058 case IMM:
1059 switch (reg->type) {
1060 case BRW_REGISTER_TYPE_F:
1061 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
1062 break;
1063 case BRW_REGISTER_TYPE_D:
1064 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
1065 break;
1066 case BRW_REGISTER_TYPE_UD:
1067 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
1068 break;
1069 default:
1070 unreachable("not reached");
1071 }
1072 break;
1073 case HW_REG:
1074 assert(reg->type == reg->fixed_hw_reg.type);
1075 brw_reg = reg->fixed_hw_reg;
1076 break;
1077 case BAD_FILE:
1078 /* Probably unused. */
1079 brw_reg = brw_null_reg();
1080 break;
1081 case UNIFORM:
1082 unreachable("not reached");
1083 default:
1084 unreachable("not reached");
1085 }
1086 if (reg->abs)
1087 brw_reg = brw_abs(brw_reg);
1088 if (reg->negate)
1089 brw_reg = negate(brw_reg);
1090
1091 return brw_reg;
1092 }
1093
1094 /**
1095 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1096 * sampler LD messages.
1097 *
1098 * We don't want to bake it into the send message's code generation because
1099 * that means we don't get a chance to schedule the instructions.
1100 */
1101 void
1102 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1103 struct brw_reg dst,
1104 struct brw_reg value)
1105 {
1106 assert(value.file == BRW_IMMEDIATE_VALUE);
1107
1108 brw_push_insn_state(p);
1109 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1110 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1111 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1112 brw_pop_insn_state(p);
1113 }
1114
1115 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1116 * (when mask is passed as a uniform) of register mask before moving it
1117 * to register dst.
1118 */
1119 void
1120 fs_generator::generate_set_omask(fs_inst *inst,
1121 struct brw_reg dst,
1122 struct brw_reg mask)
1123 {
1124 bool stride_8_8_1 =
1125 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1126 mask.width == BRW_WIDTH_8 &&
1127 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1128
1129 bool stride_0_1_0 =
1130 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1131 mask.width == BRW_WIDTH_1 &&
1132 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1133
1134 assert(stride_8_8_1 || stride_0_1_0);
1135 assert(dst.type == BRW_REGISTER_TYPE_UW);
1136
1137 if (dispatch_width == 16)
1138 dst = vec16(dst);
1139 brw_push_insn_state(p);
1140 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1141 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1142
1143 if (stride_8_8_1) {
1144 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1145 } else if (stride_0_1_0) {
1146 brw_MOV(p, dst, retype(mask, dst.type));
1147 }
1148 brw_pop_insn_state(p);
1149 }
1150
1151 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1152 * the ADD instruction.
1153 */
1154 void
1155 fs_generator::generate_set_sample_id(fs_inst *inst,
1156 struct brw_reg dst,
1157 struct brw_reg src0,
1158 struct brw_reg src1)
1159 {
1160 assert(dst.type == BRW_REGISTER_TYPE_D ||
1161 dst.type == BRW_REGISTER_TYPE_UD);
1162 assert(src0.type == BRW_REGISTER_TYPE_D ||
1163 src0.type == BRW_REGISTER_TYPE_UD);
1164
1165 brw_push_insn_state(p);
1166 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1167 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1168 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1169 brw_ADD(p, dst, src0, reg);
1170 if (dispatch_width == 16)
1171 brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
1172 brw_pop_insn_state(p);
1173 }
1174
1175 /**
1176 * Change the register's data type from UD to W, doubling the strides in order
1177 * to compensate for halving the data type width.
1178 */
1179 static struct brw_reg
1180 ud_reg_to_w(struct brw_reg r)
1181 {
1182 assert(r.type == BRW_REGISTER_TYPE_UD);
1183 r.type = BRW_REGISTER_TYPE_W;
1184
1185 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1186 * doubles the real stride.
1187 */
1188 if (r.hstride != 0)
1189 ++r.hstride;
1190 if (r.vstride != 0)
1191 ++r.vstride;
1192
1193 return r;
1194 }
1195
1196 void
1197 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1198 struct brw_reg dst,
1199 struct brw_reg x,
1200 struct brw_reg y)
1201 {
1202 assert(brw->gen >= 7);
1203 assert(dst.type == BRW_REGISTER_TYPE_UD);
1204 assert(x.type == BRW_REGISTER_TYPE_F);
1205 assert(y.type == BRW_REGISTER_TYPE_F);
1206
1207 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1208 *
1209 * Because this instruction does not have a 16-bit floating-point type,
1210 * the destination data type must be Word (W).
1211 *
1212 * The destination must be DWord-aligned and specify a horizontal stride
1213 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1214 * each destination channel and the upper word is not modified.
1215 */
1216 struct brw_reg dst_w = ud_reg_to_w(dst);
1217
1218 /* Give each 32-bit channel of dst the form below , where "." means
1219 * unchanged.
1220 * 0x....hhhh
1221 */
1222 brw_F32TO16(p, dst_w, y);
1223
1224 /* Now the form:
1225 * 0xhhhh0000
1226 */
1227 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1228
1229 /* And, finally the form of packHalf2x16's output:
1230 * 0xhhhhllll
1231 */
1232 brw_F32TO16(p, dst_w, x);
1233 }
1234
1235 void
1236 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1237 struct brw_reg dst,
1238 struct brw_reg src)
1239 {
1240 assert(brw->gen >= 7);
1241 assert(dst.type == BRW_REGISTER_TYPE_F);
1242 assert(src.type == BRW_REGISTER_TYPE_UD);
1243
1244 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1245 *
1246 * Because this instruction does not have a 16-bit floating-point type,
1247 * the source data type must be Word (W). The destination type must be
1248 * F (Float).
1249 */
1250 struct brw_reg src_w = ud_reg_to_w(src);
1251
1252 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1253 * For the Y case, we wish to access only the upper word; therefore
1254 * a 16-bit subregister offset is needed.
1255 */
1256 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1257 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1258 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1259 src_w.subnr += 2;
1260
1261 brw_F16TO32(p, dst, src_w);
1262 }
1263
1264 void
1265 fs_generator::generate_shader_time_add(fs_inst *inst,
1266 struct brw_reg payload,
1267 struct brw_reg offset,
1268 struct brw_reg value)
1269 {
1270 assert(brw->gen >= 7);
1271 brw_push_insn_state(p);
1272 brw_set_default_mask_control(p, true);
1273
1274 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1275 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1276 offset.type);
1277 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1278 value.type);
1279
1280 assert(offset.file == BRW_IMMEDIATE_VALUE);
1281 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1282 value.width = BRW_WIDTH_1;
1283 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1284 value.vstride = BRW_VERTICAL_STRIDE_0;
1285 } else {
1286 assert(value.file == BRW_IMMEDIATE_VALUE);
1287 }
1288
1289 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1290 * case, and we don't really care about squeezing every bit of performance
1291 * out of this path, so we just emit the MOVs from here.
1292 */
1293 brw_MOV(p, payload_offset, offset);
1294 brw_MOV(p, payload_value, value);
1295 brw_shader_time_add(p, payload,
1296 prog_data->base.binding_table.shader_time_start);
1297 brw_pop_insn_state(p);
1298
1299 brw_mark_surface_used(&prog_data->base,
1300 prog_data->base.binding_table.shader_time_start);
1301 }
1302
1303 void
1304 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1305 struct brw_reg atomic_op,
1306 struct brw_reg surf_index)
1307 {
1308 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1309 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1310 surf_index.file == BRW_IMMEDIATE_VALUE &&
1311 surf_index.type == BRW_REGISTER_TYPE_UD);
1312
1313 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1314 atomic_op.dw1.ud, surf_index.dw1.ud,
1315 inst->mlen, dispatch_width / 8);
1316
1317 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1318 }
1319
1320 void
1321 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1322 struct brw_reg surf_index)
1323 {
1324 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1325 surf_index.type == BRW_REGISTER_TYPE_UD);
1326
1327 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1328 surf_index.dw1.ud,
1329 inst->mlen, dispatch_width / 8);
1330
1331 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1332 }
1333
1334 void
1335 fs_generator::generate_code(exec_list *instructions)
1336 {
1337 int start_offset = p->next_insn_offset;
1338
1339 struct annotation_info annotation;
1340 memset(&annotation, 0, sizeof(annotation));
1341
1342 cfg_t *cfg = NULL;
1343 if (unlikely(debug_flag))
1344 cfg = new(mem_ctx) cfg_t(instructions);
1345
1346 foreach_in_list(fs_inst, inst, instructions) {
1347 struct brw_reg src[3], dst;
1348 unsigned int last_insn_offset = p->next_insn_offset;
1349
1350 if (unlikely(debug_flag))
1351 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1352
1353 for (unsigned int i = 0; i < inst->sources; i++) {
1354 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1355
1356 /* The accumulator result appears to get used for the
1357 * conditional modifier generation. When negating a UD
1358 * value, there is a 33rd bit generated for the sign in the
1359 * accumulator value, so now you can't check, for example,
1360 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1361 */
1362 assert(!inst->conditional_mod ||
1363 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1364 !inst->src[i].negate);
1365 }
1366 dst = brw_reg_from_fs_reg(&inst->dst);
1367
1368 brw_set_default_predicate_control(p, inst->predicate);
1369 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1370 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1371 brw_set_default_saturate(p, inst->saturate);
1372 brw_set_default_mask_control(p, inst->force_writemask_all);
1373 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1374
1375 if (inst->force_uncompressed || dispatch_width == 8) {
1376 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1377 } else if (inst->force_sechalf) {
1378 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1379 } else {
1380 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1381 }
1382
1383 switch (inst->opcode) {
1384 case BRW_OPCODE_MOV:
1385 brw_MOV(p, dst, src[0]);
1386 break;
1387 case BRW_OPCODE_ADD:
1388 brw_ADD(p, dst, src[0], src[1]);
1389 break;
1390 case BRW_OPCODE_MUL:
1391 brw_MUL(p, dst, src[0], src[1]);
1392 break;
1393 case BRW_OPCODE_AVG:
1394 brw_AVG(p, dst, src[0], src[1]);
1395 break;
1396 case BRW_OPCODE_MACH:
1397 brw_MACH(p, dst, src[0], src[1]);
1398 break;
1399
1400 case BRW_OPCODE_MAD:
1401 assert(brw->gen >= 6);
1402 brw_set_default_access_mode(p, BRW_ALIGN_16);
1403 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1404 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1405 brw_MAD(p, dst, src[0], src[1], src[2]);
1406 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1407 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1408 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1409 } else {
1410 brw_MAD(p, dst, src[0], src[1], src[2]);
1411 }
1412 brw_set_default_access_mode(p, BRW_ALIGN_1);
1413 break;
1414
1415 case BRW_OPCODE_LRP:
1416 assert(brw->gen >= 6);
1417 brw_set_default_access_mode(p, BRW_ALIGN_16);
1418 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1419 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1420 brw_LRP(p, dst, src[0], src[1], src[2]);
1421 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1422 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1423 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1424 } else {
1425 brw_LRP(p, dst, src[0], src[1], src[2]);
1426 }
1427 brw_set_default_access_mode(p, BRW_ALIGN_1);
1428 break;
1429
1430 case BRW_OPCODE_FRC:
1431 brw_FRC(p, dst, src[0]);
1432 break;
1433 case BRW_OPCODE_RNDD:
1434 brw_RNDD(p, dst, src[0]);
1435 break;
1436 case BRW_OPCODE_RNDE:
1437 brw_RNDE(p, dst, src[0]);
1438 break;
1439 case BRW_OPCODE_RNDZ:
1440 brw_RNDZ(p, dst, src[0]);
1441 break;
1442
1443 case BRW_OPCODE_AND:
1444 brw_AND(p, dst, src[0], src[1]);
1445 break;
1446 case BRW_OPCODE_OR:
1447 brw_OR(p, dst, src[0], src[1]);
1448 break;
1449 case BRW_OPCODE_XOR:
1450 brw_XOR(p, dst, src[0], src[1]);
1451 break;
1452 case BRW_OPCODE_NOT:
1453 brw_NOT(p, dst, src[0]);
1454 break;
1455 case BRW_OPCODE_ASR:
1456 brw_ASR(p, dst, src[0], src[1]);
1457 break;
1458 case BRW_OPCODE_SHR:
1459 brw_SHR(p, dst, src[0], src[1]);
1460 break;
1461 case BRW_OPCODE_SHL:
1462 brw_SHL(p, dst, src[0], src[1]);
1463 break;
1464 case BRW_OPCODE_F32TO16:
1465 assert(brw->gen >= 7);
1466 brw_F32TO16(p, dst, src[0]);
1467 break;
1468 case BRW_OPCODE_F16TO32:
1469 assert(brw->gen >= 7);
1470 brw_F16TO32(p, dst, src[0]);
1471 break;
1472 case BRW_OPCODE_CMP:
1473 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1474 break;
1475 case BRW_OPCODE_SEL:
1476 brw_SEL(p, dst, src[0], src[1]);
1477 break;
1478 case BRW_OPCODE_BFREV:
1479 assert(brw->gen >= 7);
1480 /* BFREV only supports UD type for src and dst. */
1481 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1482 retype(src[0], BRW_REGISTER_TYPE_UD));
1483 break;
1484 case BRW_OPCODE_FBH:
1485 assert(brw->gen >= 7);
1486 /* FBH only supports UD type for dst. */
1487 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1488 break;
1489 case BRW_OPCODE_FBL:
1490 assert(brw->gen >= 7);
1491 /* FBL only supports UD type for dst. */
1492 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1493 break;
1494 case BRW_OPCODE_CBIT:
1495 assert(brw->gen >= 7);
1496 /* CBIT only supports UD type for dst. */
1497 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1498 break;
1499 case BRW_OPCODE_ADDC:
1500 assert(brw->gen >= 7);
1501 brw_ADDC(p, dst, src[0], src[1]);
1502 break;
1503 case BRW_OPCODE_SUBB:
1504 assert(brw->gen >= 7);
1505 brw_SUBB(p, dst, src[0], src[1]);
1506 break;
1507 case BRW_OPCODE_MAC:
1508 brw_MAC(p, dst, src[0], src[1]);
1509 break;
1510
1511 case BRW_OPCODE_BFE:
1512 assert(brw->gen >= 7);
1513 brw_set_default_access_mode(p, BRW_ALIGN_16);
1514 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1515 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1516 brw_BFE(p, dst, src[0], src[1], src[2]);
1517 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1518 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1519 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1520 } else {
1521 brw_BFE(p, dst, src[0], src[1], src[2]);
1522 }
1523 brw_set_default_access_mode(p, BRW_ALIGN_1);
1524 break;
1525
1526 case BRW_OPCODE_BFI1:
1527 assert(brw->gen >= 7);
1528 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1529 * should
1530 *
1531 * "Force BFI instructions to be executed always in SIMD8."
1532 */
1533 if (dispatch_width == 16 && brw->is_haswell) {
1534 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1535 brw_BFI1(p, dst, src[0], src[1]);
1536 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1537 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1538 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1539 } else {
1540 brw_BFI1(p, dst, src[0], src[1]);
1541 }
1542 break;
1543 case BRW_OPCODE_BFI2:
1544 assert(brw->gen >= 7);
1545 brw_set_default_access_mode(p, BRW_ALIGN_16);
1546 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1547 * should
1548 *
1549 * "Force BFI instructions to be executed always in SIMD8."
1550 *
1551 * Otherwise we would be able to emit compressed instructions like we
1552 * do for the other three-source instructions.
1553 */
1554 if (dispatch_width == 16) {
1555 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1556 brw_BFI2(p, dst, src[0], src[1], src[2]);
1557 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1558 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1559 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1560 } else {
1561 brw_BFI2(p, dst, src[0], src[1], src[2]);
1562 }
1563 brw_set_default_access_mode(p, BRW_ALIGN_1);
1564 break;
1565
1566 case BRW_OPCODE_IF:
1567 if (inst->src[0].file != BAD_FILE) {
1568 /* The instruction has an embedded compare (only allowed on gen6) */
1569 assert(brw->gen == 6);
1570 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1571 } else {
1572 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1573 }
1574 break;
1575
1576 case BRW_OPCODE_ELSE:
1577 brw_ELSE(p);
1578 break;
1579 case BRW_OPCODE_ENDIF:
1580 brw_ENDIF(p);
1581 break;
1582
1583 case BRW_OPCODE_DO:
1584 brw_DO(p, BRW_EXECUTE_8);
1585 break;
1586
1587 case BRW_OPCODE_BREAK:
1588 brw_BREAK(p);
1589 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1590 break;
1591 case BRW_OPCODE_CONTINUE:
1592 brw_CONT(p);
1593 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1594 break;
1595
1596 case BRW_OPCODE_WHILE:
1597 brw_WHILE(p);
1598 break;
1599
1600 case SHADER_OPCODE_RCP:
1601 case SHADER_OPCODE_RSQ:
1602 case SHADER_OPCODE_SQRT:
1603 case SHADER_OPCODE_EXP2:
1604 case SHADER_OPCODE_LOG2:
1605 case SHADER_OPCODE_SIN:
1606 case SHADER_OPCODE_COS:
1607 assert(brw->gen < 6 || inst->mlen == 0);
1608 if (brw->gen >= 7) {
1609 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1610 brw_null_reg());
1611 } else if (brw->gen == 6) {
1612 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1613 } else if (brw->gen == 5 || brw->is_g4x) {
1614 generate_math_g45(inst, dst, src[0]);
1615 } else {
1616 generate_math_gen4(inst, dst, src[0]);
1617 }
1618 break;
1619 case SHADER_OPCODE_INT_QUOTIENT:
1620 case SHADER_OPCODE_INT_REMAINDER:
1621 case SHADER_OPCODE_POW:
1622 assert(brw->gen < 6 || inst->mlen == 0);
1623 if (brw->gen >= 7) {
1624 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1625 } else if (brw->gen == 6) {
1626 generate_math_gen6(inst, dst, src[0], src[1]);
1627 } else {
1628 generate_math_gen4(inst, dst, src[0]);
1629 }
1630 break;
1631 case FS_OPCODE_PIXEL_X:
1632 generate_pixel_xy(dst, true);
1633 break;
1634 case FS_OPCODE_PIXEL_Y:
1635 generate_pixel_xy(dst, false);
1636 break;
1637 case FS_OPCODE_CINTERP:
1638 brw_MOV(p, dst, src[0]);
1639 break;
1640 case FS_OPCODE_LINTERP:
1641 generate_linterp(inst, dst, src);
1642 break;
1643 case SHADER_OPCODE_TEX:
1644 case FS_OPCODE_TXB:
1645 case SHADER_OPCODE_TXD:
1646 case SHADER_OPCODE_TXF:
1647 case SHADER_OPCODE_TXF_CMS:
1648 case SHADER_OPCODE_TXF_UMS:
1649 case SHADER_OPCODE_TXF_MCS:
1650 case SHADER_OPCODE_TXL:
1651 case SHADER_OPCODE_TXS:
1652 case SHADER_OPCODE_LOD:
1653 case SHADER_OPCODE_TG4:
1654 case SHADER_OPCODE_TG4_OFFSET:
1655 generate_tex(inst, dst, src[0], src[1]);
1656 break;
1657 case FS_OPCODE_DDX:
1658 generate_ddx(inst, dst, src[0]);
1659 break;
1660 case FS_OPCODE_DDY:
1661 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1662 * guarantee that key->render_to_fbo is set).
1663 */
1664 assert(fp->UsesDFdy);
1665 generate_ddy(inst, dst, src[0], key->render_to_fbo);
1666 break;
1667
1668 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1669 generate_scratch_write(inst, src[0]);
1670 break;
1671
1672 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1673 generate_scratch_read(inst, dst);
1674 break;
1675
1676 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1677 generate_scratch_read_gen7(inst, dst);
1678 break;
1679
1680 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1681 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1682 break;
1683
1684 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1685 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1686 break;
1687
1688 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1689 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1690 break;
1691
1692 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1693 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1694 break;
1695
1696 case FS_OPCODE_FB_WRITE:
1697 generate_fb_write(inst);
1698 break;
1699
1700 case FS_OPCODE_BLORP_FB_WRITE:
1701 generate_blorp_fb_write(inst);
1702 break;
1703
1704 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1705 generate_mov_dispatch_to_flags(inst);
1706 break;
1707
1708 case FS_OPCODE_DISCARD_JUMP:
1709 generate_discard_jump(inst);
1710 break;
1711
1712 case SHADER_OPCODE_SHADER_TIME_ADD:
1713 generate_shader_time_add(inst, src[0], src[1], src[2]);
1714 break;
1715
1716 case SHADER_OPCODE_UNTYPED_ATOMIC:
1717 generate_untyped_atomic(inst, dst, src[0], src[1]);
1718 break;
1719
1720 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1721 generate_untyped_surface_read(inst, dst, src[0]);
1722 break;
1723
1724 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1725 generate_set_simd4x2_offset(inst, dst, src[0]);
1726 break;
1727
1728 case FS_OPCODE_SET_OMASK:
1729 generate_set_omask(inst, dst, src[0]);
1730 break;
1731
1732 case FS_OPCODE_SET_SAMPLE_ID:
1733 generate_set_sample_id(inst, dst, src[0], src[1]);
1734 break;
1735
1736 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1737 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1738 break;
1739
1740 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1741 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1742 generate_unpack_half_2x16_split(inst, dst, src[0]);
1743 break;
1744
1745 case FS_OPCODE_PLACEHOLDER_HALT:
1746 /* This is the place where the final HALT needs to be inserted if
1747 * we've emitted any discards. If not, this will emit no code.
1748 */
1749 if (!patch_discard_jumps_to_fb_writes()) {
1750 if (unlikely(debug_flag)) {
1751 annotation.ann_count--;
1752 }
1753 }
1754 break;
1755
1756 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
1757 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1758 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
1759 break;
1760
1761 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
1762 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1763 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
1764 break;
1765
1766 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
1767 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1768 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
1769 break;
1770
1771 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
1772 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1773 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
1774 break;
1775
1776 default:
1777 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1778 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1779 opcode_descs[inst->opcode].name);
1780 } else {
1781 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1782 }
1783 abort();
1784
1785 case SHADER_OPCODE_LOAD_PAYLOAD:
1786 unreachable("Should be lowered by lower_load_payload()");
1787 }
1788
1789 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1790 assert(p->next_insn_offset == last_insn_offset + 16 ||
1791 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1792 "emitting more than 1 instruction");
1793
1794 brw_inst *last = &p->store[last_insn_offset / 16];
1795
1796 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
1797 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
1798 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
1799 }
1800 }
1801
1802 brw_set_uip_jip(p);
1803 annotation_finalize(&annotation, p->next_insn_offset);
1804
1805 int before_size = p->next_insn_offset - start_offset;
1806 brw_compact_instructions(p, start_offset, annotation.ann_count,
1807 annotation.ann);
1808 int after_size = p->next_insn_offset - start_offset;
1809
1810 if (unlikely(debug_flag)) {
1811 if (prog) {
1812 fprintf(stderr,
1813 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
1814 prog->Label ? prog->Label : "unnamed",
1815 prog->Name, dispatch_width);
1816 } else if (fp) {
1817 fprintf(stderr,
1818 "Native code for fragment program %d (SIMD%d dispatch):\n",
1819 fp->Base.Id, dispatch_width);
1820 } else {
1821 fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
1822 dispatch_width);
1823 }
1824 fprintf(stderr, "SIMD%d shader: %d instructions. Compacted %d to %d"
1825 " bytes (%.0f%%)\n",
1826 dispatch_width, before_size / 16, before_size, after_size,
1827 100.0f * (before_size - after_size) / before_size);
1828
1829 const struct gl_program *prog = fp ? &fp->Base : NULL;
1830
1831 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
1832 ralloc_free(annotation.ann);
1833 }
1834 }
1835
1836 const unsigned *
1837 fs_generator::generate_assembly(exec_list *simd8_instructions,
1838 exec_list *simd16_instructions,
1839 unsigned *assembly_size)
1840 {
1841 assert(simd8_instructions || simd16_instructions);
1842
1843 if (simd8_instructions) {
1844 dispatch_width = 8;
1845 generate_code(simd8_instructions);
1846 }
1847
1848 if (simd16_instructions) {
1849 /* align to 64 byte boundary. */
1850 while (p->next_insn_offset % 64) {
1851 brw_NOP(p);
1852 }
1853
1854 /* Save off the start of this SIMD16 program */
1855 prog_data->prog_offset_16 = p->next_insn_offset;
1856
1857 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1858
1859 dispatch_width = 16;
1860 generate_code(simd16_instructions);
1861 }
1862
1863 return brw_get_program(p, assembly_size);
1864 }