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i965/fs: Ensure delta_x/y are even-aligned registers on Gen6.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "main/macros.h"
31 #include "brw_context.h"
32 #include "brw_eu.h"
33 #include "brw_fs.h"
34 #include "brw_cfg.h"
35
36 static uint32_t brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case GRF:
40 return BRW_GENERAL_REGISTER_FILE;
41 case MRF:
42 return BRW_MESSAGE_REGISTER_FILE;
43 case IMM:
44 return BRW_IMMEDIATE_VALUE;
45 default:
46 unreachable("not reached");
47 }
48 }
49
50 static struct brw_reg
51 brw_reg_from_fs_reg(fs_reg *reg)
52 {
53 struct brw_reg brw_reg;
54
55 switch (reg->file) {
56 case GRF:
57 case MRF:
58 if (reg->stride == 0) {
59 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
60 } else if (reg->width < 8) {
61 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
62 brw_reg = stride(brw_reg, reg->width * reg->stride,
63 reg->width, reg->stride);
64 } else {
65 /* From the Haswell PRM:
66 *
67 * VertStride must be used to cross GRF register boundaries. This
68 * rule implies that elements within a 'Width' cannot cross GRF
69 * boundaries.
70 *
71 * So, for registers with width > 8, we have to use a width of 8
72 * and trust the compression state to sort out the exec size.
73 */
74 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
75 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
76 }
77
78 brw_reg = retype(brw_reg, reg->type);
79 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
80 break;
81 case IMM:
82 switch (reg->type) {
83 case BRW_REGISTER_TYPE_F:
84 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
85 break;
86 case BRW_REGISTER_TYPE_D:
87 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
88 break;
89 case BRW_REGISTER_TYPE_UD:
90 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
91 break;
92 case BRW_REGISTER_TYPE_W:
93 brw_reg = brw_imm_w(reg->fixed_hw_reg.dw1.d);
94 break;
95 case BRW_REGISTER_TYPE_UW:
96 brw_reg = brw_imm_uw(reg->fixed_hw_reg.dw1.ud);
97 break;
98 case BRW_REGISTER_TYPE_VF:
99 brw_reg = brw_imm_vf(reg->fixed_hw_reg.dw1.ud);
100 break;
101 default:
102 unreachable("not reached");
103 }
104 break;
105 case HW_REG:
106 assert(reg->type == reg->fixed_hw_reg.type);
107 brw_reg = reg->fixed_hw_reg;
108 break;
109 case BAD_FILE:
110 /* Probably unused. */
111 brw_reg = brw_null_reg();
112 break;
113 default:
114 unreachable("not reached");
115 }
116 if (reg->abs)
117 brw_reg = brw_abs(brw_reg);
118 if (reg->negate)
119 brw_reg = negate(brw_reg);
120
121 return brw_reg;
122 }
123
124 fs_generator::fs_generator(struct brw_context *brw,
125 void *mem_ctx,
126 const void *key,
127 struct brw_stage_prog_data *prog_data,
128 struct gl_program *prog,
129 unsigned promoted_constants,
130 bool runtime_check_aads_emit,
131 const char *stage_abbrev)
132
133 : brw(brw), key(key),
134 prog_data(prog_data),
135 prog(prog), promoted_constants(promoted_constants),
136 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
137 stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
138 {
139 ctx = &brw->ctx;
140
141 p = rzalloc(mem_ctx, struct brw_compile);
142 brw_init_compile(brw, p, mem_ctx);
143 }
144
145 fs_generator::~fs_generator()
146 {
147 }
148
149 class ip_record : public exec_node {
150 public:
151 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
152
153 ip_record(int ip)
154 {
155 this->ip = ip;
156 }
157
158 int ip;
159 };
160
161 bool
162 fs_generator::patch_discard_jumps_to_fb_writes()
163 {
164 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
165 return false;
166
167 int scale = brw_jump_scale(brw);
168
169 /* There is a somewhat strange undocumented requirement of using
170 * HALT, according to the simulator. If some channel has HALTed to
171 * a particular UIP, then by the end of the program, every channel
172 * must have HALTed to that UIP. Furthermore, the tracking is a
173 * stack, so you can't do the final halt of a UIP after starting
174 * halting to a new UIP.
175 *
176 * Symptoms of not emitting this instruction on actual hardware
177 * included GPU hangs and sparkly rendering on the piglit discard
178 * tests.
179 */
180 brw_inst *last_halt = gen6_HALT(p);
181 brw_inst_set_uip(brw, last_halt, 1 * scale);
182 brw_inst_set_jip(brw, last_halt, 1 * scale);
183
184 int ip = p->nr_insn;
185
186 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
187 brw_inst *patch = &p->store[patch_ip->ip];
188
189 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
190 /* HALT takes a half-instruction distance from the pre-incremented IP. */
191 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
192 }
193
194 this->discard_halt_patches.make_empty();
195 return true;
196 }
197
198 void
199 fs_generator::fire_fb_write(fs_inst *inst,
200 struct brw_reg payload,
201 struct brw_reg implied_header,
202 GLuint nr)
203 {
204 uint32_t msg_control;
205
206 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
207
208 if (brw->gen < 6) {
209 brw_push_insn_state(p);
210 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
211 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
212 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
213 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
214 brw_pop_insn_state(p);
215 }
216
217 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
218 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
219 else if (prog_data->dual_src_blend) {
220 if (dispatch_width == 8 || !inst->eot)
221 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
222 else
223 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
224 } else if (dispatch_width == 16)
225 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
226 else
227 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
228
229 uint32_t surf_index =
230 prog_data->binding_table.render_target_start + inst->target;
231
232 bool last_render_target = inst->eot ||
233 (prog_data->dual_src_blend && dispatch_width == 16);
234
235
236 brw_fb_WRITE(p,
237 dispatch_width,
238 payload,
239 implied_header,
240 msg_control,
241 surf_index,
242 nr,
243 0,
244 inst->eot,
245 last_render_target,
246 inst->header_present);
247
248 brw_mark_surface_used(&prog_data->base, surf_index);
249 }
250
251 void
252 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
253 {
254 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
255 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
256 struct brw_reg implied_header;
257
258 if (brw->gen < 8 && !brw->is_haswell) {
259 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
260 }
261
262 if (inst->base_mrf >= 0)
263 payload = brw_message_reg(inst->base_mrf);
264
265 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
266 * move, here's g1.
267 */
268 if (inst->header_present) {
269 brw_push_insn_state(p);
270 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
271 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
272 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
273 brw_set_default_flag_reg(p, 0, 0);
274
275 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
276 * present.
277 */
278 if (prog_data->uses_kill) {
279 struct brw_reg pixel_mask;
280
281 if (brw->gen >= 6)
282 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
283 else
284 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
285
286 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
287 }
288
289 if (brw->gen >= 6) {
290 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
291 brw_MOV(p,
292 retype(payload, BRW_REGISTER_TYPE_UD),
293 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
294 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
295
296 if (inst->target > 0 && key->replicate_alpha) {
297 /* Set "Source0 Alpha Present to RenderTarget" bit in message
298 * header.
299 */
300 brw_OR(p,
301 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
302 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
303 brw_imm_ud(0x1 << 11));
304 }
305
306 if (inst->target > 0) {
307 /* Set the render target index for choosing BLEND_STATE. */
308 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
309 BRW_REGISTER_TYPE_UD),
310 brw_imm_ud(inst->target));
311 }
312
313 implied_header = brw_null_reg();
314 } else {
315 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
316 }
317
318 brw_pop_insn_state(p);
319 } else {
320 implied_header = brw_null_reg();
321 }
322
323 if (!runtime_check_aads_emit) {
324 fire_fb_write(inst, payload, implied_header, inst->mlen);
325 } else {
326 /* This can only happen in gen < 6 */
327 assert(brw->gen < 6);
328
329 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
330
331 /* Check runtime bit to detect if we have to send AA data or not */
332 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
333 brw_AND(p,
334 v1_null_ud,
335 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
336 brw_imm_ud(1<<26));
337 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
338
339 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
340 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
341 {
342 /* Don't send AA data */
343 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
344 }
345 brw_land_fwd_jump(p, jmp);
346 fire_fb_write(inst, payload, implied_header, inst->mlen);
347 }
348 }
349
350 void
351 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
352 {
353 brw_inst *insn;
354
355 insn = brw_next_insn(p, BRW_OPCODE_SEND);
356
357 brw_set_dest(p, insn, brw_null_reg());
358 brw_set_src0(p, insn, payload);
359 brw_set_src1(p, insn, brw_imm_d(0));
360
361 brw_inst_set_sfid(brw, insn, BRW_SFID_URB);
362 brw_inst_set_urb_opcode(brw, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
363
364 brw_inst_set_mlen(brw, insn, inst->mlen);
365 brw_inst_set_rlen(brw, insn, 0);
366 brw_inst_set_eot(brw, insn, inst->eot);
367 brw_inst_set_header_present(brw, insn, true);
368 brw_inst_set_urb_global_offset(brw, insn, inst->offset);
369 }
370
371 void
372 fs_generator::generate_blorp_fb_write(fs_inst *inst)
373 {
374 brw_fb_WRITE(p,
375 16 /* dispatch_width */,
376 brw_message_reg(inst->base_mrf),
377 brw_reg_from_fs_reg(&inst->src[0]),
378 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
379 inst->target,
380 inst->mlen,
381 0,
382 true,
383 true,
384 inst->header_present);
385 }
386
387 /* Computes the integer pixel x,y values from the origin.
388 *
389 * This is the basis of gl_FragCoord computation, but is also used
390 * pre-gen6 for computing the deltas from v0 for computing
391 * interpolation.
392 */
393 void
394 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
395 {
396 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
397 struct brw_reg src;
398 struct brw_reg deltas;
399
400 if (is_x) {
401 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
402 deltas = brw_imm_v(0x10101010);
403 } else {
404 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
405 deltas = brw_imm_v(0x11001100);
406 }
407
408 if (dispatch_width == 16) {
409 dst = vec16(dst);
410 }
411
412 /* We do this SIMD8 or SIMD16, but since the destination is UW we
413 * don't do compression in the SIMD16 case.
414 */
415 brw_push_insn_state(p);
416 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
417 brw_ADD(p, dst, src, deltas);
418 brw_pop_insn_state(p);
419 }
420
421 void
422 fs_generator::generate_linterp(fs_inst *inst,
423 struct brw_reg dst, struct brw_reg *src)
424 {
425 struct brw_reg delta_x = src[0];
426 struct brw_reg delta_y = src[1];
427 struct brw_reg interp = src[2];
428
429 if (brw->has_pln &&
430 delta_y.nr == delta_x.nr + 1 &&
431 (brw->gen >= 7 || (delta_x.nr & 1) == 0)) {
432 brw_PLN(p, dst, interp, delta_x);
433 } else {
434 brw_LINE(p, brw_null_reg(), interp, delta_x);
435 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
436 }
437 }
438
439 void
440 fs_generator::generate_math_gen6(fs_inst *inst,
441 struct brw_reg dst,
442 struct brw_reg src0,
443 struct brw_reg src1)
444 {
445 int op = brw_math_function(inst->opcode);
446 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
447
448 if (dispatch_width == 8) {
449 gen6_math(p, dst, op, src0, src1);
450 } else if (dispatch_width == 16) {
451 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
452 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
453 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
454 gen6_math(p, sechalf(dst), op, sechalf(src0),
455 binop ? sechalf(src1) : brw_null_reg());
456 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
457 }
458 }
459
460 void
461 fs_generator::generate_math_gen4(fs_inst *inst,
462 struct brw_reg dst,
463 struct brw_reg src)
464 {
465 int op = brw_math_function(inst->opcode);
466
467 assert(inst->mlen >= 1);
468
469 if (dispatch_width == 8) {
470 gen4_math(p, dst,
471 op,
472 inst->base_mrf, src,
473 BRW_MATH_PRECISION_FULL);
474 } else if (dispatch_width == 16) {
475 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
476 gen4_math(p, firsthalf(dst),
477 op,
478 inst->base_mrf, firsthalf(src),
479 BRW_MATH_PRECISION_FULL);
480 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
481 gen4_math(p, sechalf(dst),
482 op,
483 inst->base_mrf + 1, sechalf(src),
484 BRW_MATH_PRECISION_FULL);
485
486 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
487 }
488 }
489
490 void
491 fs_generator::generate_math_g45(fs_inst *inst,
492 struct brw_reg dst,
493 struct brw_reg src)
494 {
495 if (inst->opcode == SHADER_OPCODE_POW ||
496 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
497 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
498 generate_math_gen4(inst, dst, src);
499 return;
500 }
501
502 int op = brw_math_function(inst->opcode);
503
504 assert(inst->mlen >= 1);
505
506 gen4_math(p, dst,
507 op,
508 inst->base_mrf, src,
509 BRW_MATH_PRECISION_FULL);
510 }
511
512 void
513 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
514 struct brw_reg sampler_index)
515 {
516 int msg_type = -1;
517 int rlen = 4;
518 uint32_t simd_mode;
519 uint32_t return_format;
520 bool is_combined_send = inst->eot;
521
522 switch (dst.type) {
523 case BRW_REGISTER_TYPE_D:
524 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
525 break;
526 case BRW_REGISTER_TYPE_UD:
527 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
528 break;
529 default:
530 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
531 break;
532 }
533
534 switch (inst->exec_size) {
535 case 8:
536 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
537 break;
538 case 16:
539 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
540 break;
541 default:
542 unreachable("Invalid width for texture instruction");
543 }
544
545 if (brw->gen >= 5) {
546 switch (inst->opcode) {
547 case SHADER_OPCODE_TEX:
548 if (inst->shadow_compare) {
549 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
550 } else {
551 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
552 }
553 break;
554 case FS_OPCODE_TXB:
555 if (inst->shadow_compare) {
556 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
557 } else {
558 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
559 }
560 break;
561 case SHADER_OPCODE_TXL:
562 if (inst->shadow_compare) {
563 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
564 } else {
565 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
566 }
567 break;
568 case SHADER_OPCODE_TXS:
569 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
570 break;
571 case SHADER_OPCODE_TXD:
572 if (inst->shadow_compare) {
573 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
574 assert(brw->gen >= 8 || brw->is_haswell);
575 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
576 } else {
577 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
578 }
579 break;
580 case SHADER_OPCODE_TXF:
581 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
582 break;
583 case SHADER_OPCODE_TXF_CMS:
584 if (brw->gen >= 7)
585 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
586 else
587 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
588 break;
589 case SHADER_OPCODE_TXF_UMS:
590 assert(brw->gen >= 7);
591 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
592 break;
593 case SHADER_OPCODE_TXF_MCS:
594 assert(brw->gen >= 7);
595 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
596 break;
597 case SHADER_OPCODE_LOD:
598 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
599 break;
600 case SHADER_OPCODE_TG4:
601 if (inst->shadow_compare) {
602 assert(brw->gen >= 7);
603 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
604 } else {
605 assert(brw->gen >= 6);
606 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
607 }
608 break;
609 case SHADER_OPCODE_TG4_OFFSET:
610 assert(brw->gen >= 7);
611 if (inst->shadow_compare) {
612 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
613 } else {
614 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
615 }
616 break;
617 default:
618 unreachable("not reached");
619 }
620 } else {
621 switch (inst->opcode) {
622 case SHADER_OPCODE_TEX:
623 /* Note that G45 and older determines shadow compare and dispatch width
624 * from message length for most messages.
625 */
626 if (dispatch_width == 8) {
627 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
628 if (inst->shadow_compare) {
629 assert(inst->mlen == 6);
630 } else {
631 assert(inst->mlen <= 4);
632 }
633 } else {
634 if (inst->shadow_compare) {
635 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
636 assert(inst->mlen == 9);
637 } else {
638 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
639 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
640 }
641 }
642 break;
643 case FS_OPCODE_TXB:
644 if (inst->shadow_compare) {
645 assert(dispatch_width == 8);
646 assert(inst->mlen == 6);
647 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
648 } else {
649 assert(inst->mlen == 9);
650 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
651 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
652 }
653 break;
654 case SHADER_OPCODE_TXL:
655 if (inst->shadow_compare) {
656 assert(dispatch_width == 8);
657 assert(inst->mlen == 6);
658 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
659 } else {
660 assert(inst->mlen == 9);
661 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
662 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
663 }
664 break;
665 case SHADER_OPCODE_TXD:
666 /* There is no sample_d_c message; comparisons are done manually */
667 assert(dispatch_width == 8);
668 assert(inst->mlen == 7 || inst->mlen == 10);
669 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
670 break;
671 case SHADER_OPCODE_TXF:
672 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
673 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
674 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
675 break;
676 case SHADER_OPCODE_TXS:
677 assert(inst->mlen == 3);
678 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
679 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
680 break;
681 default:
682 unreachable("not reached");
683 }
684 }
685 assert(msg_type != -1);
686
687 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
688 rlen = 8;
689 dst = vec16(dst);
690 }
691
692 if (is_combined_send) {
693 assert(brw->gen >= 9 || brw->is_cherryview);
694 rlen = 0;
695 }
696
697 assert(brw->gen < 7 || !inst->header_present ||
698 src.file == BRW_GENERAL_REGISTER_FILE);
699
700 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
701
702 /* Load the message header if present. If there's a texture offset,
703 * we need to set it up explicitly and load the offset bitfield.
704 * Otherwise, we can use an implied move from g0 to the first message reg.
705 */
706 if (inst->header_present) {
707 if (brw->gen < 6 && !inst->offset) {
708 /* Set up an implied move from g0 to the MRF. */
709 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
710 } else {
711 struct brw_reg header_reg;
712
713 if (brw->gen >= 7) {
714 header_reg = src;
715 } else {
716 assert(inst->base_mrf != -1);
717 header_reg = brw_message_reg(inst->base_mrf);
718 }
719
720 brw_push_insn_state(p);
721 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
722 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
723 /* Explicitly set up the message header by copying g0 to the MRF. */
724 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
725
726 if (inst->offset) {
727 /* Set the offset bits in DWord 2. */
728 brw_MOV(p, get_element_ud(header_reg, 2),
729 brw_imm_ud(inst->offset));
730 }
731
732 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
733 brw_pop_insn_state(p);
734 }
735 }
736
737 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
738 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
739 ? prog_data->binding_table.gather_texture_start
740 : prog_data->binding_table.texture_start;
741
742 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
743 uint32_t sampler = sampler_index.dw1.ud;
744
745 brw_SAMPLE(p,
746 retype(dst, BRW_REGISTER_TYPE_UW),
747 inst->base_mrf,
748 src,
749 sampler + base_binding_table_index,
750 sampler % 16,
751 msg_type,
752 rlen,
753 inst->mlen,
754 inst->header_present,
755 simd_mode,
756 return_format);
757
758 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
759 } else {
760 /* Non-const sampler index */
761 /* Note: this clobbers `dst` as a temporary before emitting the send */
762
763 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
764 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
765
766 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
767
768 brw_push_insn_state(p);
769 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
770 brw_set_default_access_mode(p, BRW_ALIGN_1);
771
772 /* Some care required: `sampler` and `temp` may alias:
773 * addr = sampler & 0xff
774 * temp = (sampler << 8) & 0xf00
775 * addr = addr | temp
776 */
777 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
778 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
779 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
780 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
781 brw_OR(p, addr, addr, temp);
782
783 brw_pop_insn_state(p);
784
785 /* dst = send(offset, a0.0 | <descriptor>) */
786 brw_inst *insn = brw_send_indirect_message(
787 p, BRW_SFID_SAMPLER, dst, src, addr);
788 brw_set_sampler_message(p, insn,
789 0 /* surface */,
790 0 /* sampler */,
791 msg_type,
792 rlen,
793 inst->mlen /* mlen */,
794 inst->header_present /* header */,
795 simd_mode,
796 return_format);
797
798 /* visitor knows more than we do about the surface limit required,
799 * so has already done marking.
800 */
801 }
802
803 if (is_combined_send) {
804 brw_inst_set_eot(brw, brw_last_inst, true);
805 brw_inst_set_opcode(brw, brw_last_inst, BRW_OPCODE_SENDC);
806 }
807 }
808
809
810 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
811 * looking like:
812 *
813 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
814 *
815 * Ideally, we want to produce:
816 *
817 * DDX DDY
818 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
819 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
820 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
821 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
822 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
823 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
824 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
825 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
826 *
827 * and add another set of two more subspans if in 16-pixel dispatch mode.
828 *
829 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
830 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
831 * pair. But the ideal approximation may impose a huge performance cost on
832 * sample_d. On at least Haswell, sample_d instruction does some
833 * optimizations if the same LOD is used for all pixels in the subspan.
834 *
835 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
836 * appropriate swizzling.
837 */
838 void
839 fs_generator::generate_ddx(enum opcode opcode,
840 struct brw_reg dst, struct brw_reg src)
841 {
842 unsigned vstride, width;
843
844 if (opcode == FS_OPCODE_DDX_FINE) {
845 /* produce accurate derivatives */
846 vstride = BRW_VERTICAL_STRIDE_2;
847 width = BRW_WIDTH_2;
848 } else {
849 /* replicate the derivative at the top-left pixel to other pixels */
850 vstride = BRW_VERTICAL_STRIDE_4;
851 width = BRW_WIDTH_4;
852 }
853
854 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
855 src.negate, src.abs,
856 BRW_REGISTER_TYPE_F,
857 vstride,
858 width,
859 BRW_HORIZONTAL_STRIDE_0,
860 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
861 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
862 src.negate, src.abs,
863 BRW_REGISTER_TYPE_F,
864 vstride,
865 width,
866 BRW_HORIZONTAL_STRIDE_0,
867 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
868 brw_ADD(p, dst, src0, negate(src1));
869 }
870
871 /* The negate_value boolean is used to negate the derivative computation for
872 * FBOs, since they place the origin at the upper left instead of the lower
873 * left.
874 */
875 void
876 fs_generator::generate_ddy(enum opcode opcode,
877 struct brw_reg dst, struct brw_reg src,
878 bool negate_value)
879 {
880 if (opcode == FS_OPCODE_DDY_FINE) {
881 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
882 * Region Restrictions):
883 *
884 * In Align16 access mode, SIMD16 is not allowed for DW operations
885 * and SIMD8 is not allowed for DF operations.
886 *
887 * In this context, "DW operations" means "operations acting on 32-bit
888 * values", so it includes operations on floats.
889 *
890 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
891 * (Instruction Compression -> Rules and Restrictions):
892 *
893 * A compressed instruction must be in Align1 access mode. Align16
894 * mode instructions cannot be compressed.
895 *
896 * Similar text exists in the g45 PRM.
897 *
898 * On these platforms, if we're building a SIMD16 shader, we need to
899 * manually unroll to a pair of SIMD8 instructions.
900 */
901 bool unroll_to_simd8 =
902 (dispatch_width == 16 &&
903 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
904
905 /* produce accurate derivatives */
906 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
907 src.negate, src.abs,
908 BRW_REGISTER_TYPE_F,
909 BRW_VERTICAL_STRIDE_4,
910 BRW_WIDTH_4,
911 BRW_HORIZONTAL_STRIDE_1,
912 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
913 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
914 src.negate, src.abs,
915 BRW_REGISTER_TYPE_F,
916 BRW_VERTICAL_STRIDE_4,
917 BRW_WIDTH_4,
918 BRW_HORIZONTAL_STRIDE_1,
919 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
920 brw_push_insn_state(p);
921 brw_set_default_access_mode(p, BRW_ALIGN_16);
922 if (unroll_to_simd8) {
923 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
924 if (negate_value) {
925 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
926 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
927 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
928 } else {
929 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
930 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
931 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
932 }
933 } else {
934 if (negate_value)
935 brw_ADD(p, dst, src1, negate(src0));
936 else
937 brw_ADD(p, dst, src0, negate(src1));
938 }
939 brw_pop_insn_state(p);
940 } else {
941 /* replicate the derivative at the top-left pixel to other pixels */
942 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
943 src.negate, src.abs,
944 BRW_REGISTER_TYPE_F,
945 BRW_VERTICAL_STRIDE_4,
946 BRW_WIDTH_4,
947 BRW_HORIZONTAL_STRIDE_0,
948 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
949 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
950 src.negate, src.abs,
951 BRW_REGISTER_TYPE_F,
952 BRW_VERTICAL_STRIDE_4,
953 BRW_WIDTH_4,
954 BRW_HORIZONTAL_STRIDE_0,
955 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
956 if (negate_value)
957 brw_ADD(p, dst, src1, negate(src0));
958 else
959 brw_ADD(p, dst, src0, negate(src1));
960 }
961 }
962
963 void
964 fs_generator::generate_discard_jump(fs_inst *inst)
965 {
966 assert(brw->gen >= 6);
967
968 /* This HALT will be patched up at FB write time to point UIP at the end of
969 * the program, and at brw_uip_jip() JIP will be set to the end of the
970 * current block (or the program).
971 */
972 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
973
974 brw_push_insn_state(p);
975 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
976 gen6_HALT(p);
977 brw_pop_insn_state(p);
978 }
979
980 void
981 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
982 {
983 assert(inst->mlen != 0);
984
985 brw_MOV(p,
986 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
987 retype(src, BRW_REGISTER_TYPE_UD));
988 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
989 inst->exec_size / 8, inst->offset);
990 }
991
992 void
993 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
994 {
995 assert(inst->mlen != 0);
996
997 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
998 inst->exec_size / 8, inst->offset);
999 }
1000
1001 void
1002 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1003 {
1004 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1005 }
1006
1007 void
1008 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1009 struct brw_reg dst,
1010 struct brw_reg index,
1011 struct brw_reg offset)
1012 {
1013 assert(inst->mlen != 0);
1014
1015 assert(index.file == BRW_IMMEDIATE_VALUE &&
1016 index.type == BRW_REGISTER_TYPE_UD);
1017 uint32_t surf_index = index.dw1.ud;
1018
1019 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1020 offset.type == BRW_REGISTER_TYPE_UD);
1021 uint32_t read_offset = offset.dw1.ud;
1022
1023 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1024 read_offset, surf_index);
1025
1026 brw_mark_surface_used(prog_data, surf_index);
1027 }
1028
1029 void
1030 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1031 struct brw_reg dst,
1032 struct brw_reg index,
1033 struct brw_reg offset)
1034 {
1035 assert(inst->mlen == 0);
1036 assert(index.type == BRW_REGISTER_TYPE_UD);
1037
1038 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1039 /* Reference just the dword we need, to avoid angering validate_reg(). */
1040 offset = brw_vec1_grf(offset.nr, 0);
1041
1042 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1043 * the destination loaded consecutively from the same offset (which appears
1044 * in the first component, and the rest are ignored).
1045 */
1046 dst.width = BRW_WIDTH_4;
1047
1048 struct brw_reg src = offset;
1049 bool header_present = false;
1050 int mlen = 1;
1051
1052 if (brw->gen >= 9) {
1053 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1054 src = retype(brw_vec4_grf(offset.nr - 1, 0), BRW_REGISTER_TYPE_UD);
1055 mlen = 2;
1056 header_present = true;
1057
1058 brw_push_insn_state(p);
1059 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1060 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1061 brw_set_default_access_mode(p, BRW_ALIGN_1);
1062
1063 brw_MOV(p, get_element_ud(src, 2),
1064 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1065 brw_pop_insn_state(p);
1066 }
1067
1068 if (index.file == BRW_IMMEDIATE_VALUE) {
1069
1070 uint32_t surf_index = index.dw1.ud;
1071
1072 brw_push_insn_state(p);
1073 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1074 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1075 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1076 brw_pop_insn_state(p);
1077
1078 brw_set_dest(p, send, dst);
1079 brw_set_src0(p, send, src);
1080 brw_set_sampler_message(p, send,
1081 surf_index,
1082 0, /* LD message ignores sampler unit */
1083 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1084 1, /* rlen */
1085 mlen,
1086 header_present,
1087 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1088 0);
1089
1090 brw_mark_surface_used(prog_data, surf_index);
1091
1092 } else {
1093
1094 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1095
1096 brw_push_insn_state(p);
1097 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1098 brw_set_default_access_mode(p, BRW_ALIGN_1);
1099
1100 /* a0.0 = surf_index & 0xff */
1101 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1102 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1103 brw_set_dest(p, insn_and, addr);
1104 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1105 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1106
1107 /* dst = send(payload, a0.0 | <descriptor>) */
1108 brw_inst *insn = brw_send_indirect_message(
1109 p, BRW_SFID_SAMPLER, dst, src, addr);
1110 brw_set_sampler_message(p, insn,
1111 0,
1112 0, /* LD message ignores sampler unit */
1113 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1114 1, /* rlen */
1115 mlen,
1116 header_present,
1117 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1118 0);
1119
1120 brw_pop_insn_state(p);
1121
1122 /* visitor knows more than we do about the surface limit required,
1123 * so has already done marking.
1124 */
1125
1126 }
1127 }
1128
1129 void
1130 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1131 struct brw_reg dst,
1132 struct brw_reg index,
1133 struct brw_reg offset)
1134 {
1135 assert(brw->gen < 7); /* Should use the gen7 variant. */
1136 assert(inst->header_present);
1137 assert(inst->mlen);
1138
1139 assert(index.file == BRW_IMMEDIATE_VALUE &&
1140 index.type == BRW_REGISTER_TYPE_UD);
1141 uint32_t surf_index = index.dw1.ud;
1142
1143 uint32_t simd_mode, rlen, msg_type;
1144 if (dispatch_width == 16) {
1145 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1146 rlen = 8;
1147 } else {
1148 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1149 rlen = 4;
1150 }
1151
1152 if (brw->gen >= 5)
1153 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1154 else {
1155 /* We always use the SIMD16 message so that we only have to load U, and
1156 * not V or R.
1157 */
1158 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1159 assert(inst->mlen == 3);
1160 assert(inst->regs_written == 8);
1161 rlen = 8;
1162 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1163 }
1164
1165 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1166 BRW_REGISTER_TYPE_D);
1167 brw_MOV(p, offset_mrf, offset);
1168
1169 struct brw_reg header = brw_vec8_grf(0, 0);
1170 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1171
1172 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1173 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
1174 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1175 brw_set_src0(p, send, header);
1176 if (brw->gen < 6)
1177 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
1178
1179 /* Our surface is set up as floats, regardless of what actual data is
1180 * stored in it.
1181 */
1182 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1183 brw_set_sampler_message(p, send,
1184 surf_index,
1185 0, /* sampler (unused) */
1186 msg_type,
1187 rlen,
1188 inst->mlen,
1189 inst->header_present,
1190 simd_mode,
1191 return_format);
1192
1193 brw_mark_surface_used(prog_data, surf_index);
1194 }
1195
1196 void
1197 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1198 struct brw_reg dst,
1199 struct brw_reg index,
1200 struct brw_reg offset)
1201 {
1202 assert(brw->gen >= 7);
1203 /* Varying-offset pull constant loads are treated as a normal expression on
1204 * gen7, so the fact that it's a send message is hidden at the IR level.
1205 */
1206 assert(!inst->header_present);
1207 assert(!inst->mlen);
1208 assert(index.type == BRW_REGISTER_TYPE_UD);
1209
1210 uint32_t simd_mode, rlen, mlen;
1211 if (dispatch_width == 16) {
1212 mlen = 2;
1213 rlen = 8;
1214 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1215 } else {
1216 mlen = 1;
1217 rlen = 4;
1218 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1219 }
1220
1221 if (index.file == BRW_IMMEDIATE_VALUE) {
1222
1223 uint32_t surf_index = index.dw1.ud;
1224
1225 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1226 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1227 brw_set_src0(p, send, offset);
1228 brw_set_sampler_message(p, send,
1229 surf_index,
1230 0, /* LD message ignores sampler unit */
1231 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1232 rlen,
1233 mlen,
1234 false, /* no header */
1235 simd_mode,
1236 0);
1237
1238 brw_mark_surface_used(prog_data, surf_index);
1239
1240 } else {
1241
1242 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1243
1244 brw_push_insn_state(p);
1245 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1246 brw_set_default_access_mode(p, BRW_ALIGN_1);
1247
1248 /* a0.0 = surf_index & 0xff */
1249 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1250 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1251 brw_set_dest(p, insn_and, addr);
1252 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1253 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1254
1255 brw_pop_insn_state(p);
1256
1257 /* dst = send(offset, a0.0 | <descriptor>) */
1258 brw_inst *insn = brw_send_indirect_message(
1259 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1260 offset, addr);
1261 brw_set_sampler_message(p, insn,
1262 0 /* surface */,
1263 0 /* sampler */,
1264 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1265 rlen /* rlen */,
1266 mlen /* mlen */,
1267 false /* header */,
1268 simd_mode,
1269 0);
1270
1271 /* visitor knows more than we do about the surface limit required,
1272 * so has already done marking.
1273 */
1274 }
1275 }
1276
1277 /**
1278 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1279 * into the flags register (f0.0).
1280 *
1281 * Used only on Gen6 and above.
1282 */
1283 void
1284 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1285 {
1286 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1287 struct brw_reg dispatch_mask;
1288
1289 if (brw->gen >= 6)
1290 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1291 else
1292 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1293
1294 brw_push_insn_state(p);
1295 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1296 brw_MOV(p, flags, dispatch_mask);
1297 brw_pop_insn_state(p);
1298 }
1299
1300 void
1301 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1302 struct brw_reg dst,
1303 struct brw_reg src,
1304 struct brw_reg msg_data,
1305 unsigned msg_type)
1306 {
1307 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1308 msg_data.type == BRW_REGISTER_TYPE_UD);
1309
1310 brw_pixel_interpolator_query(p,
1311 retype(dst, BRW_REGISTER_TYPE_UW),
1312 src,
1313 inst->pi_noperspective,
1314 msg_type,
1315 msg_data.dw1.ud,
1316 inst->mlen,
1317 inst->regs_written);
1318 }
1319
1320
1321 /**
1322 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1323 * sampler LD messages.
1324 *
1325 * We don't want to bake it into the send message's code generation because
1326 * that means we don't get a chance to schedule the instructions.
1327 */
1328 void
1329 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1330 struct brw_reg dst,
1331 struct brw_reg value)
1332 {
1333 assert(value.file == BRW_IMMEDIATE_VALUE);
1334
1335 brw_push_insn_state(p);
1336 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1337 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1338 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1339 brw_pop_insn_state(p);
1340 }
1341
1342 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1343 * (when mask is passed as a uniform) of register mask before moving it
1344 * to register dst.
1345 */
1346 void
1347 fs_generator::generate_set_omask(fs_inst *inst,
1348 struct brw_reg dst,
1349 struct brw_reg mask)
1350 {
1351 bool stride_8_8_1 =
1352 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1353 mask.width == BRW_WIDTH_8 &&
1354 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1355
1356 bool stride_0_1_0 = has_scalar_region(mask);
1357
1358 assert(stride_8_8_1 || stride_0_1_0);
1359 assert(dst.type == BRW_REGISTER_TYPE_UW);
1360
1361 if (dispatch_width == 16)
1362 dst = vec16(dst);
1363 brw_push_insn_state(p);
1364 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1365 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1366
1367 if (stride_8_8_1) {
1368 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1369 } else if (stride_0_1_0) {
1370 brw_MOV(p, dst, retype(mask, dst.type));
1371 }
1372 brw_pop_insn_state(p);
1373 }
1374
1375 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1376 * the ADD instruction.
1377 */
1378 void
1379 fs_generator::generate_set_sample_id(fs_inst *inst,
1380 struct brw_reg dst,
1381 struct brw_reg src0,
1382 struct brw_reg src1)
1383 {
1384 assert(dst.type == BRW_REGISTER_TYPE_D ||
1385 dst.type == BRW_REGISTER_TYPE_UD);
1386 assert(src0.type == BRW_REGISTER_TYPE_D ||
1387 src0.type == BRW_REGISTER_TYPE_UD);
1388
1389 brw_push_insn_state(p);
1390 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1391 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1392 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1393 if (dispatch_width == 8) {
1394 brw_ADD(p, dst, src0, reg);
1395 } else if (dispatch_width == 16) {
1396 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1397 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1398 }
1399 brw_pop_insn_state(p);
1400 }
1401
1402 void
1403 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1404 struct brw_reg dst,
1405 struct brw_reg x,
1406 struct brw_reg y)
1407 {
1408 assert(brw->gen >= 7);
1409 assert(dst.type == BRW_REGISTER_TYPE_UD);
1410 assert(x.type == BRW_REGISTER_TYPE_F);
1411 assert(y.type == BRW_REGISTER_TYPE_F);
1412
1413 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1414 *
1415 * Because this instruction does not have a 16-bit floating-point type,
1416 * the destination data type must be Word (W).
1417 *
1418 * The destination must be DWord-aligned and specify a horizontal stride
1419 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1420 * each destination channel and the upper word is not modified.
1421 */
1422 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1423
1424 /* Give each 32-bit channel of dst the form below, where "." means
1425 * unchanged.
1426 * 0x....hhhh
1427 */
1428 brw_F32TO16(p, dst_w, y);
1429
1430 /* Now the form:
1431 * 0xhhhh0000
1432 */
1433 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1434
1435 /* And, finally the form of packHalf2x16's output:
1436 * 0xhhhhllll
1437 */
1438 brw_F32TO16(p, dst_w, x);
1439 }
1440
1441 void
1442 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1443 struct brw_reg dst,
1444 struct brw_reg src)
1445 {
1446 assert(brw->gen >= 7);
1447 assert(dst.type == BRW_REGISTER_TYPE_F);
1448 assert(src.type == BRW_REGISTER_TYPE_UD);
1449
1450 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1451 *
1452 * Because this instruction does not have a 16-bit floating-point type,
1453 * the source data type must be Word (W). The destination type must be
1454 * F (Float).
1455 */
1456 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1457
1458 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1459 * For the Y case, we wish to access only the upper word; therefore
1460 * a 16-bit subregister offset is needed.
1461 */
1462 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1463 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1464 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1465 src_w.subnr += 2;
1466
1467 brw_F16TO32(p, dst, src_w);
1468 }
1469
1470 void
1471 fs_generator::generate_shader_time_add(fs_inst *inst,
1472 struct brw_reg payload,
1473 struct brw_reg offset,
1474 struct brw_reg value)
1475 {
1476 assert(brw->gen >= 7);
1477 brw_push_insn_state(p);
1478 brw_set_default_mask_control(p, true);
1479
1480 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1481 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1482 offset.type);
1483 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1484 value.type);
1485
1486 assert(offset.file == BRW_IMMEDIATE_VALUE);
1487 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1488 value.width = BRW_WIDTH_1;
1489 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1490 value.vstride = BRW_VERTICAL_STRIDE_0;
1491 } else {
1492 assert(value.file == BRW_IMMEDIATE_VALUE);
1493 }
1494
1495 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1496 * case, and we don't really care about squeezing every bit of performance
1497 * out of this path, so we just emit the MOVs from here.
1498 */
1499 brw_MOV(p, payload_offset, offset);
1500 brw_MOV(p, payload_value, value);
1501 brw_shader_time_add(p, payload,
1502 prog_data->binding_table.shader_time_start);
1503 brw_pop_insn_state(p);
1504
1505 brw_mark_surface_used(prog_data,
1506 prog_data->binding_table.shader_time_start);
1507 }
1508
1509 void
1510 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1511 struct brw_reg payload,
1512 struct brw_reg atomic_op,
1513 struct brw_reg surf_index)
1514 {
1515 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1516 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1517 surf_index.file == BRW_IMMEDIATE_VALUE &&
1518 surf_index.type == BRW_REGISTER_TYPE_UD);
1519
1520 brw_untyped_atomic(p, dst, payload,
1521 atomic_op.dw1.ud, surf_index.dw1.ud,
1522 inst->mlen, true);
1523
1524 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1525 }
1526
1527 void
1528 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1529 struct brw_reg payload,
1530 struct brw_reg surf_index)
1531 {
1532 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1533 surf_index.type == BRW_REGISTER_TYPE_UD);
1534
1535 brw_untyped_surface_read(p, dst, payload, surf_index.dw1.ud, inst->mlen, 1);
1536
1537 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1538 }
1539
1540 void
1541 fs_generator::enable_debug(const char *shader_name)
1542 {
1543 debug_flag = true;
1544 this->shader_name = shader_name;
1545 }
1546
1547 /**
1548 * Some hardware doesn't support SIMD16 instructions with 3 sources.
1549 */
1550 static bool
1551 brw_supports_simd16_3src(const struct brw_context *brw)
1552 {
1553 /* WaDisableSIMD16On3SrcInstr: 3-source instructions don't work in SIMD16
1554 * on a few steppings of Skylake.
1555 */
1556 if (brw->gen == 9)
1557 return brw->revision != 2 && brw->revision != 3 && brw->revision != -1;
1558
1559 return brw->is_haswell || brw->gen >= 8;
1560 }
1561
1562 int
1563 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1564 {
1565 /* align to 64 byte boundary. */
1566 while (p->next_insn_offset % 64)
1567 brw_NOP(p);
1568
1569 this->dispatch_width = dispatch_width;
1570 if (dispatch_width == 16)
1571 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1572
1573 int start_offset = p->next_insn_offset;
1574 int spill_count = 0, fill_count = 0;
1575 int loop_count = 0;
1576
1577 struct annotation_info annotation;
1578 memset(&annotation, 0, sizeof(annotation));
1579
1580 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1581 struct brw_reg src[3], dst;
1582 unsigned int last_insn_offset = p->next_insn_offset;
1583 bool multiple_instructions_emitted = false;
1584
1585 if (unlikely(debug_flag))
1586 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1587
1588 for (unsigned int i = 0; i < inst->sources; i++) {
1589 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1590
1591 /* The accumulator result appears to get used for the
1592 * conditional modifier generation. When negating a UD
1593 * value, there is a 33rd bit generated for the sign in the
1594 * accumulator value, so now you can't check, for example,
1595 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1596 */
1597 assert(!inst->conditional_mod ||
1598 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1599 !inst->src[i].negate);
1600 }
1601 dst = brw_reg_from_fs_reg(&inst->dst);
1602
1603 brw_set_default_predicate_control(p, inst->predicate);
1604 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1605 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1606 brw_set_default_saturate(p, inst->saturate);
1607 brw_set_default_mask_control(p, inst->force_writemask_all);
1608 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1609
1610 switch (inst->exec_size) {
1611 case 1:
1612 case 2:
1613 case 4:
1614 assert(inst->force_writemask_all);
1615 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1616 break;
1617 case 8:
1618 if (inst->force_sechalf) {
1619 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1620 } else {
1621 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1622 }
1623 break;
1624 case 16:
1625 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1626 break;
1627 default:
1628 unreachable("Invalid instruction width");
1629 }
1630
1631 switch (inst->opcode) {
1632 case BRW_OPCODE_MOV:
1633 brw_MOV(p, dst, src[0]);
1634 break;
1635 case BRW_OPCODE_ADD:
1636 brw_ADD(p, dst, src[0], src[1]);
1637 break;
1638 case BRW_OPCODE_MUL:
1639 brw_MUL(p, dst, src[0], src[1]);
1640 break;
1641 case BRW_OPCODE_AVG:
1642 brw_AVG(p, dst, src[0], src[1]);
1643 break;
1644 case BRW_OPCODE_MACH:
1645 brw_MACH(p, dst, src[0], src[1]);
1646 break;
1647
1648 case BRW_OPCODE_LINE:
1649 brw_LINE(p, dst, src[0], src[1]);
1650 break;
1651
1652 case BRW_OPCODE_MAD:
1653 assert(brw->gen >= 6);
1654 brw_set_default_access_mode(p, BRW_ALIGN_16);
1655 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1656 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1657 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1658 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1659 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1660 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1661
1662 if (inst->conditional_mod) {
1663 brw_inst_set_cond_modifier(brw, f, inst->conditional_mod);
1664 brw_inst_set_cond_modifier(brw, s, inst->conditional_mod);
1665 multiple_instructions_emitted = true;
1666 }
1667 } else {
1668 brw_MAD(p, dst, src[0], src[1], src[2]);
1669 }
1670 brw_set_default_access_mode(p, BRW_ALIGN_1);
1671 break;
1672
1673 case BRW_OPCODE_LRP:
1674 assert(brw->gen >= 6);
1675 brw_set_default_access_mode(p, BRW_ALIGN_16);
1676 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1677 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1678 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1679 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1680 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1681 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1682
1683 if (inst->conditional_mod) {
1684 brw_inst_set_cond_modifier(brw, f, inst->conditional_mod);
1685 brw_inst_set_cond_modifier(brw, s, inst->conditional_mod);
1686 multiple_instructions_emitted = true;
1687 }
1688 } else {
1689 brw_LRP(p, dst, src[0], src[1], src[2]);
1690 }
1691 brw_set_default_access_mode(p, BRW_ALIGN_1);
1692 break;
1693
1694 case BRW_OPCODE_FRC:
1695 brw_FRC(p, dst, src[0]);
1696 break;
1697 case BRW_OPCODE_RNDD:
1698 brw_RNDD(p, dst, src[0]);
1699 break;
1700 case BRW_OPCODE_RNDE:
1701 brw_RNDE(p, dst, src[0]);
1702 break;
1703 case BRW_OPCODE_RNDZ:
1704 brw_RNDZ(p, dst, src[0]);
1705 break;
1706
1707 case BRW_OPCODE_AND:
1708 brw_AND(p, dst, src[0], src[1]);
1709 break;
1710 case BRW_OPCODE_OR:
1711 brw_OR(p, dst, src[0], src[1]);
1712 break;
1713 case BRW_OPCODE_XOR:
1714 brw_XOR(p, dst, src[0], src[1]);
1715 break;
1716 case BRW_OPCODE_NOT:
1717 brw_NOT(p, dst, src[0]);
1718 break;
1719 case BRW_OPCODE_ASR:
1720 brw_ASR(p, dst, src[0], src[1]);
1721 break;
1722 case BRW_OPCODE_SHR:
1723 brw_SHR(p, dst, src[0], src[1]);
1724 break;
1725 case BRW_OPCODE_SHL:
1726 brw_SHL(p, dst, src[0], src[1]);
1727 break;
1728 case BRW_OPCODE_F32TO16:
1729 assert(brw->gen >= 7);
1730 brw_F32TO16(p, dst, src[0]);
1731 break;
1732 case BRW_OPCODE_F16TO32:
1733 assert(brw->gen >= 7);
1734 brw_F16TO32(p, dst, src[0]);
1735 break;
1736 case BRW_OPCODE_CMP:
1737 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1738 * that when the destination is a GRF that the dependency-clear bit on
1739 * the flag register is cleared early.
1740 *
1741 * Suggested workarounds are to disable coissuing CMP instructions
1742 * or to split CMP(16) instructions into two CMP(8) instructions.
1743 *
1744 * We choose to split into CMP(8) instructions since disabling
1745 * coissuing would affect CMP instructions not otherwise affected by
1746 * the errata.
1747 */
1748 if (dispatch_width == 16 && brw->gen == 7 && !brw->is_haswell) {
1749 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1750 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1751 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1752 firsthalf(src[0]), firsthalf(src[1]));
1753 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1754 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1755 sechalf(src[0]), sechalf(src[1]));
1756 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1757
1758 multiple_instructions_emitted = true;
1759 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1760 /* For unknown reasons, the aforementioned workaround is not
1761 * sufficient. Overriding the type when the destination is the
1762 * null register is necessary but not sufficient by itself.
1763 */
1764 assert(dst.nr == BRW_ARF_NULL);
1765 dst.type = BRW_REGISTER_TYPE_D;
1766 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1767 } else {
1768 unreachable("not reached");
1769 }
1770 } else {
1771 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1772 }
1773 break;
1774 case BRW_OPCODE_SEL:
1775 brw_SEL(p, dst, src[0], src[1]);
1776 break;
1777 case BRW_OPCODE_BFREV:
1778 assert(brw->gen >= 7);
1779 /* BFREV only supports UD type for src and dst. */
1780 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1781 retype(src[0], BRW_REGISTER_TYPE_UD));
1782 break;
1783 case BRW_OPCODE_FBH:
1784 assert(brw->gen >= 7);
1785 /* FBH only supports UD type for dst. */
1786 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1787 break;
1788 case BRW_OPCODE_FBL:
1789 assert(brw->gen >= 7);
1790 /* FBL only supports UD type for dst. */
1791 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1792 break;
1793 case BRW_OPCODE_CBIT:
1794 assert(brw->gen >= 7);
1795 /* CBIT only supports UD type for dst. */
1796 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1797 break;
1798 case BRW_OPCODE_ADDC:
1799 assert(brw->gen >= 7);
1800 brw_ADDC(p, dst, src[0], src[1]);
1801 break;
1802 case BRW_OPCODE_SUBB:
1803 assert(brw->gen >= 7);
1804 brw_SUBB(p, dst, src[0], src[1]);
1805 break;
1806 case BRW_OPCODE_MAC:
1807 brw_MAC(p, dst, src[0], src[1]);
1808 break;
1809
1810 case BRW_OPCODE_BFE:
1811 assert(brw->gen >= 7);
1812 brw_set_default_access_mode(p, BRW_ALIGN_16);
1813 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1814 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1815 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1816 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1817 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1818 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1819 } else {
1820 brw_BFE(p, dst, src[0], src[1], src[2]);
1821 }
1822 brw_set_default_access_mode(p, BRW_ALIGN_1);
1823 break;
1824
1825 case BRW_OPCODE_BFI1:
1826 assert(brw->gen >= 7);
1827 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1828 * should
1829 *
1830 * "Force BFI instructions to be executed always in SIMD8."
1831 */
1832 if (dispatch_width == 16 && brw->is_haswell) {
1833 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1834 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1835 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1836 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1837 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1838 } else {
1839 brw_BFI1(p, dst, src[0], src[1]);
1840 }
1841 break;
1842 case BRW_OPCODE_BFI2:
1843 assert(brw->gen >= 7);
1844 brw_set_default_access_mode(p, BRW_ALIGN_16);
1845 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1846 * should
1847 *
1848 * "Force BFI instructions to be executed always in SIMD8."
1849 *
1850 * Otherwise we would be able to emit compressed instructions like we
1851 * do for the other three-source instructions.
1852 */
1853 if (dispatch_width == 16 &&
1854 (brw->is_haswell || !brw_supports_simd16_3src(brw))) {
1855 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1856 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1857 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1858 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1859 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1860 } else {
1861 brw_BFI2(p, dst, src[0], src[1], src[2]);
1862 }
1863 brw_set_default_access_mode(p, BRW_ALIGN_1);
1864 break;
1865
1866 case BRW_OPCODE_IF:
1867 if (inst->src[0].file != BAD_FILE) {
1868 /* The instruction has an embedded compare (only allowed on gen6) */
1869 assert(brw->gen == 6);
1870 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1871 } else {
1872 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1873 }
1874 break;
1875
1876 case BRW_OPCODE_ELSE:
1877 brw_ELSE(p);
1878 break;
1879 case BRW_OPCODE_ENDIF:
1880 brw_ENDIF(p);
1881 break;
1882
1883 case BRW_OPCODE_DO:
1884 brw_DO(p, BRW_EXECUTE_8);
1885 break;
1886
1887 case BRW_OPCODE_BREAK:
1888 brw_BREAK(p);
1889 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1890 break;
1891 case BRW_OPCODE_CONTINUE:
1892 brw_CONT(p);
1893 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1894 break;
1895
1896 case BRW_OPCODE_WHILE:
1897 brw_WHILE(p);
1898 loop_count++;
1899 break;
1900
1901 case SHADER_OPCODE_RCP:
1902 case SHADER_OPCODE_RSQ:
1903 case SHADER_OPCODE_SQRT:
1904 case SHADER_OPCODE_EXP2:
1905 case SHADER_OPCODE_LOG2:
1906 case SHADER_OPCODE_SIN:
1907 case SHADER_OPCODE_COS:
1908 assert(brw->gen < 6 || inst->mlen == 0);
1909 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1910 if (brw->gen >= 7) {
1911 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1912 brw_null_reg());
1913 } else if (brw->gen == 6) {
1914 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1915 } else if (brw->gen == 5 || brw->is_g4x) {
1916 generate_math_g45(inst, dst, src[0]);
1917 } else {
1918 generate_math_gen4(inst, dst, src[0]);
1919 }
1920 break;
1921 case SHADER_OPCODE_INT_QUOTIENT:
1922 case SHADER_OPCODE_INT_REMAINDER:
1923 case SHADER_OPCODE_POW:
1924 assert(brw->gen < 6 || inst->mlen == 0);
1925 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1926 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1927 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1928 } else if (brw->gen >= 6) {
1929 generate_math_gen6(inst, dst, src[0], src[1]);
1930 } else {
1931 generate_math_gen4(inst, dst, src[0]);
1932 }
1933 break;
1934 case FS_OPCODE_PIXEL_X:
1935 generate_pixel_xy(dst, true);
1936 break;
1937 case FS_OPCODE_PIXEL_Y:
1938 generate_pixel_xy(dst, false);
1939 break;
1940 case FS_OPCODE_CINTERP:
1941 brw_MOV(p, dst, src[0]);
1942 break;
1943 case FS_OPCODE_LINTERP:
1944 generate_linterp(inst, dst, src);
1945 break;
1946 case SHADER_OPCODE_TEX:
1947 case FS_OPCODE_TXB:
1948 case SHADER_OPCODE_TXD:
1949 case SHADER_OPCODE_TXF:
1950 case SHADER_OPCODE_TXF_CMS:
1951 case SHADER_OPCODE_TXF_UMS:
1952 case SHADER_OPCODE_TXF_MCS:
1953 case SHADER_OPCODE_TXL:
1954 case SHADER_OPCODE_TXS:
1955 case SHADER_OPCODE_LOD:
1956 case SHADER_OPCODE_TG4:
1957 case SHADER_OPCODE_TG4_OFFSET:
1958 generate_tex(inst, dst, src[0], src[1]);
1959 break;
1960 case FS_OPCODE_DDX_COARSE:
1961 case FS_OPCODE_DDX_FINE:
1962 generate_ddx(inst->opcode, dst, src[0]);
1963 break;
1964 case FS_OPCODE_DDY_COARSE:
1965 case FS_OPCODE_DDY_FINE:
1966 assert(src[1].file == BRW_IMMEDIATE_VALUE);
1967 generate_ddy(inst->opcode, dst, src[0], src[1].dw1.ud);
1968 break;
1969
1970 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1971 generate_scratch_write(inst, src[0]);
1972 spill_count++;
1973 break;
1974
1975 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1976 generate_scratch_read(inst, dst);
1977 fill_count++;
1978 break;
1979
1980 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1981 generate_scratch_read_gen7(inst, dst);
1982 fill_count++;
1983 break;
1984
1985 case SHADER_OPCODE_URB_WRITE_SIMD8:
1986 generate_urb_write(inst, src[0]);
1987 break;
1988
1989 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1990 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1991 break;
1992
1993 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1994 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1995 break;
1996
1997 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1998 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1999 break;
2000
2001 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
2002 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2003 break;
2004
2005 case FS_OPCODE_REP_FB_WRITE:
2006 case FS_OPCODE_FB_WRITE:
2007 generate_fb_write(inst, src[0]);
2008 break;
2009
2010 case FS_OPCODE_BLORP_FB_WRITE:
2011 generate_blorp_fb_write(inst);
2012 break;
2013
2014 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2015 generate_mov_dispatch_to_flags(inst);
2016 break;
2017
2018 case FS_OPCODE_DISCARD_JUMP:
2019 generate_discard_jump(inst);
2020 break;
2021
2022 case SHADER_OPCODE_SHADER_TIME_ADD:
2023 generate_shader_time_add(inst, src[0], src[1], src[2]);
2024 break;
2025
2026 case SHADER_OPCODE_UNTYPED_ATOMIC:
2027 generate_untyped_atomic(inst, dst, src[0], src[1], src[2]);
2028 break;
2029
2030 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2031 generate_untyped_surface_read(inst, dst, src[0], src[1]);
2032 break;
2033
2034 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2035 generate_set_simd4x2_offset(inst, dst, src[0]);
2036 break;
2037
2038 case FS_OPCODE_SET_OMASK:
2039 generate_set_omask(inst, dst, src[0]);
2040 break;
2041
2042 case FS_OPCODE_SET_SAMPLE_ID:
2043 generate_set_sample_id(inst, dst, src[0], src[1]);
2044 break;
2045
2046 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2047 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2048 break;
2049
2050 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2051 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2052 generate_unpack_half_2x16_split(inst, dst, src[0]);
2053 break;
2054
2055 case FS_OPCODE_PLACEHOLDER_HALT:
2056 /* This is the place where the final HALT needs to be inserted if
2057 * we've emitted any discards. If not, this will emit no code.
2058 */
2059 if (!patch_discard_jumps_to_fb_writes()) {
2060 if (unlikely(debug_flag)) {
2061 annotation.ann_count--;
2062 }
2063 }
2064 break;
2065
2066 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2067 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2068 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2069 break;
2070
2071 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2072 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2073 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2074 break;
2075
2076 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2077 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2078 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2079 break;
2080
2081 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2082 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2083 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2084 break;
2085
2086 default:
2087 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
2088 _mesa_problem(ctx, "Unsupported opcode `%s' in %s",
2089 opcode_descs[inst->opcode].name, stage_abbrev);
2090 } else {
2091 _mesa_problem(ctx, "Unsupported opcode %d in %s", inst->opcode,
2092 stage_abbrev);
2093 }
2094 abort();
2095
2096 case SHADER_OPCODE_LOAD_PAYLOAD:
2097 unreachable("Should be lowered by lower_load_payload()");
2098 }
2099
2100 if (multiple_instructions_emitted)
2101 continue;
2102
2103 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2104 assert(p->next_insn_offset == last_insn_offset + 16 ||
2105 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2106 "emitting more than 1 instruction");
2107
2108 brw_inst *last = &p->store[last_insn_offset / 16];
2109
2110 if (inst->conditional_mod)
2111 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
2112 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
2113 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
2114 }
2115 }
2116
2117 brw_set_uip_jip(p);
2118 annotation_finalize(&annotation, p->next_insn_offset);
2119
2120 int before_size = p->next_insn_offset - start_offset;
2121 brw_compact_instructions(p, start_offset, annotation.ann_count,
2122 annotation.ann);
2123 int after_size = p->next_insn_offset - start_offset;
2124
2125 if (unlikely(debug_flag)) {
2126 fprintf(stderr, "Native code for %s\n"
2127 "SIMD%d shader: %d instructions. %d loops. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2128 " bytes (%.0f%%)\n",
2129 shader_name, dispatch_width, before_size / 16, loop_count,
2130 spill_count, fill_count, promoted_constants, before_size, after_size,
2131 100.0f * (before_size - after_size) / before_size);
2132
2133 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
2134 ralloc_free(annotation.ann);
2135 }
2136
2137 static GLuint msg_id = 0;
2138 _mesa_gl_debug(&brw->ctx, &msg_id,
2139 MESA_DEBUG_SOURCE_SHADER_COMPILER,
2140 MESA_DEBUG_TYPE_OTHER,
2141 MESA_DEBUG_SEVERITY_NOTIFICATION,
2142 "%s SIMD%d shader: %d inst, %d loops, %d:%d spills:fills, "
2143 "Promoted %u constants, compacted %d to %d bytes.\n",
2144 stage_abbrev, dispatch_width, before_size / 16, loop_count,
2145 spill_count, fill_count, promoted_constants, before_size, after_size);
2146
2147 return start_offset;
2148 }
2149
2150 const unsigned *
2151 fs_generator::get_assembly(unsigned int *assembly_size)
2152 {
2153 return brw_get_program(p, assembly_size);
2154 }