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[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "brw_eu.h"
31 #include "brw_fs.h"
32 #include "brw_cfg.h"
33 #include "brw_program.h"
34
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case ARF:
40 return BRW_ARCHITECTURE_REGISTER_FILE;
41 case FIXED_GRF:
42 case VGRF:
43 return BRW_GENERAL_REGISTER_FILE;
44 case MRF:
45 return BRW_MESSAGE_REGISTER_FILE;
46 case IMM:
47 return BRW_IMMEDIATE_VALUE;
48 case BAD_FILE:
49 case ATTR:
50 case UNIFORM:
51 unreachable("not reached");
52 }
53 return BRW_ARCHITECTURE_REGISTER_FILE;
54 }
55
56 static struct brw_reg
57 brw_reg_from_fs_reg(const struct brw_codegen *p,
58 fs_inst *inst, fs_reg *reg, unsigned gen)
59 {
60 struct brw_reg brw_reg;
61
62 switch (reg->file) {
63 case MRF:
64 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(gen));
65 /* Fallthrough */
66 case VGRF:
67 if (reg->stride == 0) {
68 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
69 } else if (!p->compressed &&
70 inst->exec_size * reg->stride * type_sz(reg->type) <= 32) {
71 brw_reg = brw_vecn_reg(inst->exec_size, brw_file_from_reg(reg),
72 reg->nr, 0);
73 brw_reg = stride(brw_reg, inst->exec_size * reg->stride,
74 inst->exec_size, reg->stride);
75 } else {
76 /* From the Haswell PRM:
77 *
78 * VertStride must be used to cross GRF register boundaries. This
79 * rule implies that elements within a 'Width' cannot cross GRF
80 * boundaries.
81 *
82 * So, for registers that are large enough, we have to split the exec
83 * size in two and trust the compression state to sort it out.
84 */
85 assert(inst->exec_size / 2 * reg->stride * type_sz(reg->type) <= 32);
86 brw_reg = brw_vecn_reg(inst->exec_size / 2, brw_file_from_reg(reg),
87 reg->nr, 0);
88 brw_reg = stride(brw_reg, inst->exec_size / 2 * reg->stride,
89 inst->exec_size / 2, reg->stride);
90 }
91
92 brw_reg = retype(brw_reg, reg->type);
93 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
94 brw_reg.abs = reg->abs;
95 brw_reg.negate = reg->negate;
96 break;
97 case ARF:
98 case FIXED_GRF:
99 case IMM:
100 brw_reg = reg->as_brw_reg();
101 break;
102 case BAD_FILE:
103 /* Probably unused. */
104 brw_reg = brw_null_reg();
105 break;
106 case ATTR:
107 case UNIFORM:
108 unreachable("not reached");
109 }
110
111 return brw_reg;
112 }
113
114 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
115 void *mem_ctx,
116 const void *key,
117 struct brw_stage_prog_data *prog_data,
118 unsigned promoted_constants,
119 bool runtime_check_aads_emit,
120 gl_shader_stage stage)
121
122 : compiler(compiler), log_data(log_data),
123 devinfo(compiler->devinfo), key(key),
124 prog_data(prog_data),
125 promoted_constants(promoted_constants),
126 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
127 stage(stage), mem_ctx(mem_ctx)
128 {
129 p = rzalloc(mem_ctx, struct brw_codegen);
130 brw_init_codegen(devinfo, p, mem_ctx);
131 }
132
133 fs_generator::~fs_generator()
134 {
135 }
136
137 class ip_record : public exec_node {
138 public:
139 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
140
141 ip_record(int ip)
142 {
143 this->ip = ip;
144 }
145
146 int ip;
147 };
148
149 bool
150 fs_generator::patch_discard_jumps_to_fb_writes()
151 {
152 if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
153 return false;
154
155 int scale = brw_jump_scale(p->devinfo);
156
157 /* There is a somewhat strange undocumented requirement of using
158 * HALT, according to the simulator. If some channel has HALTed to
159 * a particular UIP, then by the end of the program, every channel
160 * must have HALTed to that UIP. Furthermore, the tracking is a
161 * stack, so you can't do the final halt of a UIP after starting
162 * halting to a new UIP.
163 *
164 * Symptoms of not emitting this instruction on actual hardware
165 * included GPU hangs and sparkly rendering on the piglit discard
166 * tests.
167 */
168 brw_inst *last_halt = gen6_HALT(p);
169 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
170 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
171
172 int ip = p->nr_insn;
173
174 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
175 brw_inst *patch = &p->store[patch_ip->ip];
176
177 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
178 /* HALT takes a half-instruction distance from the pre-incremented IP. */
179 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
180 }
181
182 this->discard_halt_patches.make_empty();
183 return true;
184 }
185
186 void
187 fs_generator::fire_fb_write(fs_inst *inst,
188 struct brw_reg payload,
189 struct brw_reg implied_header,
190 GLuint nr)
191 {
192 uint32_t msg_control;
193
194 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
195
196 if (devinfo->gen < 6) {
197 brw_push_insn_state(p);
198 brw_set_default_exec_size(p, BRW_EXECUTE_8);
199 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
200 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
201 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
202 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
203 brw_pop_insn_state(p);
204 }
205
206 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
207 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
208 else if (prog_data->dual_src_blend) {
209 if (!inst->force_sechalf)
210 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
211 else
212 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
213 } else if (inst->exec_size == 16)
214 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
215 else
216 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
217
218 uint32_t surf_index =
219 prog_data->binding_table.render_target_start + inst->target;
220
221 bool last_render_target = inst->eot ||
222 (prog_data->dual_src_blend && dispatch_width == 16);
223
224
225 brw_fb_WRITE(p,
226 dispatch_width,
227 payload,
228 implied_header,
229 msg_control,
230 surf_index,
231 nr,
232 0,
233 inst->eot,
234 last_render_target,
235 inst->header_size != 0);
236
237 brw_mark_surface_used(&prog_data->base, surf_index);
238 }
239
240 void
241 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
242 {
243 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
244 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
245 struct brw_reg implied_header;
246
247 if (devinfo->gen < 8 && !devinfo->is_haswell) {
248 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
249 }
250
251 if (inst->base_mrf >= 0)
252 payload = brw_message_reg(inst->base_mrf);
253
254 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
255 * move, here's g1.
256 */
257 if (inst->header_size != 0) {
258 brw_push_insn_state(p);
259 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
260 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
261 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
262 brw_set_default_flag_reg(p, 0, 0);
263
264 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
265 * present.
266 */
267 if (prog_data->uses_kill) {
268 struct brw_reg pixel_mask;
269
270 if (devinfo->gen >= 6)
271 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
272 else
273 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
274
275 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
276 }
277
278 if (devinfo->gen >= 6) {
279 brw_push_insn_state(p);
280 brw_set_default_exec_size(p, BRW_EXECUTE_16);
281 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
282 brw_MOV(p,
283 retype(payload, BRW_REGISTER_TYPE_UD),
284 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
285 brw_pop_insn_state(p);
286
287 if (inst->target > 0 && key->replicate_alpha) {
288 /* Set "Source0 Alpha Present to RenderTarget" bit in message
289 * header.
290 */
291 brw_OR(p,
292 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
293 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
294 brw_imm_ud(0x1 << 11));
295 }
296
297 if (inst->target > 0) {
298 /* Set the render target index for choosing BLEND_STATE. */
299 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
300 BRW_REGISTER_TYPE_UD),
301 brw_imm_ud(inst->target));
302 }
303
304 /* Set computes stencil to render target */
305 if (prog_data->computed_stencil) {
306 brw_OR(p,
307 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
308 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
309 brw_imm_ud(0x1 << 14));
310 }
311
312 implied_header = brw_null_reg();
313 } else {
314 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
315 }
316
317 brw_pop_insn_state(p);
318 } else {
319 implied_header = brw_null_reg();
320 }
321
322 if (!runtime_check_aads_emit) {
323 fire_fb_write(inst, payload, implied_header, inst->mlen);
324 } else {
325 /* This can only happen in gen < 6 */
326 assert(devinfo->gen < 6);
327
328 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
329
330 /* Check runtime bit to detect if we have to send AA data or not */
331 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
332 brw_AND(p,
333 v1_null_ud,
334 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
335 brw_imm_ud(1<<26));
336 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
337
338 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
339 brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
340 {
341 /* Don't send AA data */
342 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
343 }
344 brw_land_fwd_jump(p, jmp);
345 fire_fb_write(inst, payload, implied_header, inst->mlen);
346 }
347 }
348
349 void
350 fs_generator::generate_mov_indirect(fs_inst *inst,
351 struct brw_reg dst,
352 struct brw_reg reg,
353 struct brw_reg indirect_byte_offset)
354 {
355 assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD);
356 assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE);
357
358 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
359
360 if (indirect_byte_offset.file == BRW_IMMEDIATE_VALUE) {
361 imm_byte_offset += indirect_byte_offset.ud;
362
363 reg.nr = imm_byte_offset / REG_SIZE;
364 reg.subnr = imm_byte_offset % REG_SIZE;
365 brw_MOV(p, dst, reg);
366 } else {
367 /* Prior to Broadwell, there are only 8 address registers. */
368 assert(inst->exec_size == 8 || devinfo->gen >= 8);
369
370 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
371 struct brw_reg addr = vec8(brw_address_reg(0));
372
373 /* The destination stride of an instruction (in bytes) must be greater
374 * than or equal to the size of the rest of the instruction. Since the
375 * address register is of type UW, we can't use a D-type instruction.
376 * In order to get around this, re retype to UW and use a stride.
377 */
378 indirect_byte_offset =
379 retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);
380
381 struct brw_reg ind_src;
382 if (devinfo->gen < 8) {
383 /* From the Haswell PRM section "Register Region Restrictions":
384 *
385 * "The lower bits of the AddressImmediate must not overflow to
386 * change the register address. The lower 5 bits of Address
387 * Immediate when added to lower 5 bits of address register gives
388 * the sub-register offset. The upper bits of Address Immediate
389 * when added to upper bits of address register gives the register
390 * address. Any overflow from sub-register offset is dropped."
391 *
392 * This restriction is only listed in the Haswell PRM but emperical
393 * testing indicates that it applies on all older generations and is
394 * lifted on Broadwell.
395 *
396 * Since the indirect may cause us to cross a register boundary, this
397 * makes the base offset almost useless. We could try and do
398 * something clever where we use a actual base offset if
399 * base_offset % 32 == 0 but that would mean we were generating
400 * different code depending on the base offset. Instead, for the
401 * sake of consistency, we'll just do the add ourselves.
402 */
403 brw_ADD(p, addr, indirect_byte_offset, brw_imm_uw(imm_byte_offset));
404 ind_src = brw_VxH_indirect(0, 0);
405 } else {
406 brw_MOV(p, addr, indirect_byte_offset);
407 ind_src = brw_VxH_indirect(0, imm_byte_offset);
408 }
409
410 brw_inst *mov = brw_MOV(p, dst, retype(ind_src, dst.type));
411
412 if (devinfo->gen == 6 && dst.file == BRW_MESSAGE_REGISTER_FILE &&
413 !inst->get_next()->is_tail_sentinel() &&
414 ((fs_inst *)inst->get_next())->mlen > 0) {
415 /* From the Sandybridge PRM:
416 *
417 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
418 * instruction that “indexed/indirect” source AND is followed by a
419 * send, the instruction requires a “Switch”. This is to avoid
420 * race condition where send may dispatch before MRF is updated."
421 */
422 brw_inst_set_thread_control(devinfo, mov, BRW_THREAD_SWITCH);
423 }
424 }
425 }
426
427 void
428 fs_generator::generate_urb_read(fs_inst *inst,
429 struct brw_reg dst,
430 struct brw_reg header)
431 {
432 assert(header.file == BRW_GENERAL_REGISTER_FILE);
433 assert(header.type == BRW_REGISTER_TYPE_UD);
434
435 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
436 brw_set_dest(p, send, dst);
437 brw_set_src0(p, send, header);
438 brw_set_src1(p, send, brw_imm_ud(0u));
439
440 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
441 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
442
443 if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
444 brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
445
446 brw_inst_set_mlen(p->devinfo, send, inst->mlen);
447 brw_inst_set_rlen(p->devinfo, send, inst->regs_written);
448 brw_inst_set_header_present(p->devinfo, send, true);
449 brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
450 }
451
452 void
453 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
454 {
455 brw_inst *insn;
456
457 insn = brw_next_insn(p, BRW_OPCODE_SEND);
458
459 brw_set_dest(p, insn, brw_null_reg());
460 brw_set_src0(p, insn, payload);
461 brw_set_src1(p, insn, brw_imm_d(0));
462
463 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
464 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
465
466 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
467 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
468 brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
469
470 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
471 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
472 brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
473
474 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
475 brw_inst_set_rlen(p->devinfo, insn, 0);
476 brw_inst_set_eot(p->devinfo, insn, inst->eot);
477 brw_inst_set_header_present(p->devinfo, insn, true);
478 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
479 }
480
481 void
482 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
483 {
484 struct brw_inst *insn;
485
486 insn = brw_next_insn(p, BRW_OPCODE_SEND);
487
488 brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW));
489 brw_set_src0(p, insn, payload);
490 brw_set_src1(p, insn, brw_imm_d(0));
491
492 /* Terminate a compute shader by sending a message to the thread spawner.
493 */
494 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
495 brw_inst_set_mlen(devinfo, insn, 1);
496 brw_inst_set_rlen(devinfo, insn, 0);
497 brw_inst_set_eot(devinfo, insn, inst->eot);
498 brw_inst_set_header_present(devinfo, insn, false);
499
500 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
501 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
502
503 /* Note that even though the thread has a URB resource associated with it,
504 * we set the "do not dereference URB" bit, because the URB resource is
505 * managed by the fixed-function unit, so it will free it automatically.
506 */
507 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
508
509 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
510 }
511
512 void
513 fs_generator::generate_stencil_ref_packing(fs_inst *inst,
514 struct brw_reg dst,
515 struct brw_reg src)
516 {
517 assert(dispatch_width == 8);
518 assert(devinfo->gen >= 9);
519
520 /* Stencil value updates are provided in 8 slots of 1 byte per slot.
521 * Presumably, in order to save memory bandwidth, the stencil reference
522 * values written from the FS need to be packed into 2 dwords (this makes
523 * sense because the stencil values are limited to 1 byte each and a SIMD8
524 * send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
525 *
526 * The spec is confusing here because in the payload definition of MDP_RTW_S8
527 * (Message Data Payload for Render Target Writes with Stencil 8b) the
528 * stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
529 * dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
530 * packed values specified above and diagrammed below:
531 *
532 * 31 0
533 * --------------------------------
534 * DW | |
535 * 2-7 | IGNORED |
536 * | |
537 * --------------------------------
538 * DW1 | STC | STC | STC | STC |
539 * | slot7 | slot6 | slot5 | slot4|
540 * --------------------------------
541 * DW0 | STC | STC | STC | STC |
542 * | slot3 | slot2 | slot1 | slot0|
543 * --------------------------------
544 */
545
546 src.vstride = BRW_VERTICAL_STRIDE_4;
547 src.width = BRW_WIDTH_1;
548 src.hstride = BRW_HORIZONTAL_STRIDE_0;
549 assert(src.type == BRW_REGISTER_TYPE_UB);
550 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UB), src);
551 }
552
553 void
554 fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
555 {
556 brw_barrier(p, src);
557 brw_WAIT(p);
558 }
559
560 void
561 fs_generator::generate_linterp(fs_inst *inst,
562 struct brw_reg dst, struct brw_reg *src)
563 {
564 /* PLN reads:
565 * / in SIMD16 \
566 * -----------------------------------
567 * | src1+0 | src1+1 | src1+2 | src1+3 |
568 * |-----------------------------------|
569 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
570 * -----------------------------------
571 *
572 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
573 *
574 * -----------------------------------
575 * | src1+0 | src1+1 | src1+2 | src1+3 |
576 * |-----------------------------------|
577 * |(x0, x1)|(y0, y1)| | | in SIMD8
578 * |-----------------------------------|
579 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
580 * -----------------------------------
581 *
582 * See also: emit_interpolation_setup_gen4().
583 */
584 struct brw_reg delta_x = src[0];
585 struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
586 struct brw_reg interp = src[1];
587
588 if (devinfo->has_pln &&
589 (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
590 brw_PLN(p, dst, interp, delta_x);
591 } else {
592 brw_LINE(p, brw_null_reg(), interp, delta_x);
593 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
594 }
595 }
596
597 void
598 fs_generator::generate_get_buffer_size(fs_inst *inst,
599 struct brw_reg dst,
600 struct brw_reg src,
601 struct brw_reg surf_index)
602 {
603 assert(devinfo->gen >= 7);
604 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
605
606 uint32_t simd_mode;
607 int rlen = 4;
608
609 switch (inst->exec_size) {
610 case 8:
611 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
612 break;
613 case 16:
614 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
615 break;
616 default:
617 unreachable("Invalid width for texture instruction");
618 }
619
620 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
621 rlen = 8;
622 dst = vec16(dst);
623 }
624
625 brw_SAMPLE(p,
626 retype(dst, BRW_REGISTER_TYPE_UW),
627 inst->base_mrf,
628 src,
629 surf_index.ud,
630 0,
631 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
632 rlen, /* response length */
633 inst->mlen,
634 inst->header_size > 0,
635 simd_mode,
636 BRW_SAMPLER_RETURN_FORMAT_SINT32);
637
638 brw_mark_surface_used(prog_data, surf_index.ud);
639 }
640
641 void
642 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
643 struct brw_reg surface_index,
644 struct brw_reg sampler_index)
645 {
646 int msg_type = -1;
647 uint32_t simd_mode;
648 uint32_t return_format;
649 bool is_combined_send = inst->eot;
650
651 switch (dst.type) {
652 case BRW_REGISTER_TYPE_D:
653 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
654 break;
655 case BRW_REGISTER_TYPE_UD:
656 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
657 break;
658 default:
659 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
660 break;
661 }
662
663 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
664 * is set as part of the message descriptor. On gen4, the PRM seems to
665 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
666 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
667 * gone from the message descriptor entirely and you just get UINT32 all
668 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
669 * just stomp it to UINT32 all the time.
670 */
671 if (inst->opcode == SHADER_OPCODE_TXS)
672 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
673
674 switch (inst->exec_size) {
675 case 8:
676 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
677 break;
678 case 16:
679 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
680 break;
681 default:
682 unreachable("Invalid width for texture instruction");
683 }
684
685 if (devinfo->gen >= 5) {
686 switch (inst->opcode) {
687 case SHADER_OPCODE_TEX:
688 if (inst->shadow_compare) {
689 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
690 } else {
691 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
692 }
693 break;
694 case FS_OPCODE_TXB:
695 if (inst->shadow_compare) {
696 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
697 } else {
698 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
699 }
700 break;
701 case SHADER_OPCODE_TXL:
702 if (inst->shadow_compare) {
703 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
704 } else {
705 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
706 }
707 break;
708 case SHADER_OPCODE_TXL_LZ:
709 assert(devinfo->gen >= 9);
710 if (inst->shadow_compare) {
711 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ;
712 } else {
713 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LZ;
714 }
715 break;
716 case SHADER_OPCODE_TXS:
717 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
718 break;
719 case SHADER_OPCODE_TXD:
720 if (inst->shadow_compare) {
721 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
722 assert(devinfo->gen >= 8 || devinfo->is_haswell);
723 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
724 } else {
725 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
726 }
727 break;
728 case SHADER_OPCODE_TXF:
729 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
730 break;
731 case SHADER_OPCODE_TXF_LZ:
732 assert(devinfo->gen >= 9);
733 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ;
734 break;
735 case SHADER_OPCODE_TXF_CMS_W:
736 assert(devinfo->gen >= 9);
737 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
738 break;
739 case SHADER_OPCODE_TXF_CMS:
740 if (devinfo->gen >= 7)
741 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
742 else
743 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
744 break;
745 case SHADER_OPCODE_TXF_UMS:
746 assert(devinfo->gen >= 7);
747 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
748 break;
749 case SHADER_OPCODE_TXF_MCS:
750 assert(devinfo->gen >= 7);
751 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
752 break;
753 case SHADER_OPCODE_LOD:
754 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
755 break;
756 case SHADER_OPCODE_TG4:
757 if (inst->shadow_compare) {
758 assert(devinfo->gen >= 7);
759 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
760 } else {
761 assert(devinfo->gen >= 6);
762 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
763 }
764 break;
765 case SHADER_OPCODE_TG4_OFFSET:
766 assert(devinfo->gen >= 7);
767 if (inst->shadow_compare) {
768 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
769 } else {
770 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
771 }
772 break;
773 case SHADER_OPCODE_SAMPLEINFO:
774 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
775 break;
776 default:
777 unreachable("not reached");
778 }
779 } else {
780 switch (inst->opcode) {
781 case SHADER_OPCODE_TEX:
782 /* Note that G45 and older determines shadow compare and dispatch width
783 * from message length for most messages.
784 */
785 if (inst->exec_size == 8) {
786 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
787 if (inst->shadow_compare) {
788 assert(inst->mlen == 6);
789 } else {
790 assert(inst->mlen <= 4);
791 }
792 } else {
793 if (inst->shadow_compare) {
794 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
795 assert(inst->mlen == 9);
796 } else {
797 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
798 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
799 }
800 }
801 break;
802 case FS_OPCODE_TXB:
803 if (inst->shadow_compare) {
804 assert(inst->exec_size == 8);
805 assert(inst->mlen == 6);
806 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
807 } else {
808 assert(inst->mlen == 9);
809 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
810 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
811 }
812 break;
813 case SHADER_OPCODE_TXL:
814 if (inst->shadow_compare) {
815 assert(inst->exec_size == 8);
816 assert(inst->mlen == 6);
817 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
818 } else {
819 assert(inst->mlen == 9);
820 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
821 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
822 }
823 break;
824 case SHADER_OPCODE_TXD:
825 /* There is no sample_d_c message; comparisons are done manually */
826 assert(inst->exec_size == 8);
827 assert(inst->mlen == 7 || inst->mlen == 10);
828 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
829 break;
830 case SHADER_OPCODE_TXF:
831 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
832 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
833 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
834 break;
835 case SHADER_OPCODE_TXS:
836 assert(inst->mlen == 3);
837 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
838 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
839 break;
840 default:
841 unreachable("not reached");
842 }
843 }
844 assert(msg_type != -1);
845
846 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
847 dst = vec16(dst);
848 }
849
850 assert(devinfo->gen < 7 || inst->header_size == 0 ||
851 src.file == BRW_GENERAL_REGISTER_FILE);
852
853 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
854
855 /* Load the message header if present. If there's a texture offset,
856 * we need to set it up explicitly and load the offset bitfield.
857 * Otherwise, we can use an implied move from g0 to the first message reg.
858 */
859 if (inst->header_size != 0) {
860 if (devinfo->gen < 6 && !inst->offset) {
861 /* Set up an implied move from g0 to the MRF. */
862 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
863 } else {
864 struct brw_reg header_reg;
865
866 if (devinfo->gen >= 7) {
867 header_reg = src;
868 } else {
869 assert(inst->base_mrf != -1);
870 header_reg = brw_message_reg(inst->base_mrf);
871 }
872
873 brw_push_insn_state(p);
874 brw_set_default_exec_size(p, BRW_EXECUTE_8);
875 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
876 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
877 /* Explicitly set up the message header by copying g0 to the MRF. */
878 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
879
880 if (inst->offset) {
881 /* Set the offset bits in DWord 2. */
882 brw_MOV(p, get_element_ud(header_reg, 2),
883 brw_imm_ud(inst->offset));
884 } else if (stage != MESA_SHADER_VERTEX &&
885 stage != MESA_SHADER_FRAGMENT) {
886 /* The vertex and fragment stages have g0.2 set to 0, so
887 * header0.2 is 0 when g0 is copied. Other stages may not, so we
888 * must set it to 0 to avoid setting undesirable bits in the
889 * message.
890 */
891 brw_MOV(p, get_element_ud(header_reg, 2), brw_imm_ud(0));
892 }
893
894 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
895 brw_pop_insn_state(p);
896 }
897 }
898
899 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
900 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
901 ? prog_data->binding_table.gather_texture_start
902 : prog_data->binding_table.texture_start;
903
904 if (surface_index.file == BRW_IMMEDIATE_VALUE &&
905 sampler_index.file == BRW_IMMEDIATE_VALUE) {
906 uint32_t surface = surface_index.ud;
907 uint32_t sampler = sampler_index.ud;
908
909 brw_SAMPLE(p,
910 retype(dst, BRW_REGISTER_TYPE_UW),
911 inst->base_mrf,
912 src,
913 surface + base_binding_table_index,
914 sampler % 16,
915 msg_type,
916 inst->regs_written,
917 inst->mlen,
918 inst->header_size != 0,
919 simd_mode,
920 return_format);
921
922 brw_mark_surface_used(prog_data, surface + base_binding_table_index);
923 } else {
924 /* Non-const sampler index */
925
926 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
927 struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
928 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
929
930 brw_push_insn_state(p);
931 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
932 brw_set_default_access_mode(p, BRW_ALIGN_1);
933
934 if (brw_regs_equal(&surface_reg, &sampler_reg)) {
935 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
936 } else {
937 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
938 brw_OR(p, addr, addr, surface_reg);
939 }
940 if (base_binding_table_index)
941 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
942 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
943
944 brw_pop_insn_state(p);
945
946 /* dst = send(offset, a0.0 | <descriptor>) */
947 brw_inst *insn = brw_send_indirect_message(
948 p, BRW_SFID_SAMPLER, dst, src, addr);
949 brw_set_sampler_message(p, insn,
950 0 /* surface */,
951 0 /* sampler */,
952 msg_type,
953 inst->regs_written,
954 inst->mlen /* mlen */,
955 inst->header_size != 0 /* header */,
956 simd_mode,
957 return_format);
958
959 /* visitor knows more than we do about the surface limit required,
960 * so has already done marking.
961 */
962 }
963
964 if (is_combined_send) {
965 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
966 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
967 }
968 }
969
970
971 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
972 * looking like:
973 *
974 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
975 *
976 * Ideally, we want to produce:
977 *
978 * DDX DDY
979 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
980 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
981 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
982 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
983 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
984 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
985 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
986 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
987 *
988 * and add another set of two more subspans if in 16-pixel dispatch mode.
989 *
990 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
991 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
992 * pair. But the ideal approximation may impose a huge performance cost on
993 * sample_d. On at least Haswell, sample_d instruction does some
994 * optimizations if the same LOD is used for all pixels in the subspan.
995 *
996 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
997 * appropriate swizzling.
998 */
999 void
1000 fs_generator::generate_ddx(enum opcode opcode,
1001 struct brw_reg dst, struct brw_reg src)
1002 {
1003 unsigned vstride, width;
1004
1005 if (opcode == FS_OPCODE_DDX_FINE) {
1006 /* produce accurate derivatives */
1007 vstride = BRW_VERTICAL_STRIDE_2;
1008 width = BRW_WIDTH_2;
1009 } else {
1010 /* replicate the derivative at the top-left pixel to other pixels */
1011 vstride = BRW_VERTICAL_STRIDE_4;
1012 width = BRW_WIDTH_4;
1013 }
1014
1015 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
1016 src.negate, src.abs,
1017 BRW_REGISTER_TYPE_F,
1018 vstride,
1019 width,
1020 BRW_HORIZONTAL_STRIDE_0,
1021 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1022 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1023 src.negate, src.abs,
1024 BRW_REGISTER_TYPE_F,
1025 vstride,
1026 width,
1027 BRW_HORIZONTAL_STRIDE_0,
1028 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1029 brw_ADD(p, dst, src0, negate(src1));
1030 }
1031
1032 /* The negate_value boolean is used to negate the derivative computation for
1033 * FBOs, since they place the origin at the upper left instead of the lower
1034 * left.
1035 */
1036 void
1037 fs_generator::generate_ddy(enum opcode opcode,
1038 struct brw_reg dst, struct brw_reg src)
1039 {
1040 if (opcode == FS_OPCODE_DDY_FINE) {
1041 /* produce accurate derivatives */
1042 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1043 src.negate, src.abs,
1044 BRW_REGISTER_TYPE_F,
1045 BRW_VERTICAL_STRIDE_4,
1046 BRW_WIDTH_4,
1047 BRW_HORIZONTAL_STRIDE_1,
1048 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
1049 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1050 src.negate, src.abs,
1051 BRW_REGISTER_TYPE_F,
1052 BRW_VERTICAL_STRIDE_4,
1053 BRW_WIDTH_4,
1054 BRW_HORIZONTAL_STRIDE_1,
1055 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
1056 brw_push_insn_state(p);
1057 brw_set_default_access_mode(p, BRW_ALIGN_16);
1058 brw_ADD(p, dst, negate(src0), src1);
1059 brw_pop_insn_state(p);
1060 } else {
1061 /* replicate the derivative at the top-left pixel to other pixels */
1062 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1063 src.negate, src.abs,
1064 BRW_REGISTER_TYPE_F,
1065 BRW_VERTICAL_STRIDE_4,
1066 BRW_WIDTH_4,
1067 BRW_HORIZONTAL_STRIDE_0,
1068 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1069 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
1070 src.negate, src.abs,
1071 BRW_REGISTER_TYPE_F,
1072 BRW_VERTICAL_STRIDE_4,
1073 BRW_WIDTH_4,
1074 BRW_HORIZONTAL_STRIDE_0,
1075 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1076 brw_ADD(p, dst, negate(src0), src1);
1077 }
1078 }
1079
1080 void
1081 fs_generator::generate_discard_jump(fs_inst *inst)
1082 {
1083 assert(devinfo->gen >= 6);
1084
1085 /* This HALT will be patched up at FB write time to point UIP at the end of
1086 * the program, and at brw_uip_jip() JIP will be set to the end of the
1087 * current block (or the program).
1088 */
1089 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1090
1091 brw_push_insn_state(p);
1092 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1093 gen6_HALT(p);
1094 brw_pop_insn_state(p);
1095 }
1096
1097 void
1098 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1099 {
1100 assert(inst->mlen != 0);
1101
1102 brw_MOV(p,
1103 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
1104 retype(src, BRW_REGISTER_TYPE_UD));
1105 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1106 inst->exec_size / 8, inst->offset);
1107 }
1108
1109 void
1110 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1111 {
1112 assert(inst->mlen != 0);
1113
1114 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1115 inst->exec_size / 8, inst->offset);
1116 }
1117
1118 void
1119 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1120 {
1121 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1122 }
1123
1124 void
1125 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1126 struct brw_reg dst,
1127 struct brw_reg index,
1128 struct brw_reg offset)
1129 {
1130 assert(inst->mlen != 0);
1131
1132 assert(index.file == BRW_IMMEDIATE_VALUE &&
1133 index.type == BRW_REGISTER_TYPE_UD);
1134 uint32_t surf_index = index.ud;
1135
1136 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1137 offset.type == BRW_REGISTER_TYPE_UD);
1138 uint32_t read_offset = offset.ud;
1139
1140 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1141 read_offset, surf_index);
1142 }
1143
1144 void
1145 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1146 struct brw_reg dst,
1147 struct brw_reg index,
1148 struct brw_reg offset)
1149 {
1150 assert(index.type == BRW_REGISTER_TYPE_UD);
1151
1152 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1153 /* Reference just the dword we need, to avoid angering validate_reg(). */
1154 offset = brw_vec1_grf(offset.nr, 0);
1155
1156 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1157 * the destination loaded consecutively from the same offset (which appears
1158 * in the first component, and the rest are ignored).
1159 */
1160 dst.width = BRW_WIDTH_4;
1161
1162 struct brw_reg src = offset;
1163 bool header_present = false;
1164
1165 if (devinfo->gen >= 9) {
1166 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1167 src = retype(brw_vec4_grf(offset.nr, 0), BRW_REGISTER_TYPE_UD);
1168 header_present = true;
1169
1170 brw_push_insn_state(p);
1171 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1172 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1173 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1174 brw_set_default_access_mode(p, BRW_ALIGN_1);
1175
1176 brw_MOV(p, get_element_ud(src, 2),
1177 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1178 brw_pop_insn_state(p);
1179 }
1180
1181 if (index.file == BRW_IMMEDIATE_VALUE) {
1182
1183 uint32_t surf_index = index.ud;
1184
1185 brw_push_insn_state(p);
1186 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1187 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1188 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1189 brw_inst_set_exec_size(devinfo, send, BRW_EXECUTE_4);
1190 brw_pop_insn_state(p);
1191
1192 brw_set_dest(p, send, dst);
1193 brw_set_src0(p, send, src);
1194 brw_set_sampler_message(p, send,
1195 surf_index,
1196 0, /* LD message ignores sampler unit */
1197 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1198 1, /* rlen */
1199 inst->mlen,
1200 header_present,
1201 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1202 0);
1203 } else {
1204
1205 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1206
1207 brw_push_insn_state(p);
1208 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1209 brw_set_default_access_mode(p, BRW_ALIGN_1);
1210
1211 /* a0.0 = surf_index & 0xff */
1212 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1213 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1214 brw_set_dest(p, insn_and, addr);
1215 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1216 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1217
1218 /* dst = send(payload, a0.0 | <descriptor>) */
1219 brw_inst *insn = brw_send_indirect_message(
1220 p, BRW_SFID_SAMPLER, dst, src, addr);
1221 brw_set_sampler_message(p, insn,
1222 0,
1223 0, /* LD message ignores sampler unit */
1224 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1225 1, /* rlen */
1226 inst->mlen,
1227 header_present,
1228 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1229 0);
1230
1231 brw_pop_insn_state(p);
1232 }
1233 }
1234
1235 void
1236 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst *inst,
1237 struct brw_reg dst,
1238 struct brw_reg index)
1239 {
1240 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1241 assert(inst->header_size != 0);
1242 assert(inst->mlen);
1243
1244 assert(index.file == BRW_IMMEDIATE_VALUE &&
1245 index.type == BRW_REGISTER_TYPE_UD);
1246 uint32_t surf_index = index.ud;
1247
1248 uint32_t simd_mode, rlen, msg_type;
1249 if (dispatch_width == 16) {
1250 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1251 rlen = 8;
1252 } else {
1253 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1254 rlen = 4;
1255 }
1256
1257 if (devinfo->gen >= 5)
1258 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1259 else {
1260 /* We always use the SIMD16 message so that we only have to load U, and
1261 * not V or R.
1262 */
1263 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1264 assert(inst->mlen == 3);
1265 assert(inst->regs_written == 8);
1266 rlen = 8;
1267 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1268 }
1269
1270 struct brw_reg header = brw_vec8_grf(0, 0);
1271 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1272
1273 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1274 brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
1275 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1276 brw_set_src0(p, send, header);
1277 if (devinfo->gen < 6)
1278 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1279
1280 /* Our surface is set up as floats, regardless of what actual data is
1281 * stored in it.
1282 */
1283 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1284 brw_set_sampler_message(p, send,
1285 surf_index,
1286 0, /* sampler (unused) */
1287 msg_type,
1288 rlen,
1289 inst->mlen,
1290 inst->header_size != 0,
1291 simd_mode,
1292 return_format);
1293 }
1294
1295 void
1296 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1297 struct brw_reg dst,
1298 struct brw_reg index,
1299 struct brw_reg offset)
1300 {
1301 assert(devinfo->gen >= 7);
1302 /* Varying-offset pull constant loads are treated as a normal expression on
1303 * gen7, so the fact that it's a send message is hidden at the IR level.
1304 */
1305 assert(inst->header_size == 0);
1306 assert(!inst->mlen);
1307 assert(index.type == BRW_REGISTER_TYPE_UD);
1308
1309 uint32_t simd_mode, rlen, mlen;
1310 if (dispatch_width == 16) {
1311 mlen = 2;
1312 rlen = 8;
1313 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1314 } else {
1315 mlen = 1;
1316 rlen = 4;
1317 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1318 }
1319
1320 if (index.file == BRW_IMMEDIATE_VALUE) {
1321
1322 uint32_t surf_index = index.ud;
1323
1324 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1325 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1326 brw_set_src0(p, send, offset);
1327 brw_set_sampler_message(p, send,
1328 surf_index,
1329 0, /* LD message ignores sampler unit */
1330 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1331 rlen,
1332 mlen,
1333 false, /* no header */
1334 simd_mode,
1335 0);
1336
1337 } else {
1338
1339 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1340
1341 brw_push_insn_state(p);
1342 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1343 brw_set_default_access_mode(p, BRW_ALIGN_1);
1344
1345 /* a0.0 = surf_index & 0xff */
1346 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1347 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1348 brw_set_dest(p, insn_and, addr);
1349 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1350 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1351
1352 brw_pop_insn_state(p);
1353
1354 /* dst = send(offset, a0.0 | <descriptor>) */
1355 brw_inst *insn = brw_send_indirect_message(
1356 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1357 offset, addr);
1358 brw_set_sampler_message(p, insn,
1359 0 /* surface */,
1360 0 /* sampler */,
1361 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1362 rlen /* rlen */,
1363 mlen /* mlen */,
1364 false /* header */,
1365 simd_mode,
1366 0);
1367 }
1368 }
1369
1370 /**
1371 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1372 * into the flags register (f0.0).
1373 *
1374 * Used only on Gen6 and above.
1375 */
1376 void
1377 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1378 {
1379 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1380 struct brw_reg dispatch_mask;
1381
1382 if (devinfo->gen >= 6)
1383 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1384 else
1385 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1386
1387 brw_push_insn_state(p);
1388 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1389 brw_MOV(p, flags, dispatch_mask);
1390 brw_pop_insn_state(p);
1391 }
1392
1393 void
1394 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1395 struct brw_reg dst,
1396 struct brw_reg src,
1397 struct brw_reg msg_data,
1398 unsigned msg_type)
1399 {
1400 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1401
1402 brw_pixel_interpolator_query(p,
1403 retype(dst, BRW_REGISTER_TYPE_UW),
1404 src,
1405 inst->pi_noperspective,
1406 msg_type,
1407 msg_data,
1408 inst->mlen,
1409 inst->regs_written);
1410 }
1411
1412
1413 /**
1414 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1415 * sampler LD messages.
1416 *
1417 * We don't want to bake it into the send message's code generation because
1418 * that means we don't get a chance to schedule the instructions.
1419 */
1420 void
1421 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1422 struct brw_reg dst,
1423 struct brw_reg value)
1424 {
1425 assert(value.file == BRW_IMMEDIATE_VALUE);
1426
1427 brw_push_insn_state(p);
1428 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1429 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1430 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1431 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1432 brw_pop_insn_state(p);
1433 }
1434
1435 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1436 * the ADD instruction.
1437 */
1438 void
1439 fs_generator::generate_set_sample_id(fs_inst *inst,
1440 struct brw_reg dst,
1441 struct brw_reg src0,
1442 struct brw_reg src1)
1443 {
1444 assert(dst.type == BRW_REGISTER_TYPE_D ||
1445 dst.type == BRW_REGISTER_TYPE_UD);
1446 assert(src0.type == BRW_REGISTER_TYPE_D ||
1447 src0.type == BRW_REGISTER_TYPE_UD);
1448
1449 struct brw_reg reg = stride(src1, 1, 4, 0);
1450 if (devinfo->gen >= 8 || dispatch_width == 8) {
1451 brw_ADD(p, dst, src0, reg);
1452 } else if (dispatch_width == 16) {
1453 brw_push_insn_state(p);
1454 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1455 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1456 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1457 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1458 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1459 brw_pop_insn_state(p);
1460 }
1461 }
1462
1463 void
1464 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1465 struct brw_reg dst,
1466 struct brw_reg x,
1467 struct brw_reg y)
1468 {
1469 assert(devinfo->gen >= 7);
1470 assert(dst.type == BRW_REGISTER_TYPE_UD);
1471 assert(x.type == BRW_REGISTER_TYPE_F);
1472 assert(y.type == BRW_REGISTER_TYPE_F);
1473
1474 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1475 *
1476 * Because this instruction does not have a 16-bit floating-point type,
1477 * the destination data type must be Word (W).
1478 *
1479 * The destination must be DWord-aligned and specify a horizontal stride
1480 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1481 * each destination channel and the upper word is not modified.
1482 */
1483 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1484
1485 /* Give each 32-bit channel of dst the form below, where "." means
1486 * unchanged.
1487 * 0x....hhhh
1488 */
1489 brw_F32TO16(p, dst_w, y);
1490
1491 /* Now the form:
1492 * 0xhhhh0000
1493 */
1494 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1495
1496 /* And, finally the form of packHalf2x16's output:
1497 * 0xhhhhllll
1498 */
1499 brw_F32TO16(p, dst_w, x);
1500 }
1501
1502 void
1503 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1504 struct brw_reg dst,
1505 struct brw_reg src)
1506 {
1507 assert(devinfo->gen >= 7);
1508 assert(dst.type == BRW_REGISTER_TYPE_F);
1509 assert(src.type == BRW_REGISTER_TYPE_UD);
1510
1511 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1512 *
1513 * Because this instruction does not have a 16-bit floating-point type,
1514 * the source data type must be Word (W). The destination type must be
1515 * F (Float).
1516 */
1517 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1518
1519 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1520 * For the Y case, we wish to access only the upper word; therefore
1521 * a 16-bit subregister offset is needed.
1522 */
1523 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1524 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1525 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1526 src_w.subnr += 2;
1527
1528 brw_F16TO32(p, dst, src_w);
1529 }
1530
1531 void
1532 fs_generator::generate_shader_time_add(fs_inst *inst,
1533 struct brw_reg payload,
1534 struct brw_reg offset,
1535 struct brw_reg value)
1536 {
1537 assert(devinfo->gen >= 7);
1538 brw_push_insn_state(p);
1539 brw_set_default_mask_control(p, true);
1540
1541 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1542 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1543 offset.type);
1544 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1545 value.type);
1546
1547 assert(offset.file == BRW_IMMEDIATE_VALUE);
1548 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1549 value.width = BRW_WIDTH_1;
1550 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1551 value.vstride = BRW_VERTICAL_STRIDE_0;
1552 } else {
1553 assert(value.file == BRW_IMMEDIATE_VALUE);
1554 }
1555
1556 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1557 * case, and we don't really care about squeezing every bit of performance
1558 * out of this path, so we just emit the MOVs from here.
1559 */
1560 brw_MOV(p, payload_offset, offset);
1561 brw_MOV(p, payload_value, value);
1562 brw_shader_time_add(p, payload,
1563 prog_data->binding_table.shader_time_start);
1564 brw_pop_insn_state(p);
1565
1566 brw_mark_surface_used(prog_data,
1567 prog_data->binding_table.shader_time_start);
1568 }
1569
1570 void
1571 fs_generator::enable_debug(const char *shader_name)
1572 {
1573 debug_flag = true;
1574 this->shader_name = shader_name;
1575 }
1576
1577 int
1578 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1579 {
1580 /* align to 64 byte boundary. */
1581 while (p->next_insn_offset % 64)
1582 brw_NOP(p);
1583
1584 this->dispatch_width = dispatch_width;
1585 if (dispatch_width == 16)
1586 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1587
1588 int start_offset = p->next_insn_offset;
1589 int spill_count = 0, fill_count = 0;
1590 int loop_count = 0;
1591
1592 struct annotation_info annotation;
1593 memset(&annotation, 0, sizeof(annotation));
1594
1595 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1596 struct brw_reg src[3], dst;
1597 unsigned int last_insn_offset = p->next_insn_offset;
1598 bool multiple_instructions_emitted = false;
1599
1600 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1601 * "Register Region Restrictions" section: for BDW, SKL:
1602 *
1603 * "A POW/FDIV operation must not be followed by an instruction
1604 * that requires two destination registers."
1605 *
1606 * The documentation is often lacking annotations for Atom parts,
1607 * and empirically this affects CHV as well.
1608 */
1609 if (devinfo->gen >= 8 &&
1610 p->nr_insn > 1 &&
1611 brw_inst_opcode(devinfo, brw_last_inst) == BRW_OPCODE_MATH &&
1612 brw_inst_math_function(devinfo, brw_last_inst) == BRW_MATH_FUNCTION_POW &&
1613 inst->dst.component_size(inst->exec_size) > REG_SIZE) {
1614 brw_NOP(p);
1615 last_insn_offset = p->next_insn_offset;
1616 }
1617
1618 if (unlikely(debug_flag))
1619 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1620
1621 switch (inst->exec_size) {
1622 case 1:
1623 case 2:
1624 case 4:
1625 assert(inst->force_writemask_all);
1626 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1627 break;
1628 case 8:
1629 if (inst->force_sechalf) {
1630 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1631 } else {
1632 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1633 }
1634 break;
1635 case 16:
1636 case 32:
1637 /* If the instruction writes to more than one register, it needs to
1638 * be a "compressed" instruction on Gen <= 5.
1639 */
1640 if (inst->dst.component_size(inst->exec_size) > REG_SIZE)
1641 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1642 else
1643 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1644 break;
1645 default:
1646 unreachable("Invalid instruction width");
1647 }
1648
1649 for (unsigned int i = 0; i < inst->sources; i++) {
1650 src[i] = brw_reg_from_fs_reg(p, inst, &inst->src[i], devinfo->gen);
1651
1652 /* The accumulator result appears to get used for the
1653 * conditional modifier generation. When negating a UD
1654 * value, there is a 33rd bit generated for the sign in the
1655 * accumulator value, so now you can't check, for example,
1656 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1657 */
1658 assert(!inst->conditional_mod ||
1659 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1660 !inst->src[i].negate);
1661 }
1662 dst = brw_reg_from_fs_reg(p, inst, &inst->dst, devinfo->gen);
1663
1664 brw_set_default_access_mode(p, BRW_ALIGN_1);
1665 brw_set_default_predicate_control(p, inst->predicate);
1666 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1667 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1668 brw_set_default_saturate(p, inst->saturate);
1669 brw_set_default_mask_control(p, inst->force_writemask_all);
1670 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1671 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1672
1673 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1674 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1675
1676 switch (inst->opcode) {
1677 case BRW_OPCODE_MOV:
1678 brw_MOV(p, dst, src[0]);
1679 break;
1680 case BRW_OPCODE_ADD:
1681 brw_ADD(p, dst, src[0], src[1]);
1682 break;
1683 case BRW_OPCODE_MUL:
1684 brw_MUL(p, dst, src[0], src[1]);
1685 break;
1686 case BRW_OPCODE_AVG:
1687 brw_AVG(p, dst, src[0], src[1]);
1688 break;
1689 case BRW_OPCODE_MACH:
1690 brw_MACH(p, dst, src[0], src[1]);
1691 break;
1692
1693 case BRW_OPCODE_LINE:
1694 brw_LINE(p, dst, src[0], src[1]);
1695 break;
1696
1697 case BRW_OPCODE_MAD:
1698 assert(devinfo->gen >= 6);
1699 brw_set_default_access_mode(p, BRW_ALIGN_16);
1700 brw_MAD(p, dst, src[0], src[1], src[2]);
1701 break;
1702
1703 case BRW_OPCODE_LRP:
1704 assert(devinfo->gen >= 6);
1705 brw_set_default_access_mode(p, BRW_ALIGN_16);
1706 brw_LRP(p, dst, src[0], src[1], src[2]);
1707 break;
1708
1709 case BRW_OPCODE_FRC:
1710 brw_FRC(p, dst, src[0]);
1711 break;
1712 case BRW_OPCODE_RNDD:
1713 brw_RNDD(p, dst, src[0]);
1714 break;
1715 case BRW_OPCODE_RNDE:
1716 brw_RNDE(p, dst, src[0]);
1717 break;
1718 case BRW_OPCODE_RNDZ:
1719 brw_RNDZ(p, dst, src[0]);
1720 break;
1721
1722 case BRW_OPCODE_AND:
1723 brw_AND(p, dst, src[0], src[1]);
1724 break;
1725 case BRW_OPCODE_OR:
1726 brw_OR(p, dst, src[0], src[1]);
1727 break;
1728 case BRW_OPCODE_XOR:
1729 brw_XOR(p, dst, src[0], src[1]);
1730 break;
1731 case BRW_OPCODE_NOT:
1732 brw_NOT(p, dst, src[0]);
1733 break;
1734 case BRW_OPCODE_ASR:
1735 brw_ASR(p, dst, src[0], src[1]);
1736 break;
1737 case BRW_OPCODE_SHR:
1738 brw_SHR(p, dst, src[0], src[1]);
1739 break;
1740 case BRW_OPCODE_SHL:
1741 brw_SHL(p, dst, src[0], src[1]);
1742 break;
1743 case BRW_OPCODE_F32TO16:
1744 assert(devinfo->gen >= 7);
1745 brw_F32TO16(p, dst, src[0]);
1746 break;
1747 case BRW_OPCODE_F16TO32:
1748 assert(devinfo->gen >= 7);
1749 brw_F16TO32(p, dst, src[0]);
1750 break;
1751 case BRW_OPCODE_CMP:
1752 if (inst->exec_size >= 16 && devinfo->gen == 7 && !devinfo->is_haswell &&
1753 dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1754 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1755 * implemented in the compiler is not sufficient. Overriding the
1756 * type when the destination is the null register is necessary but
1757 * not sufficient by itself.
1758 */
1759 assert(dst.nr == BRW_ARF_NULL);
1760 dst.type = BRW_REGISTER_TYPE_D;
1761 }
1762 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1763 break;
1764 case BRW_OPCODE_SEL:
1765 brw_SEL(p, dst, src[0], src[1]);
1766 break;
1767 case BRW_OPCODE_BFREV:
1768 assert(devinfo->gen >= 7);
1769 /* BFREV only supports UD type for src and dst. */
1770 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1771 retype(src[0], BRW_REGISTER_TYPE_UD));
1772 break;
1773 case BRW_OPCODE_FBH:
1774 assert(devinfo->gen >= 7);
1775 /* FBH only supports UD type for dst. */
1776 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1777 break;
1778 case BRW_OPCODE_FBL:
1779 assert(devinfo->gen >= 7);
1780 /* FBL only supports UD type for dst. */
1781 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1782 break;
1783 case BRW_OPCODE_CBIT:
1784 assert(devinfo->gen >= 7);
1785 /* CBIT only supports UD type for dst. */
1786 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1787 break;
1788 case BRW_OPCODE_ADDC:
1789 assert(devinfo->gen >= 7);
1790 brw_ADDC(p, dst, src[0], src[1]);
1791 break;
1792 case BRW_OPCODE_SUBB:
1793 assert(devinfo->gen >= 7);
1794 brw_SUBB(p, dst, src[0], src[1]);
1795 break;
1796 case BRW_OPCODE_MAC:
1797 brw_MAC(p, dst, src[0], src[1]);
1798 break;
1799
1800 case BRW_OPCODE_BFE:
1801 assert(devinfo->gen >= 7);
1802 brw_set_default_access_mode(p, BRW_ALIGN_16);
1803 brw_BFE(p, dst, src[0], src[1], src[2]);
1804 break;
1805
1806 case BRW_OPCODE_BFI1:
1807 assert(devinfo->gen >= 7);
1808 brw_BFI1(p, dst, src[0], src[1]);
1809 break;
1810 case BRW_OPCODE_BFI2:
1811 assert(devinfo->gen >= 7);
1812 brw_set_default_access_mode(p, BRW_ALIGN_16);
1813 brw_BFI2(p, dst, src[0], src[1], src[2]);
1814 break;
1815
1816 case BRW_OPCODE_IF:
1817 if (inst->src[0].file != BAD_FILE) {
1818 /* The instruction has an embedded compare (only allowed on gen6) */
1819 assert(devinfo->gen == 6);
1820 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1821 } else {
1822 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1823 }
1824 break;
1825
1826 case BRW_OPCODE_ELSE:
1827 brw_ELSE(p);
1828 break;
1829 case BRW_OPCODE_ENDIF:
1830 brw_ENDIF(p);
1831 break;
1832
1833 case BRW_OPCODE_DO:
1834 brw_DO(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1835 break;
1836
1837 case BRW_OPCODE_BREAK:
1838 brw_BREAK(p);
1839 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1840 break;
1841 case BRW_OPCODE_CONTINUE:
1842 brw_CONT(p);
1843 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1844 break;
1845
1846 case BRW_OPCODE_WHILE:
1847 brw_WHILE(p);
1848 loop_count++;
1849 break;
1850
1851 case SHADER_OPCODE_RCP:
1852 case SHADER_OPCODE_RSQ:
1853 case SHADER_OPCODE_SQRT:
1854 case SHADER_OPCODE_EXP2:
1855 case SHADER_OPCODE_LOG2:
1856 case SHADER_OPCODE_SIN:
1857 case SHADER_OPCODE_COS:
1858 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1859 if (devinfo->gen >= 6) {
1860 assert(inst->mlen == 0);
1861 assert(devinfo->gen >= 7 || inst->exec_size == 8);
1862 gen6_math(p, dst, brw_math_function(inst->opcode),
1863 src[0], brw_null_reg());
1864 } else {
1865 assert(inst->mlen >= 1);
1866 assert(devinfo->gen == 5 || devinfo->is_g4x || inst->exec_size == 8);
1867 gen4_math(p, dst,
1868 brw_math_function(inst->opcode),
1869 inst->base_mrf, src[0],
1870 BRW_MATH_PRECISION_FULL);
1871 }
1872 break;
1873 case SHADER_OPCODE_INT_QUOTIENT:
1874 case SHADER_OPCODE_INT_REMAINDER:
1875 case SHADER_OPCODE_POW:
1876 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1877 if (devinfo->gen >= 6) {
1878 assert(inst->mlen == 0);
1879 assert((devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) ||
1880 inst->exec_size == 8);
1881 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1882 } else {
1883 assert(inst->mlen >= 1);
1884 assert(inst->exec_size == 8);
1885 gen4_math(p, dst, brw_math_function(inst->opcode),
1886 inst->base_mrf, src[0],
1887 BRW_MATH_PRECISION_FULL);
1888 }
1889 break;
1890 case FS_OPCODE_CINTERP:
1891 brw_MOV(p, dst, src[0]);
1892 break;
1893 case FS_OPCODE_LINTERP:
1894 generate_linterp(inst, dst, src);
1895 break;
1896 case FS_OPCODE_PIXEL_X:
1897 assert(src[0].type == BRW_REGISTER_TYPE_UW);
1898 src[0].subnr = 0 * type_sz(src[0].type);
1899 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
1900 break;
1901 case FS_OPCODE_PIXEL_Y:
1902 assert(src[0].type == BRW_REGISTER_TYPE_UW);
1903 src[0].subnr = 4 * type_sz(src[0].type);
1904 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
1905 break;
1906 case FS_OPCODE_GET_BUFFER_SIZE:
1907 generate_get_buffer_size(inst, dst, src[0], src[1]);
1908 break;
1909 case SHADER_OPCODE_TEX:
1910 case FS_OPCODE_TXB:
1911 case SHADER_OPCODE_TXD:
1912 case SHADER_OPCODE_TXF:
1913 case SHADER_OPCODE_TXF_LZ:
1914 case SHADER_OPCODE_TXF_CMS:
1915 case SHADER_OPCODE_TXF_CMS_W:
1916 case SHADER_OPCODE_TXF_UMS:
1917 case SHADER_OPCODE_TXF_MCS:
1918 case SHADER_OPCODE_TXL:
1919 case SHADER_OPCODE_TXL_LZ:
1920 case SHADER_OPCODE_TXS:
1921 case SHADER_OPCODE_LOD:
1922 case SHADER_OPCODE_TG4:
1923 case SHADER_OPCODE_TG4_OFFSET:
1924 case SHADER_OPCODE_SAMPLEINFO:
1925 generate_tex(inst, dst, src[0], src[1], src[2]);
1926 break;
1927 case FS_OPCODE_DDX_COARSE:
1928 case FS_OPCODE_DDX_FINE:
1929 generate_ddx(inst->opcode, dst, src[0]);
1930 break;
1931 case FS_OPCODE_DDY_COARSE:
1932 case FS_OPCODE_DDY_FINE:
1933 generate_ddy(inst->opcode, dst, src[0]);
1934 break;
1935
1936 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1937 generate_scratch_write(inst, src[0]);
1938 spill_count++;
1939 break;
1940
1941 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1942 generate_scratch_read(inst, dst);
1943 fill_count++;
1944 break;
1945
1946 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1947 generate_scratch_read_gen7(inst, dst);
1948 fill_count++;
1949 break;
1950
1951 case SHADER_OPCODE_MOV_INDIRECT:
1952 generate_mov_indirect(inst, dst, src[0], src[1]);
1953 break;
1954
1955 case SHADER_OPCODE_URB_READ_SIMD8:
1956 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1957 generate_urb_read(inst, dst, src[0]);
1958 break;
1959
1960 case SHADER_OPCODE_URB_WRITE_SIMD8:
1961 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1962 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1963 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1964 generate_urb_write(inst, src[0]);
1965 break;
1966
1967 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1968 assert(inst->force_writemask_all);
1969 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1970 break;
1971
1972 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1973 assert(inst->force_writemask_all);
1974 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1975 break;
1976
1977 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
1978 generate_varying_pull_constant_load_gen4(inst, dst, src[0]);
1979 break;
1980
1981 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1982 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1983 break;
1984
1985 case FS_OPCODE_REP_FB_WRITE:
1986 case FS_OPCODE_FB_WRITE:
1987 generate_fb_write(inst, src[0]);
1988 break;
1989
1990 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1991 generate_mov_dispatch_to_flags(inst);
1992 break;
1993
1994 case FS_OPCODE_DISCARD_JUMP:
1995 generate_discard_jump(inst);
1996 break;
1997
1998 case SHADER_OPCODE_SHADER_TIME_ADD:
1999 generate_shader_time_add(inst, src[0], src[1], src[2]);
2000 break;
2001
2002 case SHADER_OPCODE_UNTYPED_ATOMIC:
2003 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2004 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud,
2005 inst->mlen, !inst->dst.is_null());
2006 break;
2007
2008 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2009 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2010 brw_untyped_surface_read(p, dst, src[0], src[1],
2011 inst->mlen, src[2].ud);
2012 break;
2013
2014 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
2015 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2016 brw_untyped_surface_write(p, src[0], src[1],
2017 inst->mlen, src[2].ud);
2018 break;
2019
2020 case SHADER_OPCODE_TYPED_ATOMIC:
2021 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2022 brw_typed_atomic(p, dst, src[0], src[1],
2023 src[2].ud, inst->mlen, !inst->dst.is_null());
2024 break;
2025
2026 case SHADER_OPCODE_TYPED_SURFACE_READ:
2027 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2028 brw_typed_surface_read(p, dst, src[0], src[1],
2029 inst->mlen, src[2].ud);
2030 break;
2031
2032 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
2033 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2034 brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].ud);
2035 break;
2036
2037 case SHADER_OPCODE_MEMORY_FENCE:
2038 brw_memory_fence(p, dst);
2039 break;
2040
2041 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2042 generate_set_simd4x2_offset(inst, dst, src[0]);
2043 break;
2044
2045 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
2046 brw_find_live_channel(p, dst);
2047 break;
2048
2049 case SHADER_OPCODE_BROADCAST:
2050 brw_broadcast(p, dst, src[0], src[1]);
2051 break;
2052
2053 case SHADER_OPCODE_EXTRACT_BYTE: {
2054 assert(src[0].type == BRW_REGISTER_TYPE_D ||
2055 src[0].type == BRW_REGISTER_TYPE_UD);
2056
2057 enum brw_reg_type type =
2058 src[0].type == BRW_REGISTER_TYPE_D ? BRW_REGISTER_TYPE_B
2059 : BRW_REGISTER_TYPE_UB;
2060 brw_MOV(p, dst, spread(suboffset(retype(src[0], type), src[1].ud), 4));
2061 break;
2062 }
2063
2064 case SHADER_OPCODE_EXTRACT_WORD: {
2065 assert(src[0].type == BRW_REGISTER_TYPE_D ||
2066 src[0].type == BRW_REGISTER_TYPE_UD);
2067
2068 enum brw_reg_type type =
2069 src[0].type == BRW_REGISTER_TYPE_D ? BRW_REGISTER_TYPE_W
2070 : BRW_REGISTER_TYPE_UW;
2071 brw_MOV(p, dst, spread(suboffset(retype(src[0], type), src[1].ud), 2));
2072 break;
2073 }
2074
2075 case FS_OPCODE_SET_SAMPLE_ID:
2076 generate_set_sample_id(inst, dst, src[0], src[1]);
2077 break;
2078
2079 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2080 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2081 break;
2082
2083 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2084 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2085 generate_unpack_half_2x16_split(inst, dst, src[0]);
2086 break;
2087
2088 case FS_OPCODE_PLACEHOLDER_HALT:
2089 /* This is the place where the final HALT needs to be inserted if
2090 * we've emitted any discards. If not, this will emit no code.
2091 */
2092 if (!patch_discard_jumps_to_fb_writes()) {
2093 if (unlikely(debug_flag)) {
2094 annotation.ann_count--;
2095 }
2096 }
2097 break;
2098
2099 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2100 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2101 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2102 break;
2103
2104 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2105 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2106 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2107 break;
2108
2109 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2110 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2111 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2112 break;
2113
2114 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2115 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2116 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2117 break;
2118
2119 case CS_OPCODE_CS_TERMINATE:
2120 generate_cs_terminate(inst, src[0]);
2121 break;
2122
2123 case SHADER_OPCODE_BARRIER:
2124 generate_barrier(inst, src[0]);
2125 break;
2126
2127 case FS_OPCODE_PACK_STENCIL_REF:
2128 generate_stencil_ref_packing(inst, dst, src[0]);
2129 break;
2130
2131 default:
2132 unreachable("Unsupported opcode");
2133
2134 case SHADER_OPCODE_LOAD_PAYLOAD:
2135 unreachable("Should be lowered by lower_load_payload()");
2136 }
2137
2138 if (multiple_instructions_emitted)
2139 continue;
2140
2141 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2142 assert(p->next_insn_offset == last_insn_offset + 16 ||
2143 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2144 "emitting more than 1 instruction");
2145
2146 brw_inst *last = &p->store[last_insn_offset / 16];
2147
2148 if (inst->conditional_mod)
2149 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2150 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2151 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2152 }
2153 }
2154
2155 brw_set_uip_jip(p);
2156 annotation_finalize(&annotation, p->next_insn_offset);
2157
2158 #ifndef NDEBUG
2159 bool validated = brw_validate_instructions(p, start_offset, &annotation);
2160 #else
2161 if (unlikely(debug_flag))
2162 brw_validate_instructions(p, start_offset, &annotation);
2163 #endif
2164
2165 int before_size = p->next_insn_offset - start_offset;
2166 brw_compact_instructions(p, start_offset, annotation.ann_count,
2167 annotation.ann);
2168 int after_size = p->next_insn_offset - start_offset;
2169
2170 if (unlikely(debug_flag)) {
2171 fprintf(stderr, "Native code for %s\n"
2172 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2173 " bytes (%.0f%%)\n",
2174 shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
2175 spill_count, fill_count, promoted_constants, before_size, after_size,
2176 100.0f * (before_size - after_size) / before_size);
2177
2178 dump_assembly(p->store, annotation.ann_count, annotation.ann,
2179 p->devinfo);
2180 ralloc_free(annotation.mem_ctx);
2181 }
2182 assert(validated);
2183
2184 compiler->shader_debug_log(log_data,
2185 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2186 "%d:%d spills:fills, Promoted %u constants, "
2187 "compacted %d to %d bytes.",
2188 _mesa_shader_stage_to_abbrev(stage),
2189 dispatch_width, before_size / 16,
2190 loop_count, cfg->cycle_count, spill_count,
2191 fill_count, promoted_constants, before_size,
2192 after_size);
2193
2194 return start_offset;
2195 }
2196
2197 const unsigned *
2198 fs_generator::get_assembly(unsigned int *assembly_size)
2199 {
2200 return brw_get_program(p, assembly_size);
2201 }