2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
31 #include "main/macros.h"
32 #include "brw_context.h"
39 static uint32_t brw_file_from_reg(fs_reg
*reg
)
43 return BRW_GENERAL_REGISTER_FILE
;
45 return BRW_MESSAGE_REGISTER_FILE
;
47 return BRW_IMMEDIATE_VALUE
;
49 unreachable("not reached");
54 brw_reg_from_fs_reg(fs_reg
*reg
)
56 struct brw_reg brw_reg
;
61 if (reg
->stride
== 0) {
62 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
63 } else if (reg
->width
< 8) {
64 brw_reg
= brw_vec8_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
65 brw_reg
= stride(brw_reg
, reg
->width
* reg
->stride
,
66 reg
->width
, reg
->stride
);
68 /* From the Haswell PRM:
70 * VertStride must be used to cross GRF register boundaries. This
71 * rule implies that elements within a 'Width' cannot cross GRF
74 * So, for registers with width > 8, we have to use a width of 8
75 * and trust the compression state to sort out the exec size.
77 brw_reg
= brw_vec8_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
78 brw_reg
= stride(brw_reg
, 8 * reg
->stride
, 8, reg
->stride
);
81 brw_reg
= retype(brw_reg
, reg
->type
);
82 brw_reg
= byte_offset(brw_reg
, reg
->subreg_offset
);
86 case BRW_REGISTER_TYPE_F
:
87 brw_reg
= brw_imm_f(reg
->fixed_hw_reg
.dw1
.f
);
89 case BRW_REGISTER_TYPE_D
:
90 brw_reg
= brw_imm_d(reg
->fixed_hw_reg
.dw1
.d
);
92 case BRW_REGISTER_TYPE_UD
:
93 brw_reg
= brw_imm_ud(reg
->fixed_hw_reg
.dw1
.ud
);
95 case BRW_REGISTER_TYPE_VF
:
96 brw_reg
= brw_imm_vf(reg
->fixed_hw_reg
.dw1
.ud
);
99 unreachable("not reached");
103 assert(reg
->type
== reg
->fixed_hw_reg
.type
);
104 brw_reg
= reg
->fixed_hw_reg
;
107 /* Probably unused. */
108 brw_reg
= brw_null_reg();
111 unreachable("not reached");
114 brw_reg
= brw_abs(brw_reg
);
116 brw_reg
= negate(brw_reg
);
121 fs_generator::fs_generator(struct brw_context
*brw
,
124 struct brw_stage_prog_data
*prog_data
,
125 struct gl_program
*prog
,
126 bool runtime_check_aads_emit
,
127 const char *stage_abbrev
)
129 : brw(brw
), key(key
),
130 prog_data(prog_data
),
131 prog(prog
), runtime_check_aads_emit(runtime_check_aads_emit
),
132 debug_flag(false), stage_abbrev(stage_abbrev
), mem_ctx(mem_ctx
)
136 p
= rzalloc(mem_ctx
, struct brw_compile
);
137 brw_init_compile(brw
, p
, mem_ctx
);
140 fs_generator::~fs_generator()
144 class ip_record
: public exec_node
{
146 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
157 fs_generator::patch_discard_jumps_to_fb_writes()
159 if (brw
->gen
< 6 || this->discard_halt_patches
.is_empty())
162 int scale
= brw_jump_scale(brw
);
164 /* There is a somewhat strange undocumented requirement of using
165 * HALT, according to the simulator. If some channel has HALTed to
166 * a particular UIP, then by the end of the program, every channel
167 * must have HALTed to that UIP. Furthermore, the tracking is a
168 * stack, so you can't do the final halt of a UIP after starting
169 * halting to a new UIP.
171 * Symptoms of not emitting this instruction on actual hardware
172 * included GPU hangs and sparkly rendering on the piglit discard
175 brw_inst
*last_halt
= gen6_HALT(p
);
176 brw_inst_set_uip(brw
, last_halt
, 1 * scale
);
177 brw_inst_set_jip(brw
, last_halt
, 1 * scale
);
181 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
182 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
184 assert(brw_inst_opcode(brw
, patch
) == BRW_OPCODE_HALT
);
185 /* HALT takes a half-instruction distance from the pre-incremented IP. */
186 brw_inst_set_uip(brw
, patch
, (ip
- patch_ip
->ip
) * scale
);
189 this->discard_halt_patches
.make_empty();
194 fs_generator::fire_fb_write(fs_inst
*inst
,
195 struct brw_reg payload
,
196 struct brw_reg implied_header
,
199 uint32_t msg_control
;
201 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
204 brw_push_insn_state(p
);
205 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
206 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
207 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
208 brw_MOV(p
, offset(payload
, 1), brw_vec8_grf(1, 0));
209 brw_pop_insn_state(p
);
212 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
)
213 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
214 else if (prog_data
->dual_src_blend
)
215 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
216 else if (dispatch_width
== 16)
217 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
219 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
221 uint32_t surf_index
=
222 prog_data
->binding_table
.render_target_start
+ inst
->target
;
233 inst
->header_present
);
235 brw_mark_surface_used(&prog_data
->base
, surf_index
);
239 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
241 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
242 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
243 struct brw_reg implied_header
;
245 if (brw
->gen
< 8 && !brw
->is_haswell
) {
246 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
249 if (inst
->base_mrf
>= 0)
250 payload
= brw_message_reg(inst
->base_mrf
);
252 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
255 if (inst
->header_present
) {
256 brw_push_insn_state(p
);
257 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
258 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
259 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
260 brw_set_default_flag_reg(p
, 0, 0);
262 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
265 if (prog_data
->uses_kill
) {
266 struct brw_reg pixel_mask
;
269 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
271 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
273 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
277 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
279 retype(payload
, BRW_REGISTER_TYPE_UD
),
280 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
281 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
283 if (inst
->target
> 0 && key
->replicate_alpha
) {
284 /* Set "Source0 Alpha Present to RenderTarget" bit in message
288 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
289 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
290 brw_imm_ud(0x1 << 11));
293 if (inst
->target
> 0) {
294 /* Set the render target index for choosing BLEND_STATE. */
295 brw_MOV(p
, retype(vec1(suboffset(payload
, 2)),
296 BRW_REGISTER_TYPE_UD
),
297 brw_imm_ud(inst
->target
));
300 implied_header
= brw_null_reg();
302 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
305 brw_pop_insn_state(p
);
307 implied_header
= brw_null_reg();
310 if (!runtime_check_aads_emit
) {
311 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
313 /* This can only happen in gen < 6 */
314 assert(brw
->gen
< 6);
316 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
318 /* Check runtime bit to detect if we have to send AA data or not */
319 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
322 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
324 brw_inst_set_cond_modifier(brw
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
326 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
327 brw_inst_set_exec_size(brw
, brw_last_inst
, BRW_EXECUTE_1
);
329 /* Don't send AA data */
330 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
332 brw_land_fwd_jump(p
, jmp
);
333 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
338 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
342 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
344 brw_set_dest(p
, insn
, brw_null_reg());
345 brw_set_src0(p
, insn
, payload
);
346 brw_set_src1(p
, insn
, brw_imm_d(0));
348 brw_inst_set_sfid(brw
, insn
, BRW_SFID_URB
);
349 brw_inst_set_urb_opcode(brw
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
351 brw_inst_set_mlen(brw
, insn
, inst
->mlen
);
352 brw_inst_set_rlen(brw
, insn
, 0);
353 brw_inst_set_eot(brw
, insn
, inst
->eot
);
354 brw_inst_set_header_present(brw
, insn
, true);
355 brw_inst_set_urb_global_offset(brw
, insn
, inst
->offset
);
359 fs_generator::generate_blorp_fb_write(fs_inst
*inst
)
362 16 /* dispatch_width */,
363 brw_message_reg(inst
->base_mrf
),
364 brw_reg_from_fs_reg(&inst
->src
[0]),
365 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
,
370 inst
->header_present
);
373 /* Computes the integer pixel x,y values from the origin.
375 * This is the basis of gl_FragCoord computation, but is also used
376 * pre-gen6 for computing the deltas from v0 for computing
380 fs_generator::generate_pixel_xy(struct brw_reg dst
, bool is_x
)
382 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
384 struct brw_reg deltas
;
387 src
= stride(suboffset(g1_uw
, 4), 2, 4, 0);
388 deltas
= brw_imm_v(0x10101010);
390 src
= stride(suboffset(g1_uw
, 5), 2, 4, 0);
391 deltas
= brw_imm_v(0x11001100);
394 if (dispatch_width
== 16) {
398 /* We do this SIMD8 or SIMD16, but since the destination is UW we
399 * don't do compression in the SIMD16 case.
401 brw_push_insn_state(p
);
402 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
403 brw_ADD(p
, dst
, src
, deltas
);
404 brw_pop_insn_state(p
);
408 fs_generator::generate_linterp(fs_inst
*inst
,
409 struct brw_reg dst
, struct brw_reg
*src
)
411 struct brw_reg delta_x
= src
[0];
412 struct brw_reg delta_y
= src
[1];
413 struct brw_reg interp
= src
[2];
416 delta_y
.nr
== delta_x
.nr
+ 1 &&
417 (brw
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
418 brw_PLN(p
, dst
, interp
, delta_x
);
420 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
421 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
426 fs_generator::generate_math_gen6(fs_inst
*inst
,
431 int op
= brw_math_function(inst
->opcode
);
432 bool binop
= src1
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
;
434 if (dispatch_width
== 8) {
435 gen6_math(p
, dst
, op
, src0
, src1
);
436 } else if (dispatch_width
== 16) {
437 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
438 gen6_math(p
, firsthalf(dst
), op
, firsthalf(src0
), firsthalf(src1
));
439 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
440 gen6_math(p
, sechalf(dst
), op
, sechalf(src0
),
441 binop
? sechalf(src1
) : brw_null_reg());
442 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
447 fs_generator::generate_math_gen4(fs_inst
*inst
,
451 int op
= brw_math_function(inst
->opcode
);
453 assert(inst
->mlen
>= 1);
455 if (dispatch_width
== 8) {
459 BRW_MATH_PRECISION_FULL
);
460 } else if (dispatch_width
== 16) {
461 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
462 gen4_math(p
, firsthalf(dst
),
464 inst
->base_mrf
, firsthalf(src
),
465 BRW_MATH_PRECISION_FULL
);
466 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
467 gen4_math(p
, sechalf(dst
),
469 inst
->base_mrf
+ 1, sechalf(src
),
470 BRW_MATH_PRECISION_FULL
);
472 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
477 fs_generator::generate_math_g45(fs_inst
*inst
,
481 if (inst
->opcode
== SHADER_OPCODE_POW
||
482 inst
->opcode
== SHADER_OPCODE_INT_QUOTIENT
||
483 inst
->opcode
== SHADER_OPCODE_INT_REMAINDER
) {
484 generate_math_gen4(inst
, dst
, src
);
488 int op
= brw_math_function(inst
->opcode
);
490 assert(inst
->mlen
>= 1);
495 BRW_MATH_PRECISION_FULL
);
499 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
500 struct brw_reg sampler_index
)
505 uint32_t return_format
;
508 case BRW_REGISTER_TYPE_D
:
509 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
511 case BRW_REGISTER_TYPE_UD
:
512 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
515 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
519 switch (inst
->exec_size
) {
521 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
524 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
527 unreachable("Invalid width for texture instruction");
531 switch (inst
->opcode
) {
532 case SHADER_OPCODE_TEX
:
533 if (inst
->shadow_compare
) {
534 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
536 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
540 if (inst
->shadow_compare
) {
541 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
543 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
546 case SHADER_OPCODE_TXL
:
547 if (inst
->shadow_compare
) {
548 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
550 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
553 case SHADER_OPCODE_TXS
:
554 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
556 case SHADER_OPCODE_TXD
:
557 if (inst
->shadow_compare
) {
558 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
559 assert(brw
->gen
>= 8 || brw
->is_haswell
);
560 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
562 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
565 case SHADER_OPCODE_TXF
:
566 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
568 case SHADER_OPCODE_TXF_CMS
:
570 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
572 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
574 case SHADER_OPCODE_TXF_UMS
:
575 assert(brw
->gen
>= 7);
576 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
578 case SHADER_OPCODE_TXF_MCS
:
579 assert(brw
->gen
>= 7);
580 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
582 case SHADER_OPCODE_LOD
:
583 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
585 case SHADER_OPCODE_TG4
:
586 if (inst
->shadow_compare
) {
587 assert(brw
->gen
>= 7);
588 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
590 assert(brw
->gen
>= 6);
591 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
594 case SHADER_OPCODE_TG4_OFFSET
:
595 assert(brw
->gen
>= 7);
596 if (inst
->shadow_compare
) {
597 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
599 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
603 unreachable("not reached");
606 switch (inst
->opcode
) {
607 case SHADER_OPCODE_TEX
:
608 /* Note that G45 and older determines shadow compare and dispatch width
609 * from message length for most messages.
611 assert(dispatch_width
== 8);
612 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
613 if (inst
->shadow_compare
) {
614 assert(inst
->mlen
== 6);
616 assert(inst
->mlen
<= 4);
620 if (inst
->shadow_compare
) {
621 assert(inst
->mlen
== 6);
622 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
624 assert(inst
->mlen
== 9);
625 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
626 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
629 case SHADER_OPCODE_TXL
:
630 if (inst
->shadow_compare
) {
631 assert(inst
->mlen
== 6);
632 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
634 assert(inst
->mlen
== 9);
635 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
636 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
639 case SHADER_OPCODE_TXD
:
640 /* There is no sample_d_c message; comparisons are done manually */
641 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
642 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
644 case SHADER_OPCODE_TXF
:
645 assert(inst
->mlen
== 9);
646 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
647 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
649 case SHADER_OPCODE_TXS
:
650 assert(inst
->mlen
== 3);
651 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
652 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
655 unreachable("not reached");
658 assert(msg_type
!= -1);
660 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
665 assert(brw
->gen
< 7 || !inst
->header_present
||
666 src
.file
== BRW_GENERAL_REGISTER_FILE
);
668 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
670 /* Load the message header if present. If there's a texture offset,
671 * we need to set it up explicitly and load the offset bitfield.
672 * Otherwise, we can use an implied move from g0 to the first message reg.
674 if (inst
->header_present
) {
675 if (brw
->gen
< 6 && !inst
->offset
) {
676 /* Set up an implied move from g0 to the MRF. */
677 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
679 struct brw_reg header_reg
;
684 assert(inst
->base_mrf
!= -1);
685 header_reg
= brw_message_reg(inst
->base_mrf
);
688 brw_push_insn_state(p
);
689 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
690 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
691 /* Explicitly set up the message header by copying g0 to the MRF. */
692 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
695 /* Set the offset bits in DWord 2. */
696 brw_MOV(p
, get_element_ud(header_reg
, 2),
697 brw_imm_ud(inst
->offset
));
700 brw_adjust_sampler_state_pointer(p
, header_reg
, sampler_index
, dst
);
701 brw_pop_insn_state(p
);
705 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
706 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
707 ? prog_data
->binding_table
.gather_texture_start
708 : prog_data
->binding_table
.texture_start
;
710 if (sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
711 uint32_t sampler
= sampler_index
.dw1
.ud
;
714 retype(dst
, BRW_REGISTER_TYPE_UW
),
717 sampler
+ base_binding_table_index
,
722 inst
->header_present
,
726 brw_mark_surface_used(prog_data
, sampler
+ base_binding_table_index
);
728 /* Non-const sampler index */
729 /* Note: this clobbers `dst` as a temporary before emitting the send */
731 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
732 struct brw_reg temp
= vec1(retype(dst
, BRW_REGISTER_TYPE_UD
));
734 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
736 brw_push_insn_state(p
);
737 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
738 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
740 /* Some care required: `sampler` and `temp` may alias:
741 * addr = sampler & 0xff
742 * temp = (sampler << 8) & 0xf00
745 brw_ADD(p
, addr
, sampler_reg
, brw_imm_ud(base_binding_table_index
));
746 brw_SHL(p
, temp
, sampler_reg
, brw_imm_ud(8u));
747 brw_AND(p
, temp
, temp
, brw_imm_ud(0x0f00));
748 brw_AND(p
, addr
, addr
, brw_imm_ud(0x0ff));
749 brw_OR(p
, addr
, addr
, temp
);
751 /* a0.0 |= <descriptor> */
752 brw_inst
*insn_or
= brw_next_insn(p
, BRW_OPCODE_OR
);
753 brw_set_sampler_message(p
, insn_or
,
758 inst
->mlen
/* mlen */,
759 inst
->header_present
/* header */,
762 brw_inst_set_exec_size(p
->brw
, insn_or
, BRW_EXECUTE_1
);
763 brw_inst_set_src1_reg_type(p
->brw
, insn_or
, BRW_REGISTER_TYPE_UD
);
764 brw_set_src0(p
, insn_or
, addr
);
765 brw_set_dest(p
, insn_or
, addr
);
768 /* dst = send(offset, a0.0) */
769 brw_inst
*insn_send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
770 brw_set_dest(p
, insn_send
, dst
);
771 brw_set_src0(p
, insn_send
, src
);
772 brw_set_indirect_send_descriptor(p
, insn_send
, BRW_SFID_SAMPLER
, addr
);
774 brw_pop_insn_state(p
);
776 /* visitor knows more than we do about the surface limit required,
777 * so has already done marking.
783 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
786 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
788 * Ideally, we want to produce:
791 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
792 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
793 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
794 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
795 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
796 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
797 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
798 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
800 * and add another set of two more subspans if in 16-pixel dispatch mode.
802 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
803 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
804 * pair. But the ideal approximation may impose a huge performance cost on
805 * sample_d. On at least Haswell, sample_d instruction does some
806 * optimizations if the same LOD is used for all pixels in the subspan.
808 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
809 * appropriate swizzling.
812 fs_generator::generate_ddx(enum opcode opcode
,
813 struct brw_reg dst
, struct brw_reg src
)
815 unsigned vstride
, width
;
817 if (opcode
== FS_OPCODE_DDX_FINE
) {
818 /* produce accurate derivatives */
819 vstride
= BRW_VERTICAL_STRIDE_2
;
822 /* replicate the derivative at the top-left pixel to other pixels */
823 vstride
= BRW_VERTICAL_STRIDE_4
;
827 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
832 BRW_HORIZONTAL_STRIDE_0
,
833 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
834 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
839 BRW_HORIZONTAL_STRIDE_0
,
840 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
841 brw_ADD(p
, dst
, src0
, negate(src1
));
844 /* The negate_value boolean is used to negate the derivative computation for
845 * FBOs, since they place the origin at the upper left instead of the lower
849 fs_generator::generate_ddy(enum opcode opcode
,
850 struct brw_reg dst
, struct brw_reg src
,
853 if (opcode
== FS_OPCODE_DDY_FINE
) {
854 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
855 * Region Restrictions):
857 * In Align16 access mode, SIMD16 is not allowed for DW operations
858 * and SIMD8 is not allowed for DF operations.
860 * In this context, "DW operations" means "operations acting on 32-bit
861 * values", so it includes operations on floats.
863 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
864 * (Instruction Compression -> Rules and Restrictions):
866 * A compressed instruction must be in Align1 access mode. Align16
867 * mode instructions cannot be compressed.
869 * Similar text exists in the g45 PRM.
871 * On these platforms, if we're building a SIMD16 shader, we need to
872 * manually unroll to a pair of SIMD8 instructions.
874 bool unroll_to_simd8
=
875 (dispatch_width
== 16 &&
876 (brw
->gen
== 4 || (brw
->gen
== 7 && !brw
->is_haswell
)));
878 /* produce accurate derivatives */
879 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
882 BRW_VERTICAL_STRIDE_4
,
884 BRW_HORIZONTAL_STRIDE_1
,
885 BRW_SWIZZLE_XYXY
, WRITEMASK_XYZW
);
886 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
889 BRW_VERTICAL_STRIDE_4
,
891 BRW_HORIZONTAL_STRIDE_1
,
892 BRW_SWIZZLE_ZWZW
, WRITEMASK_XYZW
);
893 brw_push_insn_state(p
);
894 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
895 if (unroll_to_simd8
) {
896 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
898 brw_ADD(p
, firsthalf(dst
), firsthalf(src1
), negate(firsthalf(src0
)));
899 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
900 brw_ADD(p
, sechalf(dst
), sechalf(src1
), negate(sechalf(src0
)));
902 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), negate(firsthalf(src1
)));
903 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
904 brw_ADD(p
, sechalf(dst
), sechalf(src0
), negate(sechalf(src1
)));
908 brw_ADD(p
, dst
, src1
, negate(src0
));
910 brw_ADD(p
, dst
, src0
, negate(src1
));
912 brw_pop_insn_state(p
);
914 /* replicate the derivative at the top-left pixel to other pixels */
915 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
918 BRW_VERTICAL_STRIDE_4
,
920 BRW_HORIZONTAL_STRIDE_0
,
921 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
922 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
925 BRW_VERTICAL_STRIDE_4
,
927 BRW_HORIZONTAL_STRIDE_0
,
928 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
930 brw_ADD(p
, dst
, src1
, negate(src0
));
932 brw_ADD(p
, dst
, src0
, negate(src1
));
937 fs_generator::generate_discard_jump(fs_inst
*inst
)
939 assert(brw
->gen
>= 6);
941 /* This HALT will be patched up at FB write time to point UIP at the end of
942 * the program, and at brw_uip_jip() JIP will be set to the end of the
943 * current block (or the program).
945 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
947 brw_push_insn_state(p
);
948 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
950 brw_pop_insn_state(p
);
954 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
956 assert(inst
->mlen
!= 0);
959 brw_uvec_mrf(inst
->exec_size
, (inst
->base_mrf
+ 1), 0),
960 retype(src
, BRW_REGISTER_TYPE_UD
));
961 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
962 inst
->exec_size
/ 8, inst
->offset
);
966 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
968 assert(inst
->mlen
!= 0);
970 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
971 inst
->exec_size
/ 8, inst
->offset
);
975 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
977 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
981 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
983 struct brw_reg index
,
984 struct brw_reg offset
)
986 assert(inst
->mlen
!= 0);
988 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
989 index
.type
== BRW_REGISTER_TYPE_UD
);
990 uint32_t surf_index
= index
.dw1
.ud
;
992 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
993 offset
.type
== BRW_REGISTER_TYPE_UD
);
994 uint32_t read_offset
= offset
.dw1
.ud
;
996 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
997 read_offset
, surf_index
);
999 brw_mark_surface_used(prog_data
, surf_index
);
1003 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1005 struct brw_reg index
,
1006 struct brw_reg offset
)
1008 assert(inst
->mlen
== 0);
1009 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1011 assert(offset
.file
== BRW_GENERAL_REGISTER_FILE
);
1012 /* Reference just the dword we need, to avoid angering validate_reg(). */
1013 offset
= brw_vec1_grf(offset
.nr
, 0);
1015 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1016 * the destination loaded consecutively from the same offset (which appears
1017 * in the first component, and the rest are ignored).
1019 dst
.width
= BRW_WIDTH_4
;
1021 struct brw_reg src
= offset
;
1022 bool header_present
= false;
1025 if (brw
->gen
>= 9) {
1026 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1027 src
= retype(brw_vec8_grf(offset
.nr
- 1, 0), BRW_REGISTER_TYPE_UD
);
1029 header_present
= true;
1031 brw_push_insn_state(p
);
1032 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1033 brw_MOV(p
, src
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1034 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1036 brw_MOV(p
, get_element_ud(src
, 2),
1037 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
));
1038 brw_pop_insn_state(p
);
1041 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1043 uint32_t surf_index
= index
.dw1
.ud
;
1045 brw_push_insn_state(p
);
1046 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1047 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1048 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1049 brw_pop_insn_state(p
);
1051 brw_set_dest(p
, send
, dst
);
1052 brw_set_src0(p
, send
, src
);
1053 brw_set_sampler_message(p
, send
,
1055 0, /* LD message ignores sampler unit */
1056 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1060 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1063 brw_mark_surface_used(prog_data
, surf_index
);
1067 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1069 brw_push_insn_state(p
);
1070 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1071 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1073 /* a0.0 = surf_index & 0xff */
1074 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1075 brw_inst_set_exec_size(p
->brw
, insn_and
, BRW_EXECUTE_1
);
1076 brw_set_dest(p
, insn_and
, addr
);
1077 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1078 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1081 /* a0.0 |= <descriptor> */
1082 brw_inst
*insn_or
= brw_next_insn(p
, BRW_OPCODE_OR
);
1083 brw_set_sampler_message(p
, insn_or
,
1086 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1090 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1092 brw_inst_set_exec_size(p
->brw
, insn_or
, BRW_EXECUTE_1
);
1093 brw_inst_set_src1_reg_type(p
->brw
, insn_or
, BRW_REGISTER_TYPE_UD
);
1094 brw_set_src0(p
, insn_or
, addr
);
1095 brw_set_dest(p
, insn_or
, addr
);
1098 /* dst = send(offset, a0.0) */
1099 brw_inst
*insn_send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1100 brw_set_dest(p
, insn_send
, dst
);
1101 brw_set_src0(p
, insn_send
, src
);
1102 brw_set_indirect_send_descriptor(p
, insn_send
, BRW_SFID_SAMPLER
, addr
);
1104 brw_pop_insn_state(p
);
1106 /* visitor knows more than we do about the surface limit required,
1107 * so has already done marking.
1114 fs_generator::generate_varying_pull_constant_load(fs_inst
*inst
,
1116 struct brw_reg index
,
1117 struct brw_reg offset
)
1119 assert(brw
->gen
< 7); /* Should use the gen7 variant. */
1120 assert(inst
->header_present
);
1123 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1124 index
.type
== BRW_REGISTER_TYPE_UD
);
1125 uint32_t surf_index
= index
.dw1
.ud
;
1127 uint32_t simd_mode
, rlen
, msg_type
;
1128 if (dispatch_width
== 16) {
1129 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1132 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1137 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1139 /* We always use the SIMD16 message so that we only have to load U, and
1142 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1143 assert(inst
->mlen
== 3);
1144 assert(inst
->regs_written
== 8);
1146 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1149 struct brw_reg offset_mrf
= retype(brw_message_reg(inst
->base_mrf
+ 1),
1150 BRW_REGISTER_TYPE_D
);
1151 brw_MOV(p
, offset_mrf
, offset
);
1153 struct brw_reg header
= brw_vec8_grf(0, 0);
1154 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1156 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1157 brw_inst_set_qtr_control(brw
, send
, BRW_COMPRESSION_NONE
);
1158 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1159 brw_set_src0(p
, send
, header
);
1161 brw_inst_set_base_mrf(brw
, send
, inst
->base_mrf
);
1163 /* Our surface is set up as floats, regardless of what actual data is
1166 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1167 brw_set_sampler_message(p
, send
,
1169 0, /* sampler (unused) */
1173 inst
->header_present
,
1177 brw_mark_surface_used(prog_data
, surf_index
);
1181 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1183 struct brw_reg index
,
1184 struct brw_reg offset
)
1186 assert(brw
->gen
>= 7);
1187 /* Varying-offset pull constant loads are treated as a normal expression on
1188 * gen7, so the fact that it's a send message is hidden at the IR level.
1190 assert(!inst
->header_present
);
1191 assert(!inst
->mlen
);
1192 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1194 uint32_t simd_mode
, rlen
, mlen
;
1195 if (dispatch_width
== 16) {
1198 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1202 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1205 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1207 uint32_t surf_index
= index
.dw1
.ud
;
1209 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1210 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1211 brw_set_src0(p
, send
, offset
);
1212 brw_set_sampler_message(p
, send
,
1214 0, /* LD message ignores sampler unit */
1215 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1218 false, /* no header */
1222 brw_mark_surface_used(prog_data
, surf_index
);
1226 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1228 brw_push_insn_state(p
);
1229 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1230 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1232 /* a0.0 = surf_index & 0xff */
1233 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1234 brw_inst_set_exec_size(p
->brw
, insn_and
, BRW_EXECUTE_1
);
1235 brw_set_dest(p
, insn_and
, addr
);
1236 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1237 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1240 /* a0.0 |= <descriptor> */
1241 brw_inst
*insn_or
= brw_next_insn(p
, BRW_OPCODE_OR
);
1242 brw_set_sampler_message(p
, insn_or
,
1245 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1251 brw_inst_set_exec_size(p
->brw
, insn_or
, BRW_EXECUTE_1
);
1252 brw_inst_set_src1_reg_type(p
->brw
, insn_or
, BRW_REGISTER_TYPE_UD
);
1253 brw_set_src0(p
, insn_or
, addr
);
1254 brw_set_dest(p
, insn_or
, addr
);
1257 /* dst = send(offset, a0.0) */
1258 brw_inst
*insn_send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1259 brw_set_dest(p
, insn_send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1260 brw_set_src0(p
, insn_send
, offset
);
1261 brw_set_indirect_send_descriptor(p
, insn_send
, BRW_SFID_SAMPLER
, addr
);
1263 brw_pop_insn_state(p
);
1265 /* visitor knows more than we do about the surface limit required,
1266 * so has already done marking.
1272 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1273 * into the flags register (f0.0).
1275 * Used only on Gen6 and above.
1278 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
1280 struct brw_reg flags
= brw_flag_reg(0, inst
->flag_subreg
);
1281 struct brw_reg dispatch_mask
;
1284 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1286 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1288 brw_push_insn_state(p
);
1289 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1290 brw_MOV(p
, flags
, dispatch_mask
);
1291 brw_pop_insn_state(p
);
1295 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1298 struct brw_reg msg_data
,
1301 assert(msg_data
.file
== BRW_IMMEDIATE_VALUE
&&
1302 msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1304 brw_pixel_interpolator_query(p
,
1305 retype(dst
, BRW_REGISTER_TYPE_UW
),
1307 inst
->pi_noperspective
,
1311 inst
->regs_written
);
1316 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1317 * sampler LD messages.
1319 * We don't want to bake it into the send message's code generation because
1320 * that means we don't get a chance to schedule the instructions.
1323 fs_generator::generate_set_simd4x2_offset(fs_inst
*inst
,
1325 struct brw_reg value
)
1327 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1329 brw_push_insn_state(p
);
1330 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1331 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1332 brw_MOV(p
, retype(brw_vec1_reg(dst
.file
, dst
.nr
, 0), value
.type
), value
);
1333 brw_pop_insn_state(p
);
1336 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1337 * (when mask is passed as a uniform) of register mask before moving it
1341 fs_generator::generate_set_omask(fs_inst
*inst
,
1343 struct brw_reg mask
)
1346 (mask
.vstride
== BRW_VERTICAL_STRIDE_8
&&
1347 mask
.width
== BRW_WIDTH_8
&&
1348 mask
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
1351 (mask
.vstride
== BRW_VERTICAL_STRIDE_0
&&
1352 mask
.width
== BRW_WIDTH_1
&&
1353 mask
.hstride
== BRW_HORIZONTAL_STRIDE_0
);
1355 assert(stride_8_8_1
|| stride_0_1_0
);
1356 assert(dst
.type
== BRW_REGISTER_TYPE_UW
);
1358 if (dispatch_width
== 16)
1360 brw_push_insn_state(p
);
1361 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1362 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1365 brw_MOV(p
, dst
, retype(stride(mask
, 16, 8, 2), dst
.type
));
1366 } else if (stride_0_1_0
) {
1367 brw_MOV(p
, dst
, retype(mask
, dst
.type
));
1369 brw_pop_insn_state(p
);
1372 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1373 * the ADD instruction.
1376 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1378 struct brw_reg src0
,
1379 struct brw_reg src1
)
1381 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1382 dst
.type
== BRW_REGISTER_TYPE_UD
);
1383 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1384 src0
.type
== BRW_REGISTER_TYPE_UD
);
1386 brw_push_insn_state(p
);
1387 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1388 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1389 struct brw_reg reg
= retype(stride(src1
, 1, 4, 0), BRW_REGISTER_TYPE_UW
);
1390 if (dispatch_width
== 8) {
1391 brw_ADD(p
, dst
, src0
, reg
);
1392 } else if (dispatch_width
== 16) {
1393 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), reg
);
1394 brw_ADD(p
, sechalf(dst
), sechalf(src0
), suboffset(reg
, 2));
1396 brw_pop_insn_state(p
);
1400 * Change the register's data type from UD to W, doubling the strides in order
1401 * to compensate for halving the data type width.
1403 static struct brw_reg
1404 ud_reg_to_w(struct brw_reg r
)
1406 assert(r
.type
== BRW_REGISTER_TYPE_UD
);
1407 r
.type
= BRW_REGISTER_TYPE_W
;
1409 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1410 * doubles the real stride.
1421 fs_generator::generate_pack_half_2x16_split(fs_inst
*inst
,
1426 assert(brw
->gen
>= 7);
1427 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1428 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1429 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1431 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1433 * Because this instruction does not have a 16-bit floating-point type,
1434 * the destination data type must be Word (W).
1436 * The destination must be DWord-aligned and specify a horizontal stride
1437 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1438 * each destination channel and the upper word is not modified.
1440 struct brw_reg dst_w
= ud_reg_to_w(dst
);
1442 /* Give each 32-bit channel of dst the form below , where "." means
1446 brw_F32TO16(p
, dst_w
, y
);
1451 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1453 /* And, finally the form of packHalf2x16's output:
1456 brw_F32TO16(p
, dst_w
, x
);
1460 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
1464 assert(brw
->gen
>= 7);
1465 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1466 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1468 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1470 * Because this instruction does not have a 16-bit floating-point type,
1471 * the source data type must be Word (W). The destination type must be
1474 struct brw_reg src_w
= ud_reg_to_w(src
);
1476 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1477 * For the Y case, we wish to access only the upper word; therefore
1478 * a 16-bit subregister offset is needed.
1480 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1481 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1482 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1485 brw_F16TO32(p
, dst
, src_w
);
1489 fs_generator::generate_shader_time_add(fs_inst
*inst
,
1490 struct brw_reg payload
,
1491 struct brw_reg offset
,
1492 struct brw_reg value
)
1494 assert(brw
->gen
>= 7);
1495 brw_push_insn_state(p
);
1496 brw_set_default_mask_control(p
, true);
1498 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1499 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1501 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1504 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1505 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1506 value
.width
= BRW_WIDTH_1
;
1507 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1508 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1510 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1513 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1514 * case, and we don't really care about squeezing every bit of performance
1515 * out of this path, so we just emit the MOVs from here.
1517 brw_MOV(p
, payload_offset
, offset
);
1518 brw_MOV(p
, payload_value
, value
);
1519 brw_shader_time_add(p
, payload
,
1520 prog_data
->binding_table
.shader_time_start
);
1521 brw_pop_insn_state(p
);
1523 brw_mark_surface_used(prog_data
,
1524 prog_data
->binding_table
.shader_time_start
);
1528 fs_generator::generate_untyped_atomic(fs_inst
*inst
, struct brw_reg dst
,
1529 struct brw_reg payload
,
1530 struct brw_reg atomic_op
,
1531 struct brw_reg surf_index
)
1533 assert(atomic_op
.file
== BRW_IMMEDIATE_VALUE
&&
1534 atomic_op
.type
== BRW_REGISTER_TYPE_UD
&&
1535 surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
1536 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
1538 brw_untyped_atomic(p
, dst
, payload
, atomic_op
.dw1
.ud
, surf_index
.dw1
.ud
,
1539 inst
->mlen
, inst
->exec_size
/ 8);
1541 brw_mark_surface_used(prog_data
, surf_index
.dw1
.ud
);
1545 fs_generator::generate_untyped_surface_read(fs_inst
*inst
, struct brw_reg dst
,
1546 struct brw_reg payload
,
1547 struct brw_reg surf_index
)
1549 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
1550 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
1552 brw_untyped_surface_read(p
, dst
, payload
,
1554 inst
->mlen
, inst
->exec_size
/ 8);
1556 brw_mark_surface_used(prog_data
, surf_index
.dw1
.ud
);
1560 fs_generator::enable_debug(const char *shader_name
)
1563 this->shader_name
= shader_name
;
1567 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1569 /* align to 64 byte boundary. */
1570 while (p
->next_insn_offset
% 64)
1573 this->dispatch_width
= dispatch_width
;
1574 if (dispatch_width
== 16)
1575 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1577 int start_offset
= p
->next_insn_offset
;
1580 struct annotation_info annotation
;
1581 memset(&annotation
, 0, sizeof(annotation
));
1583 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1584 struct brw_reg src
[3], dst
;
1585 unsigned int last_insn_offset
= p
->next_insn_offset
;
1587 if (unlikely(debug_flag
))
1588 annotate(brw
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1590 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1591 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
1593 /* The accumulator result appears to get used for the
1594 * conditional modifier generation. When negating a UD
1595 * value, there is a 33rd bit generated for the sign in the
1596 * accumulator value, so now you can't check, for example,
1597 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1599 assert(!inst
->conditional_mod
||
1600 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1601 !inst
->src
[i
].negate
);
1603 dst
= brw_reg_from_fs_reg(&inst
->dst
);
1605 brw_set_default_predicate_control(p
, inst
->predicate
);
1606 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1607 brw_set_default_flag_reg(p
, 0, inst
->flag_subreg
);
1608 brw_set_default_saturate(p
, inst
->saturate
);
1609 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1610 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1612 switch (inst
->exec_size
) {
1616 assert(inst
->force_writemask_all
);
1617 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1620 if (inst
->force_sechalf
) {
1621 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1623 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1627 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1630 unreachable(!"Invalid instruction width");
1633 switch (inst
->opcode
) {
1634 case BRW_OPCODE_MOV
:
1635 brw_MOV(p
, dst
, src
[0]);
1637 case BRW_OPCODE_ADD
:
1638 brw_ADD(p
, dst
, src
[0], src
[1]);
1640 case BRW_OPCODE_MUL
:
1641 brw_MUL(p
, dst
, src
[0], src
[1]);
1643 case BRW_OPCODE_AVG
:
1644 brw_AVG(p
, dst
, src
[0], src
[1]);
1646 case BRW_OPCODE_MACH
:
1647 brw_MACH(p
, dst
, src
[0], src
[1]);
1650 case BRW_OPCODE_LINE
:
1651 brw_LINE(p
, dst
, src
[0], src
[1]);
1654 case BRW_OPCODE_MAD
:
1655 assert(brw
->gen
>= 6);
1656 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1657 if (dispatch_width
== 16 && brw
->gen
< 8 && !brw
->is_haswell
) {
1658 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1659 brw_MAD(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1660 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1661 brw_MAD(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1662 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1664 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1666 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1669 case BRW_OPCODE_LRP
:
1670 assert(brw
->gen
>= 6);
1671 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1672 if (dispatch_width
== 16 && brw
->gen
< 8 && !brw
->is_haswell
) {
1673 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1674 brw_LRP(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1675 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1676 brw_LRP(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1677 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1679 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1681 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1684 case BRW_OPCODE_FRC
:
1685 brw_FRC(p
, dst
, src
[0]);
1687 case BRW_OPCODE_RNDD
:
1688 brw_RNDD(p
, dst
, src
[0]);
1690 case BRW_OPCODE_RNDE
:
1691 brw_RNDE(p
, dst
, src
[0]);
1693 case BRW_OPCODE_RNDZ
:
1694 brw_RNDZ(p
, dst
, src
[0]);
1697 case BRW_OPCODE_AND
:
1698 brw_AND(p
, dst
, src
[0], src
[1]);
1701 brw_OR(p
, dst
, src
[0], src
[1]);
1703 case BRW_OPCODE_XOR
:
1704 brw_XOR(p
, dst
, src
[0], src
[1]);
1706 case BRW_OPCODE_NOT
:
1707 brw_NOT(p
, dst
, src
[0]);
1709 case BRW_OPCODE_ASR
:
1710 brw_ASR(p
, dst
, src
[0], src
[1]);
1712 case BRW_OPCODE_SHR
:
1713 brw_SHR(p
, dst
, src
[0], src
[1]);
1715 case BRW_OPCODE_SHL
:
1716 brw_SHL(p
, dst
, src
[0], src
[1]);
1718 case BRW_OPCODE_F32TO16
:
1719 assert(brw
->gen
>= 7);
1720 brw_F32TO16(p
, dst
, src
[0]);
1722 case BRW_OPCODE_F16TO32
:
1723 assert(brw
->gen
>= 7);
1724 brw_F16TO32(p
, dst
, src
[0]);
1726 case BRW_OPCODE_CMP
:
1727 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1729 case BRW_OPCODE_SEL
:
1730 brw_SEL(p
, dst
, src
[0], src
[1]);
1732 case BRW_OPCODE_BFREV
:
1733 assert(brw
->gen
>= 7);
1734 /* BFREV only supports UD type for src and dst. */
1735 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1736 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1738 case BRW_OPCODE_FBH
:
1739 assert(brw
->gen
>= 7);
1740 /* FBH only supports UD type for dst. */
1741 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1743 case BRW_OPCODE_FBL
:
1744 assert(brw
->gen
>= 7);
1745 /* FBL only supports UD type for dst. */
1746 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1748 case BRW_OPCODE_CBIT
:
1749 assert(brw
->gen
>= 7);
1750 /* CBIT only supports UD type for dst. */
1751 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1753 case BRW_OPCODE_ADDC
:
1754 assert(brw
->gen
>= 7);
1755 brw_ADDC(p
, dst
, src
[0], src
[1]);
1757 case BRW_OPCODE_SUBB
:
1758 assert(brw
->gen
>= 7);
1759 brw_SUBB(p
, dst
, src
[0], src
[1]);
1761 case BRW_OPCODE_MAC
:
1762 brw_MAC(p
, dst
, src
[0], src
[1]);
1765 case BRW_OPCODE_BFE
:
1766 assert(brw
->gen
>= 7);
1767 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1768 if (dispatch_width
== 16 && brw
->gen
< 8 && !brw
->is_haswell
) {
1769 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1770 brw_BFE(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1771 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1772 brw_BFE(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1773 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1775 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1777 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1780 case BRW_OPCODE_BFI1
:
1781 assert(brw
->gen
>= 7);
1782 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1785 * "Force BFI instructions to be executed always in SIMD8."
1787 if (dispatch_width
== 16 && brw
->is_haswell
) {
1788 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1789 brw_BFI1(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]));
1790 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1791 brw_BFI1(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]));
1792 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1794 brw_BFI1(p
, dst
, src
[0], src
[1]);
1797 case BRW_OPCODE_BFI2
:
1798 assert(brw
->gen
>= 7);
1799 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1800 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1803 * "Force BFI instructions to be executed always in SIMD8."
1805 * Otherwise we would be able to emit compressed instructions like we
1806 * do for the other three-source instructions.
1808 if (dispatch_width
== 16 && brw
->gen
< 8) {
1809 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1810 brw_BFI2(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1811 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1812 brw_BFI2(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1813 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1815 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1817 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1821 if (inst
->src
[0].file
!= BAD_FILE
) {
1822 /* The instruction has an embedded compare (only allowed on gen6) */
1823 assert(brw
->gen
== 6);
1824 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1826 brw_IF(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
1830 case BRW_OPCODE_ELSE
:
1833 case BRW_OPCODE_ENDIF
:
1838 brw_DO(p
, BRW_EXECUTE_8
);
1841 case BRW_OPCODE_BREAK
:
1843 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1845 case BRW_OPCODE_CONTINUE
:
1847 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1850 case BRW_OPCODE_WHILE
:
1855 case SHADER_OPCODE_RCP
:
1856 case SHADER_OPCODE_RSQ
:
1857 case SHADER_OPCODE_SQRT
:
1858 case SHADER_OPCODE_EXP2
:
1859 case SHADER_OPCODE_LOG2
:
1860 case SHADER_OPCODE_SIN
:
1861 case SHADER_OPCODE_COS
:
1862 assert(brw
->gen
< 6 || inst
->mlen
== 0);
1863 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1864 if (brw
->gen
>= 7) {
1865 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
1867 } else if (brw
->gen
== 6) {
1868 generate_math_gen6(inst
, dst
, src
[0], brw_null_reg());
1869 } else if (brw
->gen
== 5 || brw
->is_g4x
) {
1870 generate_math_g45(inst
, dst
, src
[0]);
1872 generate_math_gen4(inst
, dst
, src
[0]);
1875 case SHADER_OPCODE_INT_QUOTIENT
:
1876 case SHADER_OPCODE_INT_REMAINDER
:
1877 case SHADER_OPCODE_POW
:
1878 assert(brw
->gen
< 6 || inst
->mlen
== 0);
1879 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1880 if (brw
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) {
1881 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1882 } else if (brw
->gen
>= 6) {
1883 generate_math_gen6(inst
, dst
, src
[0], src
[1]);
1885 generate_math_gen4(inst
, dst
, src
[0]);
1888 case FS_OPCODE_PIXEL_X
:
1889 generate_pixel_xy(dst
, true);
1891 case FS_OPCODE_PIXEL_Y
:
1892 generate_pixel_xy(dst
, false);
1894 case FS_OPCODE_CINTERP
:
1895 brw_MOV(p
, dst
, src
[0]);
1897 case FS_OPCODE_LINTERP
:
1898 generate_linterp(inst
, dst
, src
);
1900 case SHADER_OPCODE_TEX
:
1902 case SHADER_OPCODE_TXD
:
1903 case SHADER_OPCODE_TXF
:
1904 case SHADER_OPCODE_TXF_CMS
:
1905 case SHADER_OPCODE_TXF_UMS
:
1906 case SHADER_OPCODE_TXF_MCS
:
1907 case SHADER_OPCODE_TXL
:
1908 case SHADER_OPCODE_TXS
:
1909 case SHADER_OPCODE_LOD
:
1910 case SHADER_OPCODE_TG4
:
1911 case SHADER_OPCODE_TG4_OFFSET
:
1912 generate_tex(inst
, dst
, src
[0], src
[1]);
1914 case FS_OPCODE_DDX_COARSE
:
1915 case FS_OPCODE_DDX_FINE
:
1916 generate_ddx(inst
->opcode
, dst
, src
[0]);
1918 case FS_OPCODE_DDY_COARSE
:
1919 case FS_OPCODE_DDY_FINE
:
1920 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
1921 generate_ddy(inst
->opcode
, dst
, src
[0], src
[1].dw1
.ud
);
1924 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1925 generate_scratch_write(inst
, src
[0]);
1928 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1929 generate_scratch_read(inst
, dst
);
1932 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
1933 generate_scratch_read_gen7(inst
, dst
);
1936 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1937 generate_urb_write(inst
, src
[0]);
1940 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1941 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1944 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
1945 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1948 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
1949 generate_varying_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1952 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
1953 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1956 case FS_OPCODE_REP_FB_WRITE
:
1957 case FS_OPCODE_FB_WRITE
:
1958 generate_fb_write(inst
, src
[0]);
1961 case FS_OPCODE_BLORP_FB_WRITE
:
1962 generate_blorp_fb_write(inst
);
1965 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
1966 generate_mov_dispatch_to_flags(inst
);
1969 case FS_OPCODE_DISCARD_JUMP
:
1970 generate_discard_jump(inst
);
1973 case SHADER_OPCODE_SHADER_TIME_ADD
:
1974 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
1977 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1978 generate_untyped_atomic(inst
, dst
, src
[0], src
[1], src
[2]);
1981 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1982 generate_untyped_surface_read(inst
, dst
, src
[0], src
[1]);
1985 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
1986 generate_set_simd4x2_offset(inst
, dst
, src
[0]);
1989 case FS_OPCODE_SET_OMASK
:
1990 generate_set_omask(inst
, dst
, src
[0]);
1993 case FS_OPCODE_SET_SAMPLE_ID
:
1994 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
1997 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
1998 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2001 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
2002 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
2003 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
2006 case FS_OPCODE_PLACEHOLDER_HALT
:
2007 /* This is the place where the final HALT needs to be inserted if
2008 * we've emitted any discards. If not, this will emit no code.
2010 if (!patch_discard_jumps_to_fb_writes()) {
2011 if (unlikely(debug_flag
)) {
2012 annotation
.ann_count
--;
2017 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
2018 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2019 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID
);
2022 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2023 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2024 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2027 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2028 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2029 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2032 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2033 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2034 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2038 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
2039 _mesa_problem(ctx
, "Unsupported opcode `%s' in %s",
2040 opcode_descs
[inst
->opcode
].name
, stage_abbrev
);
2042 _mesa_problem(ctx
, "Unsupported opcode %d in %s", inst
->opcode
,
2047 case SHADER_OPCODE_LOAD_PAYLOAD
:
2048 unreachable("Should be lowered by lower_load_payload()");
2051 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2052 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2053 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2054 "emitting more than 1 instruction");
2056 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2058 if (inst
->conditional_mod
)
2059 brw_inst_set_cond_modifier(brw
, last
, inst
->conditional_mod
);
2060 brw_inst_set_no_dd_clear(brw
, last
, inst
->no_dd_clear
);
2061 brw_inst_set_no_dd_check(brw
, last
, inst
->no_dd_check
);
2066 annotation_finalize(&annotation
, p
->next_insn_offset
);
2068 int before_size
= p
->next_insn_offset
- start_offset
;
2069 brw_compact_instructions(p
, start_offset
, annotation
.ann_count
,
2071 int after_size
= p
->next_insn_offset
- start_offset
;
2073 if (unlikely(debug_flag
)) {
2074 fprintf(stderr
, "Native code for %s\n"
2075 "SIMD%d shader: %d instructions. %d loops. Compacted %d to %d"
2076 " bytes (%.0f%%)\n",
2078 dispatch_width
, before_size
/ 16, loop_count
, before_size
, after_size
,
2079 100.0f
* (before_size
- after_size
) / before_size
);
2081 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
, brw
, prog
);
2082 ralloc_free(annotation
.ann
);
2085 static GLuint msg_id
= 0;
2086 _mesa_gl_debug(&brw
->ctx
, &msg_id
,
2087 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
2088 MESA_DEBUG_TYPE_OTHER
,
2089 MESA_DEBUG_SEVERITY_NOTIFICATION
,
2090 "%s SIMD%d shader: %d inst, %d loops, "
2091 "compacted %d to %d bytes.\n",
2092 stage_abbrev
, dispatch_width
, before_size
/ 16, loop_count
,
2093 before_size
, after_size
);
2095 return start_offset
;
2099 fs_generator::get_assembly(unsigned int *assembly_size
)
2101 return brw_get_program(p
, assembly_size
);