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i965/vec4: Don't lose the force_writemask_all flag during CSE.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "main/macros.h"
31 #include "brw_context.h"
32 #include "brw_eu.h"
33 #include "brw_fs.h"
34 #include "brw_cfg.h"
35
36 static uint32_t brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case GRF:
40 return BRW_GENERAL_REGISTER_FILE;
41 case MRF:
42 return BRW_MESSAGE_REGISTER_FILE;
43 case IMM:
44 return BRW_IMMEDIATE_VALUE;
45 default:
46 unreachable("not reached");
47 }
48 }
49
50 static struct brw_reg
51 brw_reg_from_fs_reg(fs_reg *reg)
52 {
53 struct brw_reg brw_reg;
54
55 switch (reg->file) {
56 case GRF:
57 case MRF:
58 if (reg->stride == 0) {
59 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
60 } else if (reg->width < 8) {
61 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
62 brw_reg = stride(brw_reg, reg->width * reg->stride,
63 reg->width, reg->stride);
64 } else {
65 /* From the Haswell PRM:
66 *
67 * VertStride must be used to cross GRF register boundaries. This
68 * rule implies that elements within a 'Width' cannot cross GRF
69 * boundaries.
70 *
71 * So, for registers with width > 8, we have to use a width of 8
72 * and trust the compression state to sort out the exec size.
73 */
74 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
75 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
76 }
77
78 brw_reg = retype(brw_reg, reg->type);
79 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
80 break;
81 case IMM:
82 switch (reg->type) {
83 case BRW_REGISTER_TYPE_F:
84 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
85 break;
86 case BRW_REGISTER_TYPE_D:
87 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
88 break;
89 case BRW_REGISTER_TYPE_UD:
90 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
91 break;
92 case BRW_REGISTER_TYPE_W:
93 brw_reg = brw_imm_w(reg->fixed_hw_reg.dw1.d);
94 break;
95 case BRW_REGISTER_TYPE_UW:
96 brw_reg = brw_imm_uw(reg->fixed_hw_reg.dw1.ud);
97 break;
98 case BRW_REGISTER_TYPE_VF:
99 brw_reg = brw_imm_vf(reg->fixed_hw_reg.dw1.ud);
100 break;
101 default:
102 unreachable("not reached");
103 }
104 break;
105 case HW_REG:
106 assert(reg->type == reg->fixed_hw_reg.type);
107 brw_reg = reg->fixed_hw_reg;
108 break;
109 case BAD_FILE:
110 /* Probably unused. */
111 brw_reg = brw_null_reg();
112 break;
113 default:
114 unreachable("not reached");
115 }
116 if (reg->abs)
117 brw_reg = brw_abs(brw_reg);
118 if (reg->negate)
119 brw_reg = negate(brw_reg);
120
121 return brw_reg;
122 }
123
124 fs_generator::fs_generator(struct brw_context *brw,
125 void *mem_ctx,
126 const void *key,
127 struct brw_stage_prog_data *prog_data,
128 struct gl_program *prog,
129 unsigned promoted_constants,
130 bool runtime_check_aads_emit,
131 const char *stage_abbrev)
132
133 : brw(brw), key(key),
134 prog_data(prog_data),
135 prog(prog), promoted_constants(promoted_constants),
136 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
137 stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
138 {
139 ctx = &brw->ctx;
140
141 p = rzalloc(mem_ctx, struct brw_compile);
142 brw_init_compile(brw, p, mem_ctx);
143 }
144
145 fs_generator::~fs_generator()
146 {
147 }
148
149 class ip_record : public exec_node {
150 public:
151 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
152
153 ip_record(int ip)
154 {
155 this->ip = ip;
156 }
157
158 int ip;
159 };
160
161 bool
162 fs_generator::patch_discard_jumps_to_fb_writes()
163 {
164 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
165 return false;
166
167 int scale = brw_jump_scale(brw);
168
169 /* There is a somewhat strange undocumented requirement of using
170 * HALT, according to the simulator. If some channel has HALTed to
171 * a particular UIP, then by the end of the program, every channel
172 * must have HALTed to that UIP. Furthermore, the tracking is a
173 * stack, so you can't do the final halt of a UIP after starting
174 * halting to a new UIP.
175 *
176 * Symptoms of not emitting this instruction on actual hardware
177 * included GPU hangs and sparkly rendering on the piglit discard
178 * tests.
179 */
180 brw_inst *last_halt = gen6_HALT(p);
181 brw_inst_set_uip(brw, last_halt, 1 * scale);
182 brw_inst_set_jip(brw, last_halt, 1 * scale);
183
184 int ip = p->nr_insn;
185
186 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
187 brw_inst *patch = &p->store[patch_ip->ip];
188
189 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
190 /* HALT takes a half-instruction distance from the pre-incremented IP. */
191 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
192 }
193
194 this->discard_halt_patches.make_empty();
195 return true;
196 }
197
198 void
199 fs_generator::fire_fb_write(fs_inst *inst,
200 struct brw_reg payload,
201 struct brw_reg implied_header,
202 GLuint nr)
203 {
204 uint32_t msg_control;
205
206 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
207
208 if (brw->gen < 6) {
209 brw_push_insn_state(p);
210 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
211 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
212 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
213 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
214 brw_pop_insn_state(p);
215 }
216
217 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
218 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
219 else if (prog_data->dual_src_blend) {
220 if (dispatch_width == 8 || !inst->eot)
221 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
222 else
223 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
224 } else if (dispatch_width == 16)
225 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
226 else
227 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
228
229 uint32_t surf_index =
230 prog_data->binding_table.render_target_start + inst->target;
231
232 bool last_render_target = inst->eot ||
233 (prog_data->dual_src_blend && dispatch_width == 16);
234
235
236 brw_fb_WRITE(p,
237 dispatch_width,
238 payload,
239 implied_header,
240 msg_control,
241 surf_index,
242 nr,
243 0,
244 inst->eot,
245 last_render_target,
246 inst->header_present);
247
248 brw_mark_surface_used(&prog_data->base, surf_index);
249 }
250
251 void
252 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
253 {
254 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
255 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
256 struct brw_reg implied_header;
257
258 if (brw->gen < 8 && !brw->is_haswell) {
259 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
260 }
261
262 if (inst->base_mrf >= 0)
263 payload = brw_message_reg(inst->base_mrf);
264
265 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
266 * move, here's g1.
267 */
268 if (inst->header_present) {
269 brw_push_insn_state(p);
270 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
271 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
272 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
273 brw_set_default_flag_reg(p, 0, 0);
274
275 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
276 * present.
277 */
278 if (prog_data->uses_kill) {
279 struct brw_reg pixel_mask;
280
281 if (brw->gen >= 6)
282 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
283 else
284 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
285
286 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
287 }
288
289 if (brw->gen >= 6) {
290 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
291 brw_MOV(p,
292 retype(payload, BRW_REGISTER_TYPE_UD),
293 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
294 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
295
296 if (inst->target > 0 && key->replicate_alpha) {
297 /* Set "Source0 Alpha Present to RenderTarget" bit in message
298 * header.
299 */
300 brw_OR(p,
301 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
302 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
303 brw_imm_ud(0x1 << 11));
304 }
305
306 if (inst->target > 0) {
307 /* Set the render target index for choosing BLEND_STATE. */
308 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
309 BRW_REGISTER_TYPE_UD),
310 brw_imm_ud(inst->target));
311 }
312
313 implied_header = brw_null_reg();
314 } else {
315 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
316 }
317
318 brw_pop_insn_state(p);
319 } else {
320 implied_header = brw_null_reg();
321 }
322
323 if (!runtime_check_aads_emit) {
324 fire_fb_write(inst, payload, implied_header, inst->mlen);
325 } else {
326 /* This can only happen in gen < 6 */
327 assert(brw->gen < 6);
328
329 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
330
331 /* Check runtime bit to detect if we have to send AA data or not */
332 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
333 brw_AND(p,
334 v1_null_ud,
335 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
336 brw_imm_ud(1<<26));
337 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
338
339 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
340 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
341 {
342 /* Don't send AA data */
343 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
344 }
345 brw_land_fwd_jump(p, jmp);
346 fire_fb_write(inst, payload, implied_header, inst->mlen);
347 }
348 }
349
350 void
351 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
352 {
353 brw_inst *insn;
354
355 insn = brw_next_insn(p, BRW_OPCODE_SEND);
356
357 brw_set_dest(p, insn, brw_null_reg());
358 brw_set_src0(p, insn, payload);
359 brw_set_src1(p, insn, brw_imm_d(0));
360
361 brw_inst_set_sfid(brw, insn, BRW_SFID_URB);
362 brw_inst_set_urb_opcode(brw, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
363
364 brw_inst_set_mlen(brw, insn, inst->mlen);
365 brw_inst_set_rlen(brw, insn, 0);
366 brw_inst_set_eot(brw, insn, inst->eot);
367 brw_inst_set_header_present(brw, insn, true);
368 brw_inst_set_urb_global_offset(brw, insn, inst->offset);
369 }
370
371 void
372 fs_generator::generate_blorp_fb_write(fs_inst *inst)
373 {
374 brw_fb_WRITE(p,
375 16 /* dispatch_width */,
376 brw_message_reg(inst->base_mrf),
377 brw_reg_from_fs_reg(&inst->src[0]),
378 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
379 inst->target,
380 inst->mlen,
381 0,
382 true,
383 true,
384 inst->header_present);
385 }
386
387 /* Computes the integer pixel x,y values from the origin.
388 *
389 * This is the basis of gl_FragCoord computation, but is also used
390 * pre-gen6 for computing the deltas from v0 for computing
391 * interpolation.
392 */
393 void
394 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
395 {
396 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
397 struct brw_reg src;
398 struct brw_reg deltas;
399
400 if (is_x) {
401 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
402 deltas = brw_imm_v(0x10101010);
403 } else {
404 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
405 deltas = brw_imm_v(0x11001100);
406 }
407
408 if (dispatch_width == 16) {
409 dst = vec16(dst);
410 }
411
412 /* We do this SIMD8 or SIMD16, but since the destination is UW we
413 * don't do compression in the SIMD16 case.
414 */
415 brw_push_insn_state(p);
416 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
417 brw_ADD(p, dst, src, deltas);
418 brw_pop_insn_state(p);
419 }
420
421 void
422 fs_generator::generate_linterp(fs_inst *inst,
423 struct brw_reg dst, struct brw_reg *src)
424 {
425 struct brw_reg delta_x = src[0];
426 struct brw_reg delta_y = src[1];
427 struct brw_reg interp = src[2];
428
429 if (brw->has_pln &&
430 delta_y.nr == delta_x.nr + 1 &&
431 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
432 brw_PLN(p, dst, interp, delta_x);
433 } else {
434 brw_LINE(p, brw_null_reg(), interp, delta_x);
435 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
436 }
437 }
438
439 void
440 fs_generator::generate_math_gen6(fs_inst *inst,
441 struct brw_reg dst,
442 struct brw_reg src0,
443 struct brw_reg src1)
444 {
445 int op = brw_math_function(inst->opcode);
446 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
447
448 if (dispatch_width == 8) {
449 gen6_math(p, dst, op, src0, src1);
450 } else if (dispatch_width == 16) {
451 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
452 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
453 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
454 gen6_math(p, sechalf(dst), op, sechalf(src0),
455 binop ? sechalf(src1) : brw_null_reg());
456 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
457 }
458 }
459
460 void
461 fs_generator::generate_math_gen4(fs_inst *inst,
462 struct brw_reg dst,
463 struct brw_reg src)
464 {
465 int op = brw_math_function(inst->opcode);
466
467 assert(inst->mlen >= 1);
468
469 if (dispatch_width == 8) {
470 gen4_math(p, dst,
471 op,
472 inst->base_mrf, src,
473 BRW_MATH_PRECISION_FULL);
474 } else if (dispatch_width == 16) {
475 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
476 gen4_math(p, firsthalf(dst),
477 op,
478 inst->base_mrf, firsthalf(src),
479 BRW_MATH_PRECISION_FULL);
480 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
481 gen4_math(p, sechalf(dst),
482 op,
483 inst->base_mrf + 1, sechalf(src),
484 BRW_MATH_PRECISION_FULL);
485
486 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
487 }
488 }
489
490 void
491 fs_generator::generate_math_g45(fs_inst *inst,
492 struct brw_reg dst,
493 struct brw_reg src)
494 {
495 if (inst->opcode == SHADER_OPCODE_POW ||
496 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
497 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
498 generate_math_gen4(inst, dst, src);
499 return;
500 }
501
502 int op = brw_math_function(inst->opcode);
503
504 assert(inst->mlen >= 1);
505
506 gen4_math(p, dst,
507 op,
508 inst->base_mrf, src,
509 BRW_MATH_PRECISION_FULL);
510 }
511
512 void
513 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
514 struct brw_reg sampler_index)
515 {
516 int msg_type = -1;
517 int rlen = 4;
518 uint32_t simd_mode;
519 uint32_t return_format;
520
521 switch (dst.type) {
522 case BRW_REGISTER_TYPE_D:
523 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
524 break;
525 case BRW_REGISTER_TYPE_UD:
526 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
527 break;
528 default:
529 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
530 break;
531 }
532
533 switch (inst->exec_size) {
534 case 8:
535 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
536 break;
537 case 16:
538 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
539 break;
540 default:
541 unreachable("Invalid width for texture instruction");
542 }
543
544 if (brw->gen >= 5) {
545 switch (inst->opcode) {
546 case SHADER_OPCODE_TEX:
547 if (inst->shadow_compare) {
548 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
549 } else {
550 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
551 }
552 break;
553 case FS_OPCODE_TXB:
554 if (inst->shadow_compare) {
555 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
556 } else {
557 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
558 }
559 break;
560 case SHADER_OPCODE_TXL:
561 if (inst->shadow_compare) {
562 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
563 } else {
564 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
565 }
566 break;
567 case SHADER_OPCODE_TXS:
568 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
569 break;
570 case SHADER_OPCODE_TXD:
571 if (inst->shadow_compare) {
572 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
573 assert(brw->gen >= 8 || brw->is_haswell);
574 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
575 } else {
576 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
577 }
578 break;
579 case SHADER_OPCODE_TXF:
580 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
581 break;
582 case SHADER_OPCODE_TXF_CMS:
583 if (brw->gen >= 7)
584 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
585 else
586 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
587 break;
588 case SHADER_OPCODE_TXF_UMS:
589 assert(brw->gen >= 7);
590 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
591 break;
592 case SHADER_OPCODE_TXF_MCS:
593 assert(brw->gen >= 7);
594 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
595 break;
596 case SHADER_OPCODE_LOD:
597 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
598 break;
599 case SHADER_OPCODE_TG4:
600 if (inst->shadow_compare) {
601 assert(brw->gen >= 7);
602 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
603 } else {
604 assert(brw->gen >= 6);
605 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
606 }
607 break;
608 case SHADER_OPCODE_TG4_OFFSET:
609 assert(brw->gen >= 7);
610 if (inst->shadow_compare) {
611 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
612 } else {
613 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
614 }
615 break;
616 default:
617 unreachable("not reached");
618 }
619 } else {
620 switch (inst->opcode) {
621 case SHADER_OPCODE_TEX:
622 /* Note that G45 and older determines shadow compare and dispatch width
623 * from message length for most messages.
624 */
625 assert(dispatch_width == 8);
626 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
627 if (inst->shadow_compare) {
628 assert(inst->mlen == 6);
629 } else {
630 assert(inst->mlen <= 4);
631 }
632 break;
633 case FS_OPCODE_TXB:
634 if (inst->shadow_compare) {
635 assert(inst->mlen == 6);
636 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
637 } else {
638 assert(inst->mlen == 9);
639 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
640 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
641 }
642 break;
643 case SHADER_OPCODE_TXL:
644 if (inst->shadow_compare) {
645 assert(inst->mlen == 6);
646 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
647 } else {
648 assert(inst->mlen == 9);
649 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
650 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
651 }
652 break;
653 case SHADER_OPCODE_TXD:
654 /* There is no sample_d_c message; comparisons are done manually */
655 assert(inst->mlen == 7 || inst->mlen == 10);
656 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
657 break;
658 case SHADER_OPCODE_TXF:
659 assert(inst->mlen == 9);
660 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
661 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
662 break;
663 case SHADER_OPCODE_TXS:
664 assert(inst->mlen == 3);
665 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
666 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
667 break;
668 default:
669 unreachable("not reached");
670 }
671 }
672 assert(msg_type != -1);
673
674 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
675 rlen = 8;
676 dst = vec16(dst);
677 }
678
679 assert(brw->gen < 7 || !inst->header_present ||
680 src.file == BRW_GENERAL_REGISTER_FILE);
681
682 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
683
684 /* Load the message header if present. If there's a texture offset,
685 * we need to set it up explicitly and load the offset bitfield.
686 * Otherwise, we can use an implied move from g0 to the first message reg.
687 */
688 if (inst->header_present) {
689 if (brw->gen < 6 && !inst->offset) {
690 /* Set up an implied move from g0 to the MRF. */
691 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
692 } else {
693 struct brw_reg header_reg;
694
695 if (brw->gen >= 7) {
696 header_reg = src;
697 } else {
698 assert(inst->base_mrf != -1);
699 header_reg = brw_message_reg(inst->base_mrf);
700 }
701
702 brw_push_insn_state(p);
703 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
704 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
705 /* Explicitly set up the message header by copying g0 to the MRF. */
706 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
707
708 if (inst->offset) {
709 /* Set the offset bits in DWord 2. */
710 brw_MOV(p, get_element_ud(header_reg, 2),
711 brw_imm_ud(inst->offset));
712 }
713
714 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
715 brw_pop_insn_state(p);
716 }
717 }
718
719 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
720 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
721 ? prog_data->binding_table.gather_texture_start
722 : prog_data->binding_table.texture_start;
723
724 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
725 uint32_t sampler = sampler_index.dw1.ud;
726
727 brw_SAMPLE(p,
728 retype(dst, BRW_REGISTER_TYPE_UW),
729 inst->base_mrf,
730 src,
731 sampler + base_binding_table_index,
732 sampler % 16,
733 msg_type,
734 rlen,
735 inst->mlen,
736 inst->header_present,
737 simd_mode,
738 return_format);
739
740 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
741 } else {
742 /* Non-const sampler index */
743 /* Note: this clobbers `dst` as a temporary before emitting the send */
744
745 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
746 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
747
748 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
749
750 brw_push_insn_state(p);
751 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
752 brw_set_default_access_mode(p, BRW_ALIGN_1);
753
754 /* Some care required: `sampler` and `temp` may alias:
755 * addr = sampler & 0xff
756 * temp = (sampler << 8) & 0xf00
757 * addr = addr | temp
758 */
759 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
760 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
761 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
762 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
763 brw_OR(p, addr, addr, temp);
764
765 brw_pop_insn_state(p);
766
767 /* dst = send(offset, a0.0 | <descriptor>) */
768 brw_inst *insn = brw_send_indirect_message(
769 p, BRW_SFID_SAMPLER, dst, src, addr);
770 brw_set_sampler_message(p, insn,
771 0 /* surface */,
772 0 /* sampler */,
773 msg_type,
774 rlen,
775 inst->mlen /* mlen */,
776 inst->header_present /* header */,
777 simd_mode,
778 return_format);
779
780 /* visitor knows more than we do about the surface limit required,
781 * so has already done marking.
782 */
783 }
784 }
785
786
787 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
788 * looking like:
789 *
790 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
791 *
792 * Ideally, we want to produce:
793 *
794 * DDX DDY
795 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
796 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
797 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
798 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
799 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
800 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
801 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
802 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
803 *
804 * and add another set of two more subspans if in 16-pixel dispatch mode.
805 *
806 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
807 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
808 * pair. But the ideal approximation may impose a huge performance cost on
809 * sample_d. On at least Haswell, sample_d instruction does some
810 * optimizations if the same LOD is used for all pixels in the subspan.
811 *
812 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
813 * appropriate swizzling.
814 */
815 void
816 fs_generator::generate_ddx(enum opcode opcode,
817 struct brw_reg dst, struct brw_reg src)
818 {
819 unsigned vstride, width;
820
821 if (opcode == FS_OPCODE_DDX_FINE) {
822 /* produce accurate derivatives */
823 vstride = BRW_VERTICAL_STRIDE_2;
824 width = BRW_WIDTH_2;
825 } else {
826 /* replicate the derivative at the top-left pixel to other pixels */
827 vstride = BRW_VERTICAL_STRIDE_4;
828 width = BRW_WIDTH_4;
829 }
830
831 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
832 src.negate, src.abs,
833 BRW_REGISTER_TYPE_F,
834 vstride,
835 width,
836 BRW_HORIZONTAL_STRIDE_0,
837 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
838 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
839 src.negate, src.abs,
840 BRW_REGISTER_TYPE_F,
841 vstride,
842 width,
843 BRW_HORIZONTAL_STRIDE_0,
844 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
845 brw_ADD(p, dst, src0, negate(src1));
846 }
847
848 /* The negate_value boolean is used to negate the derivative computation for
849 * FBOs, since they place the origin at the upper left instead of the lower
850 * left.
851 */
852 void
853 fs_generator::generate_ddy(enum opcode opcode,
854 struct brw_reg dst, struct brw_reg src,
855 bool negate_value)
856 {
857 if (opcode == FS_OPCODE_DDY_FINE) {
858 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
859 * Region Restrictions):
860 *
861 * In Align16 access mode, SIMD16 is not allowed for DW operations
862 * and SIMD8 is not allowed for DF operations.
863 *
864 * In this context, "DW operations" means "operations acting on 32-bit
865 * values", so it includes operations on floats.
866 *
867 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
868 * (Instruction Compression -> Rules and Restrictions):
869 *
870 * A compressed instruction must be in Align1 access mode. Align16
871 * mode instructions cannot be compressed.
872 *
873 * Similar text exists in the g45 PRM.
874 *
875 * On these platforms, if we're building a SIMD16 shader, we need to
876 * manually unroll to a pair of SIMD8 instructions.
877 */
878 bool unroll_to_simd8 =
879 (dispatch_width == 16 &&
880 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
881
882 /* produce accurate derivatives */
883 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
884 src.negate, src.abs,
885 BRW_REGISTER_TYPE_F,
886 BRW_VERTICAL_STRIDE_4,
887 BRW_WIDTH_4,
888 BRW_HORIZONTAL_STRIDE_1,
889 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
890 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
891 src.negate, src.abs,
892 BRW_REGISTER_TYPE_F,
893 BRW_VERTICAL_STRIDE_4,
894 BRW_WIDTH_4,
895 BRW_HORIZONTAL_STRIDE_1,
896 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
897 brw_push_insn_state(p);
898 brw_set_default_access_mode(p, BRW_ALIGN_16);
899 if (unroll_to_simd8) {
900 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
901 if (negate_value) {
902 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
903 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
904 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
905 } else {
906 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
907 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
908 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
909 }
910 } else {
911 if (negate_value)
912 brw_ADD(p, dst, src1, negate(src0));
913 else
914 brw_ADD(p, dst, src0, negate(src1));
915 }
916 brw_pop_insn_state(p);
917 } else {
918 /* replicate the derivative at the top-left pixel to other pixels */
919 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
920 src.negate, src.abs,
921 BRW_REGISTER_TYPE_F,
922 BRW_VERTICAL_STRIDE_4,
923 BRW_WIDTH_4,
924 BRW_HORIZONTAL_STRIDE_0,
925 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
926 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
927 src.negate, src.abs,
928 BRW_REGISTER_TYPE_F,
929 BRW_VERTICAL_STRIDE_4,
930 BRW_WIDTH_4,
931 BRW_HORIZONTAL_STRIDE_0,
932 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
933 if (negate_value)
934 brw_ADD(p, dst, src1, negate(src0));
935 else
936 brw_ADD(p, dst, src0, negate(src1));
937 }
938 }
939
940 void
941 fs_generator::generate_discard_jump(fs_inst *inst)
942 {
943 assert(brw->gen >= 6);
944
945 /* This HALT will be patched up at FB write time to point UIP at the end of
946 * the program, and at brw_uip_jip() JIP will be set to the end of the
947 * current block (or the program).
948 */
949 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
950
951 brw_push_insn_state(p);
952 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
953 gen6_HALT(p);
954 brw_pop_insn_state(p);
955 }
956
957 void
958 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
959 {
960 assert(inst->mlen != 0);
961
962 brw_MOV(p,
963 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
964 retype(src, BRW_REGISTER_TYPE_UD));
965 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
966 inst->exec_size / 8, inst->offset);
967 }
968
969 void
970 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
971 {
972 assert(inst->mlen != 0);
973
974 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
975 inst->exec_size / 8, inst->offset);
976 }
977
978 void
979 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
980 {
981 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
982 }
983
984 void
985 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
986 struct brw_reg dst,
987 struct brw_reg index,
988 struct brw_reg offset)
989 {
990 assert(inst->mlen != 0);
991
992 assert(index.file == BRW_IMMEDIATE_VALUE &&
993 index.type == BRW_REGISTER_TYPE_UD);
994 uint32_t surf_index = index.dw1.ud;
995
996 assert(offset.file == BRW_IMMEDIATE_VALUE &&
997 offset.type == BRW_REGISTER_TYPE_UD);
998 uint32_t read_offset = offset.dw1.ud;
999
1000 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1001 read_offset, surf_index);
1002
1003 brw_mark_surface_used(prog_data, surf_index);
1004 }
1005
1006 void
1007 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1008 struct brw_reg dst,
1009 struct brw_reg index,
1010 struct brw_reg offset)
1011 {
1012 assert(inst->mlen == 0);
1013 assert(index.type == BRW_REGISTER_TYPE_UD);
1014
1015 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1016 /* Reference just the dword we need, to avoid angering validate_reg(). */
1017 offset = brw_vec1_grf(offset.nr, 0);
1018
1019 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1020 * the destination loaded consecutively from the same offset (which appears
1021 * in the first component, and the rest are ignored).
1022 */
1023 dst.width = BRW_WIDTH_4;
1024
1025 struct brw_reg src = offset;
1026 bool header_present = false;
1027 int mlen = 1;
1028
1029 if (brw->gen >= 9) {
1030 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1031 src = retype(brw_vec4_grf(offset.nr - 1, 0), BRW_REGISTER_TYPE_UD);
1032 mlen = 2;
1033 header_present = true;
1034
1035 brw_push_insn_state(p);
1036 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1037 brw_MOV(p, src, retype(brw_vec4_grf(0, 0), BRW_REGISTER_TYPE_UD));
1038 brw_set_default_access_mode(p, BRW_ALIGN_1);
1039
1040 brw_MOV(p, get_element_ud(src, 2),
1041 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1042 brw_pop_insn_state(p);
1043 }
1044
1045 if (index.file == BRW_IMMEDIATE_VALUE) {
1046
1047 uint32_t surf_index = index.dw1.ud;
1048
1049 brw_push_insn_state(p);
1050 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1051 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1052 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1053 brw_pop_insn_state(p);
1054
1055 brw_set_dest(p, send, dst);
1056 brw_set_src0(p, send, src);
1057 brw_set_sampler_message(p, send,
1058 surf_index,
1059 0, /* LD message ignores sampler unit */
1060 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1061 1, /* rlen */
1062 mlen,
1063 header_present,
1064 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1065 0);
1066
1067 brw_mark_surface_used(prog_data, surf_index);
1068
1069 } else {
1070
1071 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1072
1073 brw_push_insn_state(p);
1074 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1075 brw_set_default_access_mode(p, BRW_ALIGN_1);
1076
1077 /* a0.0 = surf_index & 0xff */
1078 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1079 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1080 brw_set_dest(p, insn_and, addr);
1081 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1082 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1083
1084 /* dst = send(payload, a0.0 | <descriptor>) */
1085 brw_inst *insn = brw_send_indirect_message(
1086 p, BRW_SFID_SAMPLER, dst, src, addr);
1087 brw_set_sampler_message(p, insn,
1088 0,
1089 0, /* LD message ignores sampler unit */
1090 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1091 1, /* rlen */
1092 mlen,
1093 header_present,
1094 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1095 0);
1096
1097 brw_pop_insn_state(p);
1098
1099 /* visitor knows more than we do about the surface limit required,
1100 * so has already done marking.
1101 */
1102
1103 }
1104 }
1105
1106 void
1107 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1108 struct brw_reg dst,
1109 struct brw_reg index,
1110 struct brw_reg offset)
1111 {
1112 assert(brw->gen < 7); /* Should use the gen7 variant. */
1113 assert(inst->header_present);
1114 assert(inst->mlen);
1115
1116 assert(index.file == BRW_IMMEDIATE_VALUE &&
1117 index.type == BRW_REGISTER_TYPE_UD);
1118 uint32_t surf_index = index.dw1.ud;
1119
1120 uint32_t simd_mode, rlen, msg_type;
1121 if (dispatch_width == 16) {
1122 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1123 rlen = 8;
1124 } else {
1125 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1126 rlen = 4;
1127 }
1128
1129 if (brw->gen >= 5)
1130 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1131 else {
1132 /* We always use the SIMD16 message so that we only have to load U, and
1133 * not V or R.
1134 */
1135 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1136 assert(inst->mlen == 3);
1137 assert(inst->regs_written == 8);
1138 rlen = 8;
1139 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1140 }
1141
1142 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1143 BRW_REGISTER_TYPE_D);
1144 brw_MOV(p, offset_mrf, offset);
1145
1146 struct brw_reg header = brw_vec8_grf(0, 0);
1147 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1148
1149 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1150 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
1151 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1152 brw_set_src0(p, send, header);
1153 if (brw->gen < 6)
1154 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
1155
1156 /* Our surface is set up as floats, regardless of what actual data is
1157 * stored in it.
1158 */
1159 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1160 brw_set_sampler_message(p, send,
1161 surf_index,
1162 0, /* sampler (unused) */
1163 msg_type,
1164 rlen,
1165 inst->mlen,
1166 inst->header_present,
1167 simd_mode,
1168 return_format);
1169
1170 brw_mark_surface_used(prog_data, surf_index);
1171 }
1172
1173 void
1174 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1175 struct brw_reg dst,
1176 struct brw_reg index,
1177 struct brw_reg offset)
1178 {
1179 assert(brw->gen >= 7);
1180 /* Varying-offset pull constant loads are treated as a normal expression on
1181 * gen7, so the fact that it's a send message is hidden at the IR level.
1182 */
1183 assert(!inst->header_present);
1184 assert(!inst->mlen);
1185 assert(index.type == BRW_REGISTER_TYPE_UD);
1186
1187 uint32_t simd_mode, rlen, mlen;
1188 if (dispatch_width == 16) {
1189 mlen = 2;
1190 rlen = 8;
1191 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1192 } else {
1193 mlen = 1;
1194 rlen = 4;
1195 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1196 }
1197
1198 if (index.file == BRW_IMMEDIATE_VALUE) {
1199
1200 uint32_t surf_index = index.dw1.ud;
1201
1202 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1203 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1204 brw_set_src0(p, send, offset);
1205 brw_set_sampler_message(p, send,
1206 surf_index,
1207 0, /* LD message ignores sampler unit */
1208 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1209 rlen,
1210 mlen,
1211 false, /* no header */
1212 simd_mode,
1213 0);
1214
1215 brw_mark_surface_used(prog_data, surf_index);
1216
1217 } else {
1218
1219 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1220
1221 brw_push_insn_state(p);
1222 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1223 brw_set_default_access_mode(p, BRW_ALIGN_1);
1224
1225 /* a0.0 = surf_index & 0xff */
1226 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1227 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1228 brw_set_dest(p, insn_and, addr);
1229 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1230 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1231
1232 brw_pop_insn_state(p);
1233
1234 /* dst = send(offset, a0.0 | <descriptor>) */
1235 brw_inst *insn = brw_send_indirect_message(
1236 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1237 offset, addr);
1238 brw_set_sampler_message(p, insn,
1239 0 /* surface */,
1240 0 /* sampler */,
1241 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1242 rlen /* rlen */,
1243 mlen /* mlen */,
1244 false /* header */,
1245 simd_mode,
1246 0);
1247
1248 /* visitor knows more than we do about the surface limit required,
1249 * so has already done marking.
1250 */
1251 }
1252 }
1253
1254 /**
1255 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1256 * into the flags register (f0.0).
1257 *
1258 * Used only on Gen6 and above.
1259 */
1260 void
1261 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1262 {
1263 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1264 struct brw_reg dispatch_mask;
1265
1266 if (brw->gen >= 6)
1267 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1268 else
1269 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1270
1271 brw_push_insn_state(p);
1272 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1273 brw_MOV(p, flags, dispatch_mask);
1274 brw_pop_insn_state(p);
1275 }
1276
1277 void
1278 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1279 struct brw_reg dst,
1280 struct brw_reg src,
1281 struct brw_reg msg_data,
1282 unsigned msg_type)
1283 {
1284 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1285 msg_data.type == BRW_REGISTER_TYPE_UD);
1286
1287 brw_pixel_interpolator_query(p,
1288 retype(dst, BRW_REGISTER_TYPE_UW),
1289 src,
1290 inst->pi_noperspective,
1291 msg_type,
1292 msg_data.dw1.ud,
1293 inst->mlen,
1294 inst->regs_written);
1295 }
1296
1297
1298 /**
1299 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1300 * sampler LD messages.
1301 *
1302 * We don't want to bake it into the send message's code generation because
1303 * that means we don't get a chance to schedule the instructions.
1304 */
1305 void
1306 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1307 struct brw_reg dst,
1308 struct brw_reg value)
1309 {
1310 assert(value.file == BRW_IMMEDIATE_VALUE);
1311
1312 brw_push_insn_state(p);
1313 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1314 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1315 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1316 brw_pop_insn_state(p);
1317 }
1318
1319 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1320 * (when mask is passed as a uniform) of register mask before moving it
1321 * to register dst.
1322 */
1323 void
1324 fs_generator::generate_set_omask(fs_inst *inst,
1325 struct brw_reg dst,
1326 struct brw_reg mask)
1327 {
1328 bool stride_8_8_1 =
1329 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1330 mask.width == BRW_WIDTH_8 &&
1331 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1332
1333 bool stride_0_1_0 = has_scalar_region(mask);
1334
1335 assert(stride_8_8_1 || stride_0_1_0);
1336 assert(dst.type == BRW_REGISTER_TYPE_UW);
1337
1338 if (dispatch_width == 16)
1339 dst = vec16(dst);
1340 brw_push_insn_state(p);
1341 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1342 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1343
1344 if (stride_8_8_1) {
1345 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1346 } else if (stride_0_1_0) {
1347 brw_MOV(p, dst, retype(mask, dst.type));
1348 }
1349 brw_pop_insn_state(p);
1350 }
1351
1352 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1353 * the ADD instruction.
1354 */
1355 void
1356 fs_generator::generate_set_sample_id(fs_inst *inst,
1357 struct brw_reg dst,
1358 struct brw_reg src0,
1359 struct brw_reg src1)
1360 {
1361 assert(dst.type == BRW_REGISTER_TYPE_D ||
1362 dst.type == BRW_REGISTER_TYPE_UD);
1363 assert(src0.type == BRW_REGISTER_TYPE_D ||
1364 src0.type == BRW_REGISTER_TYPE_UD);
1365
1366 brw_push_insn_state(p);
1367 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1368 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1369 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1370 if (dispatch_width == 8) {
1371 brw_ADD(p, dst, src0, reg);
1372 } else if (dispatch_width == 16) {
1373 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1374 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1375 }
1376 brw_pop_insn_state(p);
1377 }
1378
1379 void
1380 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1381 struct brw_reg dst,
1382 struct brw_reg x,
1383 struct brw_reg y)
1384 {
1385 assert(brw->gen >= 7);
1386 assert(dst.type == BRW_REGISTER_TYPE_UD);
1387 assert(x.type == BRW_REGISTER_TYPE_F);
1388 assert(y.type == BRW_REGISTER_TYPE_F);
1389
1390 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1391 *
1392 * Because this instruction does not have a 16-bit floating-point type,
1393 * the destination data type must be Word (W).
1394 *
1395 * The destination must be DWord-aligned and specify a horizontal stride
1396 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1397 * each destination channel and the upper word is not modified.
1398 */
1399 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1400
1401 /* Give each 32-bit channel of dst the form below, where "." means
1402 * unchanged.
1403 * 0x....hhhh
1404 */
1405 brw_F32TO16(p, dst_w, y);
1406
1407 /* Now the form:
1408 * 0xhhhh0000
1409 */
1410 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1411
1412 /* And, finally the form of packHalf2x16's output:
1413 * 0xhhhhllll
1414 */
1415 brw_F32TO16(p, dst_w, x);
1416 }
1417
1418 void
1419 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1420 struct brw_reg dst,
1421 struct brw_reg src)
1422 {
1423 assert(brw->gen >= 7);
1424 assert(dst.type == BRW_REGISTER_TYPE_F);
1425 assert(src.type == BRW_REGISTER_TYPE_UD);
1426
1427 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1428 *
1429 * Because this instruction does not have a 16-bit floating-point type,
1430 * the source data type must be Word (W). The destination type must be
1431 * F (Float).
1432 */
1433 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1434
1435 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1436 * For the Y case, we wish to access only the upper word; therefore
1437 * a 16-bit subregister offset is needed.
1438 */
1439 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1440 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1441 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1442 src_w.subnr += 2;
1443
1444 brw_F16TO32(p, dst, src_w);
1445 }
1446
1447 void
1448 fs_generator::generate_shader_time_add(fs_inst *inst,
1449 struct brw_reg payload,
1450 struct brw_reg offset,
1451 struct brw_reg value)
1452 {
1453 assert(brw->gen >= 7);
1454 brw_push_insn_state(p);
1455 brw_set_default_mask_control(p, true);
1456
1457 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1458 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1459 offset.type);
1460 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1461 value.type);
1462
1463 assert(offset.file == BRW_IMMEDIATE_VALUE);
1464 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1465 value.width = BRW_WIDTH_1;
1466 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1467 value.vstride = BRW_VERTICAL_STRIDE_0;
1468 } else {
1469 assert(value.file == BRW_IMMEDIATE_VALUE);
1470 }
1471
1472 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1473 * case, and we don't really care about squeezing every bit of performance
1474 * out of this path, so we just emit the MOVs from here.
1475 */
1476 brw_MOV(p, payload_offset, offset);
1477 brw_MOV(p, payload_value, value);
1478 brw_shader_time_add(p, payload,
1479 prog_data->binding_table.shader_time_start);
1480 brw_pop_insn_state(p);
1481
1482 brw_mark_surface_used(prog_data,
1483 prog_data->binding_table.shader_time_start);
1484 }
1485
1486 void
1487 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1488 struct brw_reg payload,
1489 struct brw_reg atomic_op,
1490 struct brw_reg surf_index)
1491 {
1492 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1493 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1494 surf_index.file == BRW_IMMEDIATE_VALUE &&
1495 surf_index.type == BRW_REGISTER_TYPE_UD);
1496
1497 brw_untyped_atomic(p, dst, payload,
1498 atomic_op.dw1.ud, surf_index.dw1.ud,
1499 inst->mlen, true);
1500
1501 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1502 }
1503
1504 void
1505 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1506 struct brw_reg payload,
1507 struct brw_reg surf_index)
1508 {
1509 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1510 surf_index.type == BRW_REGISTER_TYPE_UD);
1511
1512 brw_untyped_surface_read(p, dst, payload, surf_index.dw1.ud, inst->mlen, 1);
1513
1514 brw_mark_surface_used(prog_data, surf_index.dw1.ud);
1515 }
1516
1517 void
1518 fs_generator::enable_debug(const char *shader_name)
1519 {
1520 debug_flag = true;
1521 this->shader_name = shader_name;
1522 }
1523
1524 /**
1525 * Some hardware doesn't support SIMD16 instructions with 3 sources.
1526 */
1527 static bool
1528 brw_supports_simd16_3src(const struct brw_context *brw)
1529 {
1530 /* WaDisableSIMD16On3SrcInstr: 3-source instructions don't work in SIMD16
1531 * on a few steppings of Skylake.
1532 */
1533 if (brw->gen == 9)
1534 return brw->revision != 2 && brw->revision != 3 && brw->revision != -1;
1535
1536 return brw->is_haswell || brw->gen >= 8;
1537 }
1538
1539 int
1540 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1541 {
1542 /* align to 64 byte boundary. */
1543 while (p->next_insn_offset % 64)
1544 brw_NOP(p);
1545
1546 this->dispatch_width = dispatch_width;
1547 if (dispatch_width == 16)
1548 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1549
1550 int start_offset = p->next_insn_offset;
1551 int spill_count = 0, fill_count = 0;
1552 int loop_count = 0;
1553
1554 struct annotation_info annotation;
1555 memset(&annotation, 0, sizeof(annotation));
1556
1557 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1558 struct brw_reg src[3], dst;
1559 unsigned int last_insn_offset = p->next_insn_offset;
1560 bool multiple_instructions_emitted = false;
1561
1562 if (unlikely(debug_flag))
1563 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1564
1565 for (unsigned int i = 0; i < inst->sources; i++) {
1566 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1567
1568 /* The accumulator result appears to get used for the
1569 * conditional modifier generation. When negating a UD
1570 * value, there is a 33rd bit generated for the sign in the
1571 * accumulator value, so now you can't check, for example,
1572 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1573 */
1574 assert(!inst->conditional_mod ||
1575 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1576 !inst->src[i].negate);
1577 }
1578 dst = brw_reg_from_fs_reg(&inst->dst);
1579
1580 brw_set_default_predicate_control(p, inst->predicate);
1581 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1582 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1583 brw_set_default_saturate(p, inst->saturate);
1584 brw_set_default_mask_control(p, inst->force_writemask_all);
1585 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1586
1587 switch (inst->exec_size) {
1588 case 1:
1589 case 2:
1590 case 4:
1591 assert(inst->force_writemask_all);
1592 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1593 break;
1594 case 8:
1595 if (inst->force_sechalf) {
1596 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1597 } else {
1598 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1599 }
1600 break;
1601 case 16:
1602 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1603 break;
1604 default:
1605 unreachable(!"Invalid instruction width");
1606 }
1607
1608 switch (inst->opcode) {
1609 case BRW_OPCODE_MOV:
1610 brw_MOV(p, dst, src[0]);
1611 break;
1612 case BRW_OPCODE_ADD:
1613 brw_ADD(p, dst, src[0], src[1]);
1614 break;
1615 case BRW_OPCODE_MUL:
1616 brw_MUL(p, dst, src[0], src[1]);
1617 break;
1618 case BRW_OPCODE_AVG:
1619 brw_AVG(p, dst, src[0], src[1]);
1620 break;
1621 case BRW_OPCODE_MACH:
1622 brw_MACH(p, dst, src[0], src[1]);
1623 break;
1624
1625 case BRW_OPCODE_LINE:
1626 brw_LINE(p, dst, src[0], src[1]);
1627 break;
1628
1629 case BRW_OPCODE_MAD:
1630 assert(brw->gen >= 6);
1631 brw_set_default_access_mode(p, BRW_ALIGN_16);
1632 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1633 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1634 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1635 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1636 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1637 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1638
1639 if (inst->conditional_mod) {
1640 brw_inst_set_cond_modifier(brw, f, inst->conditional_mod);
1641 brw_inst_set_cond_modifier(brw, s, inst->conditional_mod);
1642 multiple_instructions_emitted = true;
1643 }
1644 } else {
1645 brw_MAD(p, dst, src[0], src[1], src[2]);
1646 }
1647 brw_set_default_access_mode(p, BRW_ALIGN_1);
1648 break;
1649
1650 case BRW_OPCODE_LRP:
1651 assert(brw->gen >= 6);
1652 brw_set_default_access_mode(p, BRW_ALIGN_16);
1653 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1654 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1655 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1656 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1657 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1658 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1659
1660 if (inst->conditional_mod) {
1661 brw_inst_set_cond_modifier(brw, f, inst->conditional_mod);
1662 brw_inst_set_cond_modifier(brw, s, inst->conditional_mod);
1663 multiple_instructions_emitted = true;
1664 }
1665 } else {
1666 brw_LRP(p, dst, src[0], src[1], src[2]);
1667 }
1668 brw_set_default_access_mode(p, BRW_ALIGN_1);
1669 break;
1670
1671 case BRW_OPCODE_FRC:
1672 brw_FRC(p, dst, src[0]);
1673 break;
1674 case BRW_OPCODE_RNDD:
1675 brw_RNDD(p, dst, src[0]);
1676 break;
1677 case BRW_OPCODE_RNDE:
1678 brw_RNDE(p, dst, src[0]);
1679 break;
1680 case BRW_OPCODE_RNDZ:
1681 brw_RNDZ(p, dst, src[0]);
1682 break;
1683
1684 case BRW_OPCODE_AND:
1685 brw_AND(p, dst, src[0], src[1]);
1686 break;
1687 case BRW_OPCODE_OR:
1688 brw_OR(p, dst, src[0], src[1]);
1689 break;
1690 case BRW_OPCODE_XOR:
1691 brw_XOR(p, dst, src[0], src[1]);
1692 break;
1693 case BRW_OPCODE_NOT:
1694 brw_NOT(p, dst, src[0]);
1695 break;
1696 case BRW_OPCODE_ASR:
1697 brw_ASR(p, dst, src[0], src[1]);
1698 break;
1699 case BRW_OPCODE_SHR:
1700 brw_SHR(p, dst, src[0], src[1]);
1701 break;
1702 case BRW_OPCODE_SHL:
1703 brw_SHL(p, dst, src[0], src[1]);
1704 break;
1705 case BRW_OPCODE_F32TO16:
1706 assert(brw->gen >= 7);
1707 brw_F32TO16(p, dst, src[0]);
1708 break;
1709 case BRW_OPCODE_F16TO32:
1710 assert(brw->gen >= 7);
1711 brw_F16TO32(p, dst, src[0]);
1712 break;
1713 case BRW_OPCODE_CMP:
1714 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1715 * that when the destination is a GRF that the dependency-clear bit on
1716 * the flag register is cleared early.
1717 *
1718 * Suggested workarounds are to disable coissuing CMP instructions
1719 * or to split CMP(16) instructions into two CMP(8) instructions.
1720 *
1721 * We choose to split into CMP(8) instructions since disabling
1722 * coissuing would affect CMP instructions not otherwise affected by
1723 * the errata.
1724 */
1725 if (dispatch_width == 16 && brw->gen == 7 && !brw->is_haswell) {
1726 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1727 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1728 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1729 firsthalf(src[0]), firsthalf(src[1]));
1730 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1731 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1732 sechalf(src[0]), sechalf(src[1]));
1733 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1734
1735 multiple_instructions_emitted = true;
1736 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1737 /* For unknown reasons, the aforementioned workaround is not
1738 * sufficient. Overriding the type when the destination is the
1739 * null register is necessary but not sufficient by itself.
1740 */
1741 assert(dst.nr == BRW_ARF_NULL);
1742 dst.type = BRW_REGISTER_TYPE_D;
1743 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1744 } else {
1745 unreachable("not reached");
1746 }
1747 } else {
1748 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1749 }
1750 break;
1751 case BRW_OPCODE_SEL:
1752 brw_SEL(p, dst, src[0], src[1]);
1753 break;
1754 case BRW_OPCODE_BFREV:
1755 assert(brw->gen >= 7);
1756 /* BFREV only supports UD type for src and dst. */
1757 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1758 retype(src[0], BRW_REGISTER_TYPE_UD));
1759 break;
1760 case BRW_OPCODE_FBH:
1761 assert(brw->gen >= 7);
1762 /* FBH only supports UD type for dst. */
1763 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1764 break;
1765 case BRW_OPCODE_FBL:
1766 assert(brw->gen >= 7);
1767 /* FBL only supports UD type for dst. */
1768 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1769 break;
1770 case BRW_OPCODE_CBIT:
1771 assert(brw->gen >= 7);
1772 /* CBIT only supports UD type for dst. */
1773 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1774 break;
1775 case BRW_OPCODE_ADDC:
1776 assert(brw->gen >= 7);
1777 brw_ADDC(p, dst, src[0], src[1]);
1778 break;
1779 case BRW_OPCODE_SUBB:
1780 assert(brw->gen >= 7);
1781 brw_SUBB(p, dst, src[0], src[1]);
1782 break;
1783 case BRW_OPCODE_MAC:
1784 brw_MAC(p, dst, src[0], src[1]);
1785 break;
1786
1787 case BRW_OPCODE_BFE:
1788 assert(brw->gen >= 7);
1789 brw_set_default_access_mode(p, BRW_ALIGN_16);
1790 if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
1791 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1792 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1793 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1794 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1795 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1796 } else {
1797 brw_BFE(p, dst, src[0], src[1], src[2]);
1798 }
1799 brw_set_default_access_mode(p, BRW_ALIGN_1);
1800 break;
1801
1802 case BRW_OPCODE_BFI1:
1803 assert(brw->gen >= 7);
1804 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1805 * should
1806 *
1807 * "Force BFI instructions to be executed always in SIMD8."
1808 */
1809 if (dispatch_width == 16 && brw->is_haswell) {
1810 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1811 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1812 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1813 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1814 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1815 } else {
1816 brw_BFI1(p, dst, src[0], src[1]);
1817 }
1818 break;
1819 case BRW_OPCODE_BFI2:
1820 assert(brw->gen >= 7);
1821 brw_set_default_access_mode(p, BRW_ALIGN_16);
1822 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1823 * should
1824 *
1825 * "Force BFI instructions to be executed always in SIMD8."
1826 *
1827 * Otherwise we would be able to emit compressed instructions like we
1828 * do for the other three-source instructions.
1829 */
1830 if (dispatch_width == 16 &&
1831 (brw->is_haswell || !brw_supports_simd16_3src(brw))) {
1832 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1833 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1834 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1835 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1836 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1837 } else {
1838 brw_BFI2(p, dst, src[0], src[1], src[2]);
1839 }
1840 brw_set_default_access_mode(p, BRW_ALIGN_1);
1841 break;
1842
1843 case BRW_OPCODE_IF:
1844 if (inst->src[0].file != BAD_FILE) {
1845 /* The instruction has an embedded compare (only allowed on gen6) */
1846 assert(brw->gen == 6);
1847 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1848 } else {
1849 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1850 }
1851 break;
1852
1853 case BRW_OPCODE_ELSE:
1854 brw_ELSE(p);
1855 break;
1856 case BRW_OPCODE_ENDIF:
1857 brw_ENDIF(p);
1858 break;
1859
1860 case BRW_OPCODE_DO:
1861 brw_DO(p, BRW_EXECUTE_8);
1862 break;
1863
1864 case BRW_OPCODE_BREAK:
1865 brw_BREAK(p);
1866 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1867 break;
1868 case BRW_OPCODE_CONTINUE:
1869 brw_CONT(p);
1870 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1871 break;
1872
1873 case BRW_OPCODE_WHILE:
1874 brw_WHILE(p);
1875 loop_count++;
1876 break;
1877
1878 case SHADER_OPCODE_RCP:
1879 case SHADER_OPCODE_RSQ:
1880 case SHADER_OPCODE_SQRT:
1881 case SHADER_OPCODE_EXP2:
1882 case SHADER_OPCODE_LOG2:
1883 case SHADER_OPCODE_SIN:
1884 case SHADER_OPCODE_COS:
1885 assert(brw->gen < 6 || inst->mlen == 0);
1886 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1887 if (brw->gen >= 7) {
1888 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1889 brw_null_reg());
1890 } else if (brw->gen == 6) {
1891 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1892 } else if (brw->gen == 5 || brw->is_g4x) {
1893 generate_math_g45(inst, dst, src[0]);
1894 } else {
1895 generate_math_gen4(inst, dst, src[0]);
1896 }
1897 break;
1898 case SHADER_OPCODE_INT_QUOTIENT:
1899 case SHADER_OPCODE_INT_REMAINDER:
1900 case SHADER_OPCODE_POW:
1901 assert(brw->gen < 6 || inst->mlen == 0);
1902 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1903 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1904 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1905 } else if (brw->gen >= 6) {
1906 generate_math_gen6(inst, dst, src[0], src[1]);
1907 } else {
1908 generate_math_gen4(inst, dst, src[0]);
1909 }
1910 break;
1911 case FS_OPCODE_PIXEL_X:
1912 generate_pixel_xy(dst, true);
1913 break;
1914 case FS_OPCODE_PIXEL_Y:
1915 generate_pixel_xy(dst, false);
1916 break;
1917 case FS_OPCODE_CINTERP:
1918 brw_MOV(p, dst, src[0]);
1919 break;
1920 case FS_OPCODE_LINTERP:
1921 generate_linterp(inst, dst, src);
1922 break;
1923 case SHADER_OPCODE_TEX:
1924 case FS_OPCODE_TXB:
1925 case SHADER_OPCODE_TXD:
1926 case SHADER_OPCODE_TXF:
1927 case SHADER_OPCODE_TXF_CMS:
1928 case SHADER_OPCODE_TXF_UMS:
1929 case SHADER_OPCODE_TXF_MCS:
1930 case SHADER_OPCODE_TXL:
1931 case SHADER_OPCODE_TXS:
1932 case SHADER_OPCODE_LOD:
1933 case SHADER_OPCODE_TG4:
1934 case SHADER_OPCODE_TG4_OFFSET:
1935 generate_tex(inst, dst, src[0], src[1]);
1936 break;
1937 case FS_OPCODE_DDX_COARSE:
1938 case FS_OPCODE_DDX_FINE:
1939 generate_ddx(inst->opcode, dst, src[0]);
1940 break;
1941 case FS_OPCODE_DDY_COARSE:
1942 case FS_OPCODE_DDY_FINE:
1943 assert(src[1].file == BRW_IMMEDIATE_VALUE);
1944 generate_ddy(inst->opcode, dst, src[0], src[1].dw1.ud);
1945 break;
1946
1947 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1948 generate_scratch_write(inst, src[0]);
1949 spill_count++;
1950 break;
1951
1952 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1953 generate_scratch_read(inst, dst);
1954 fill_count++;
1955 break;
1956
1957 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1958 generate_scratch_read_gen7(inst, dst);
1959 fill_count++;
1960 break;
1961
1962 case SHADER_OPCODE_URB_WRITE_SIMD8:
1963 generate_urb_write(inst, src[0]);
1964 break;
1965
1966 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1967 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1968 break;
1969
1970 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1971 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1972 break;
1973
1974 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1975 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1976 break;
1977
1978 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1979 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1980 break;
1981
1982 case FS_OPCODE_REP_FB_WRITE:
1983 case FS_OPCODE_FB_WRITE:
1984 generate_fb_write(inst, src[0]);
1985 break;
1986
1987 case FS_OPCODE_BLORP_FB_WRITE:
1988 generate_blorp_fb_write(inst);
1989 break;
1990
1991 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1992 generate_mov_dispatch_to_flags(inst);
1993 break;
1994
1995 case FS_OPCODE_DISCARD_JUMP:
1996 generate_discard_jump(inst);
1997 break;
1998
1999 case SHADER_OPCODE_SHADER_TIME_ADD:
2000 generate_shader_time_add(inst, src[0], src[1], src[2]);
2001 break;
2002
2003 case SHADER_OPCODE_UNTYPED_ATOMIC:
2004 generate_untyped_atomic(inst, dst, src[0], src[1], src[2]);
2005 break;
2006
2007 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2008 generate_untyped_surface_read(inst, dst, src[0], src[1]);
2009 break;
2010
2011 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2012 generate_set_simd4x2_offset(inst, dst, src[0]);
2013 break;
2014
2015 case FS_OPCODE_SET_OMASK:
2016 generate_set_omask(inst, dst, src[0]);
2017 break;
2018
2019 case FS_OPCODE_SET_SAMPLE_ID:
2020 generate_set_sample_id(inst, dst, src[0], src[1]);
2021 break;
2022
2023 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2024 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2025 break;
2026
2027 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2028 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2029 generate_unpack_half_2x16_split(inst, dst, src[0]);
2030 break;
2031
2032 case FS_OPCODE_PLACEHOLDER_HALT:
2033 /* This is the place where the final HALT needs to be inserted if
2034 * we've emitted any discards. If not, this will emit no code.
2035 */
2036 if (!patch_discard_jumps_to_fb_writes()) {
2037 if (unlikely(debug_flag)) {
2038 annotation.ann_count--;
2039 }
2040 }
2041 break;
2042
2043 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2044 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2045 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2046 break;
2047
2048 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2049 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2050 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2051 break;
2052
2053 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2054 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2055 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2056 break;
2057
2058 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2059 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2060 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2061 break;
2062
2063 default:
2064 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
2065 _mesa_problem(ctx, "Unsupported opcode `%s' in %s",
2066 opcode_descs[inst->opcode].name, stage_abbrev);
2067 } else {
2068 _mesa_problem(ctx, "Unsupported opcode %d in %s", inst->opcode,
2069 stage_abbrev);
2070 }
2071 abort();
2072
2073 case SHADER_OPCODE_LOAD_PAYLOAD:
2074 unreachable("Should be lowered by lower_load_payload()");
2075 }
2076
2077 if (multiple_instructions_emitted)
2078 continue;
2079
2080 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2081 assert(p->next_insn_offset == last_insn_offset + 16 ||
2082 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2083 "emitting more than 1 instruction");
2084
2085 brw_inst *last = &p->store[last_insn_offset / 16];
2086
2087 if (inst->conditional_mod)
2088 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
2089 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
2090 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
2091 }
2092 }
2093
2094 brw_set_uip_jip(p);
2095 annotation_finalize(&annotation, p->next_insn_offset);
2096
2097 int before_size = p->next_insn_offset - start_offset;
2098 brw_compact_instructions(p, start_offset, annotation.ann_count,
2099 annotation.ann);
2100 int after_size = p->next_insn_offset - start_offset;
2101
2102 if (unlikely(debug_flag)) {
2103 fprintf(stderr, "Native code for %s\n"
2104 "SIMD%d shader: %d instructions. %d loops. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2105 " bytes (%.0f%%)\n",
2106 shader_name, dispatch_width, before_size / 16, loop_count,
2107 spill_count, fill_count, promoted_constants, before_size, after_size,
2108 100.0f * (before_size - after_size) / before_size);
2109
2110 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
2111 ralloc_free(annotation.ann);
2112 }
2113
2114 static GLuint msg_id = 0;
2115 _mesa_gl_debug(&brw->ctx, &msg_id,
2116 MESA_DEBUG_SOURCE_SHADER_COMPILER,
2117 MESA_DEBUG_TYPE_OTHER,
2118 MESA_DEBUG_SEVERITY_NOTIFICATION,
2119 "%s SIMD%d shader: %d inst, %d loops, %d:%d spills:fills, "
2120 "Promoted %u constants, compacted %d to %d bytes.\n",
2121 stage_abbrev, dispatch_width, before_size / 16, loop_count,
2122 spill_count, fill_count, promoted_constants, before_size, after_size);
2123
2124 return start_offset;
2125 }
2126
2127 const unsigned *
2128 fs_generator::get_assembly(unsigned int *assembly_size)
2129 {
2130 return brw_get_program(p, assembly_size);
2131 }