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i965: Use SSE4.1 runtime detection for intel_miptree_map.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 fs_generator::fs_generator(struct brw_context *brw,
40 void *mem_ctx,
41 const struct brw_wm_prog_key *key,
42 struct brw_wm_prog_data *prog_data,
43 struct gl_shader_program *prog,
44 struct gl_fragment_program *fp,
45 bool dual_source_output)
46
47 : brw(brw), key(key), prog_data(prog_data), prog(prog), fp(fp),
48 dual_source_output(dual_source_output), mem_ctx(mem_ctx)
49 {
50 ctx = &brw->ctx;
51
52 p = rzalloc(mem_ctx, struct brw_compile);
53 brw_init_compile(brw, p, mem_ctx);
54 }
55
56 fs_generator::~fs_generator()
57 {
58 }
59
60 void
61 fs_generator::patch_discard_jumps_to_fb_writes()
62 {
63 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
64 return;
65
66 /* There is a somewhat strange undocumented requirement of using
67 * HALT, according to the simulator. If some channel has HALTed to
68 * a particular UIP, then by the end of the program, every channel
69 * must have HALTed to that UIP. Furthermore, the tracking is a
70 * stack, so you can't do the final halt of a UIP after starting
71 * halting to a new UIP.
72 *
73 * Symptoms of not emitting this instruction on actual hardware
74 * included GPU hangs and sparkly rendering on the piglit discard
75 * tests.
76 */
77 struct brw_instruction *last_halt = gen6_HALT(p);
78 last_halt->bits3.break_cont.uip = 2;
79 last_halt->bits3.break_cont.jip = 2;
80
81 int ip = p->nr_insn;
82
83 foreach_list(node, &this->discard_halt_patches) {
84 ip_record *patch_ip = (ip_record *)node;
85 struct brw_instruction *patch = &p->store[patch_ip->ip];
86
87 assert(patch->header.opcode == BRW_OPCODE_HALT);
88 /* HALT takes a half-instruction distance from the pre-incremented IP. */
89 patch->bits3.break_cont.uip = (ip - patch_ip->ip) * 2;
90 }
91
92 this->discard_halt_patches.make_empty();
93 }
94
95 void
96 fs_generator::generate_fb_write(fs_inst *inst)
97 {
98 bool eot = inst->eot;
99 struct brw_reg implied_header;
100 uint32_t msg_control;
101
102 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
103 * move, here's g1.
104 */
105 brw_push_insn_state(p);
106 brw_set_mask_control(p, BRW_MASK_DISABLE);
107 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
108 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
109
110 if (inst->header_present) {
111 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
112 * present.
113 */
114 if ((fp && fp->UsesKill) || key->alpha_test_func) {
115 struct brw_reg pixel_mask;
116
117 if (brw->gen >= 6)
118 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
119 else
120 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
121
122 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
123 }
124
125 if (brw->gen >= 6) {
126 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
127 brw_MOV(p,
128 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
129 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
130 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
131
132 if (inst->target > 0 && key->replicate_alpha) {
133 /* Set "Source0 Alpha Present to RenderTarget" bit in message
134 * header.
135 */
136 brw_OR(p,
137 vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)),
138 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
139 brw_imm_ud(0x1 << 11));
140 }
141
142 if (inst->target > 0) {
143 /* Set the render target index for choosing BLEND_STATE. */
144 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
145 inst->base_mrf, 2),
146 BRW_REGISTER_TYPE_UD),
147 brw_imm_ud(inst->target));
148 }
149
150 implied_header = brw_null_reg();
151 } else {
152 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
153
154 brw_MOV(p,
155 brw_message_reg(inst->base_mrf + 1),
156 brw_vec8_grf(1, 0));
157 }
158 } else {
159 implied_header = brw_null_reg();
160 }
161
162 if (this->dual_source_output)
163 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
164 else if (dispatch_width == 16)
165 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
166 else
167 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
168
169 brw_pop_insn_state(p);
170
171 uint32_t surf_index =
172 prog_data->binding_table.render_target_start + inst->target;
173 brw_fb_WRITE(p,
174 dispatch_width,
175 inst->base_mrf,
176 implied_header,
177 msg_control,
178 surf_index,
179 inst->mlen,
180 0,
181 eot,
182 inst->header_present);
183
184 brw_mark_surface_used(&prog_data->base, surf_index);
185 }
186
187 void
188 fs_generator::generate_blorp_fb_write(fs_inst *inst)
189 {
190 brw_fb_WRITE(p,
191 16 /* dispatch_width */,
192 inst->base_mrf,
193 brw_reg_from_fs_reg(&inst->src[0]),
194 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
195 inst->target,
196 inst->mlen,
197 0,
198 true,
199 inst->header_present);
200 }
201
202 /* Computes the integer pixel x,y values from the origin.
203 *
204 * This is the basis of gl_FragCoord computation, but is also used
205 * pre-gen6 for computing the deltas from v0 for computing
206 * interpolation.
207 */
208 void
209 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
210 {
211 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
212 struct brw_reg src;
213 struct brw_reg deltas;
214
215 if (is_x) {
216 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
217 deltas = brw_imm_v(0x10101010);
218 } else {
219 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
220 deltas = brw_imm_v(0x11001100);
221 }
222
223 if (dispatch_width == 16) {
224 dst = vec16(dst);
225 }
226
227 /* We do this SIMD8 or SIMD16, but since the destination is UW we
228 * don't do compression in the SIMD16 case.
229 */
230 brw_push_insn_state(p);
231 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
232 brw_ADD(p, dst, src, deltas);
233 brw_pop_insn_state(p);
234 }
235
236 void
237 fs_generator::generate_linterp(fs_inst *inst,
238 struct brw_reg dst, struct brw_reg *src)
239 {
240 struct brw_reg delta_x = src[0];
241 struct brw_reg delta_y = src[1];
242 struct brw_reg interp = src[2];
243
244 if (brw->has_pln &&
245 delta_y.nr == delta_x.nr + 1 &&
246 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
247 brw_PLN(p, dst, interp, delta_x);
248 } else {
249 brw_LINE(p, brw_null_reg(), interp, delta_x);
250 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
251 }
252 }
253
254 void
255 fs_generator::generate_math1_gen7(fs_inst *inst,
256 struct brw_reg dst,
257 struct brw_reg src0)
258 {
259 assert(inst->mlen == 0);
260 brw_math(p, dst,
261 brw_math_function(inst->opcode),
262 0, src0,
263 BRW_MATH_DATA_VECTOR,
264 BRW_MATH_PRECISION_FULL);
265 }
266
267 void
268 fs_generator::generate_math2_gen7(fs_inst *inst,
269 struct brw_reg dst,
270 struct brw_reg src0,
271 struct brw_reg src1)
272 {
273 assert(inst->mlen == 0);
274 brw_math2(p, dst, brw_math_function(inst->opcode), src0, src1);
275 }
276
277 void
278 fs_generator::generate_math1_gen6(fs_inst *inst,
279 struct brw_reg dst,
280 struct brw_reg src0)
281 {
282 int op = brw_math_function(inst->opcode);
283
284 assert(inst->mlen == 0);
285
286 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
287 brw_math(p, dst,
288 op,
289 0, src0,
290 BRW_MATH_DATA_VECTOR,
291 BRW_MATH_PRECISION_FULL);
292
293 if (dispatch_width == 16) {
294 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
295 brw_math(p, sechalf(dst),
296 op,
297 0, sechalf(src0),
298 BRW_MATH_DATA_VECTOR,
299 BRW_MATH_PRECISION_FULL);
300 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
301 }
302 }
303
304 void
305 fs_generator::generate_math2_gen6(fs_inst *inst,
306 struct brw_reg dst,
307 struct brw_reg src0,
308 struct brw_reg src1)
309 {
310 int op = brw_math_function(inst->opcode);
311
312 assert(inst->mlen == 0);
313
314 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
315 brw_math2(p, dst, op, src0, src1);
316
317 if (dispatch_width == 16) {
318 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
319 brw_math2(p, sechalf(dst), op, sechalf(src0), sechalf(src1));
320 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
321 }
322 }
323
324 void
325 fs_generator::generate_math_gen4(fs_inst *inst,
326 struct brw_reg dst,
327 struct brw_reg src)
328 {
329 int op = brw_math_function(inst->opcode);
330
331 assert(inst->mlen >= 1);
332
333 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
334 brw_math(p, dst,
335 op,
336 inst->base_mrf, src,
337 BRW_MATH_DATA_VECTOR,
338 BRW_MATH_PRECISION_FULL);
339
340 if (dispatch_width == 16) {
341 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
342 brw_math(p, sechalf(dst),
343 op,
344 inst->base_mrf + 1, sechalf(src),
345 BRW_MATH_DATA_VECTOR,
346 BRW_MATH_PRECISION_FULL);
347
348 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
349 }
350 }
351
352 void
353 fs_generator::generate_math_g45(fs_inst *inst,
354 struct brw_reg dst,
355 struct brw_reg src)
356 {
357 if (inst->opcode == SHADER_OPCODE_POW ||
358 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
359 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
360 generate_math_gen4(inst, dst, src);
361 return;
362 }
363
364 int op = brw_math_function(inst->opcode);
365
366 assert(inst->mlen >= 1);
367
368 brw_math(p, dst,
369 op,
370 inst->base_mrf, src,
371 BRW_MATH_DATA_VECTOR,
372 BRW_MATH_PRECISION_FULL);
373 }
374
375 void
376 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
377 {
378 int msg_type = -1;
379 int rlen = 4;
380 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
381 uint32_t return_format;
382
383 switch (dst.type) {
384 case BRW_REGISTER_TYPE_D:
385 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
386 break;
387 case BRW_REGISTER_TYPE_UD:
388 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
389 break;
390 default:
391 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
392 break;
393 }
394
395 if (dispatch_width == 16 &&
396 !inst->force_uncompressed && !inst->force_sechalf)
397 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
398
399 if (brw->gen >= 5) {
400 switch (inst->opcode) {
401 case SHADER_OPCODE_TEX:
402 if (inst->shadow_compare) {
403 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
404 } else {
405 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
406 }
407 break;
408 case FS_OPCODE_TXB:
409 if (inst->shadow_compare) {
410 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
411 } else {
412 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
413 }
414 break;
415 case SHADER_OPCODE_TXL:
416 if (inst->shadow_compare) {
417 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
418 } else {
419 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
420 }
421 break;
422 case SHADER_OPCODE_TXS:
423 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
424 break;
425 case SHADER_OPCODE_TXD:
426 if (inst->shadow_compare) {
427 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
428 assert(brw->is_haswell);
429 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
430 } else {
431 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
432 }
433 break;
434 case SHADER_OPCODE_TXF:
435 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
436 break;
437 case SHADER_OPCODE_TXF_CMS:
438 if (brw->gen >= 7)
439 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
440 else
441 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
442 break;
443 case SHADER_OPCODE_TXF_UMS:
444 assert(brw->gen >= 7);
445 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
446 break;
447 case SHADER_OPCODE_TXF_MCS:
448 assert(brw->gen >= 7);
449 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
450 break;
451 case SHADER_OPCODE_LOD:
452 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
453 break;
454 case SHADER_OPCODE_TG4:
455 if (inst->shadow_compare) {
456 assert(brw->gen >= 7);
457 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
458 } else {
459 assert(brw->gen >= 6);
460 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
461 }
462 break;
463 case SHADER_OPCODE_TG4_OFFSET:
464 assert(brw->gen >= 7);
465 if (inst->shadow_compare) {
466 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
467 } else {
468 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
469 }
470 break;
471 default:
472 assert(!"not reached");
473 break;
474 }
475 } else {
476 switch (inst->opcode) {
477 case SHADER_OPCODE_TEX:
478 /* Note that G45 and older determines shadow compare and dispatch width
479 * from message length for most messages.
480 */
481 assert(dispatch_width == 8);
482 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
483 if (inst->shadow_compare) {
484 assert(inst->mlen == 6);
485 } else {
486 assert(inst->mlen <= 4);
487 }
488 break;
489 case FS_OPCODE_TXB:
490 if (inst->shadow_compare) {
491 assert(inst->mlen == 6);
492 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
493 } else {
494 assert(inst->mlen == 9);
495 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
496 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
497 }
498 break;
499 case SHADER_OPCODE_TXL:
500 if (inst->shadow_compare) {
501 assert(inst->mlen == 6);
502 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
503 } else {
504 assert(inst->mlen == 9);
505 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
506 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
507 }
508 break;
509 case SHADER_OPCODE_TXD:
510 /* There is no sample_d_c message; comparisons are done manually */
511 assert(inst->mlen == 7 || inst->mlen == 10);
512 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
513 break;
514 case SHADER_OPCODE_TXF:
515 assert(inst->mlen == 9);
516 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
517 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
518 break;
519 case SHADER_OPCODE_TXS:
520 assert(inst->mlen == 3);
521 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
522 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
523 break;
524 default:
525 assert(!"not reached");
526 break;
527 }
528 }
529 assert(msg_type != -1);
530
531 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
532 rlen = 8;
533 dst = vec16(dst);
534 }
535
536 if (brw->gen >= 7 && inst->header_present && dispatch_width == 16) {
537 /* The send-from-GRF for SIMD16 texturing with a header has an extra
538 * hardware register allocated to it, which we need to skip over (since
539 * our coordinates in the payload are in the even-numbered registers,
540 * and the header comes right before the first one).
541 */
542 assert(src.file == BRW_GENERAL_REGISTER_FILE);
543 src.nr++;
544 }
545
546 /* Load the message header if present. If there's a texture offset,
547 * we need to set it up explicitly and load the offset bitfield.
548 * Otherwise, we can use an implied move from g0 to the first message reg.
549 */
550 if (inst->header_present) {
551 if (brw->gen < 6 && !inst->texture_offset) {
552 /* Set up an implied move from g0 to the MRF. */
553 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
554 } else {
555 struct brw_reg header_reg;
556
557 if (brw->gen >= 7) {
558 header_reg = src;
559 } else {
560 assert(inst->base_mrf != -1);
561 header_reg = brw_message_reg(inst->base_mrf);
562 }
563
564 brw_push_insn_state(p);
565 brw_set_mask_control(p, BRW_MASK_DISABLE);
566 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
567 /* Explicitly set up the message header by copying g0 to the MRF. */
568 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
569
570 if (inst->texture_offset) {
571 /* Set the offset bits in DWord 2. */
572 brw_MOV(p, get_element_ud(header_reg, 2),
573 brw_imm_ud(inst->texture_offset));
574 }
575
576 if (inst->sampler >= 16) {
577 /* The "Sampler Index" field can only store values between 0 and 15.
578 * However, we can add an offset to the "Sampler State Pointer"
579 * field, effectively selecting a different set of 16 samplers.
580 *
581 * The "Sampler State Pointer" needs to be aligned to a 32-byte
582 * offset, and each sampler state is only 16-bytes, so we can't
583 * exclusively use the offset - we have to use both.
584 */
585 assert(brw->is_haswell); /* field only exists on Haswell */
586 brw_ADD(p,
587 get_element_ud(header_reg, 3),
588 get_element_ud(brw_vec8_grf(0, 0), 3),
589 brw_imm_ud(16 * (inst->sampler / 16) *
590 sizeof(gen7_sampler_state)));
591 }
592 brw_pop_insn_state(p);
593 }
594 }
595
596 uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
597 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
598 ? prog_data->base.binding_table.gather_texture_start
599 : prog_data->base.binding_table.texture_start) + inst->sampler;
600
601 brw_SAMPLE(p,
602 retype(dst, BRW_REGISTER_TYPE_UW),
603 inst->base_mrf,
604 src,
605 surface_index,
606 inst->sampler % 16,
607 msg_type,
608 rlen,
609 inst->mlen,
610 inst->header_present,
611 simd_mode,
612 return_format);
613
614 brw_mark_surface_used(&prog_data->base, surface_index);
615 }
616
617
618 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
619 * looking like:
620 *
621 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
622 *
623 * Ideally, we want to produce:
624 *
625 * DDX DDY
626 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
627 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
628 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
629 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
630 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
631 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
632 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
633 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
634 *
635 * and add another set of two more subspans if in 16-pixel dispatch mode.
636 *
637 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
638 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
639 * pair. But the ideal approximation may impose a huge performance cost on
640 * sample_d. On at least Haswell, sample_d instruction does some
641 * optimizations if the same LOD is used for all pixels in the subspan.
642 *
643 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
644 * appropriate swizzling.
645 */
646 void
647 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
648 {
649 unsigned vstride, width;
650
651 if (key->high_quality_derivatives) {
652 /* produce accurate derivatives */
653 vstride = BRW_VERTICAL_STRIDE_2;
654 width = BRW_WIDTH_2;
655 }
656 else {
657 /* replicate the derivative at the top-left pixel to other pixels */
658 vstride = BRW_VERTICAL_STRIDE_4;
659 width = BRW_WIDTH_4;
660 }
661
662 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
663 BRW_REGISTER_TYPE_F,
664 vstride,
665 width,
666 BRW_HORIZONTAL_STRIDE_0,
667 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
668 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
669 BRW_REGISTER_TYPE_F,
670 vstride,
671 width,
672 BRW_HORIZONTAL_STRIDE_0,
673 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
674 brw_ADD(p, dst, src0, negate(src1));
675 }
676
677 /* The negate_value boolean is used to negate the derivative computation for
678 * FBOs, since they place the origin at the upper left instead of the lower
679 * left.
680 */
681 void
682 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
683 bool negate_value)
684 {
685 if (key->high_quality_derivatives) {
686 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
687 * Region Restrictions):
688 *
689 * In Align16 access mode, SIMD16 is not allowed for DW operations
690 * and SIMD8 is not allowed for DF operations.
691 *
692 * In this context, "DW operations" means "operations acting on 32-bit
693 * values", so it includes operations on floats.
694 *
695 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
696 * (Instruction Compression -> Rules and Restrictions):
697 *
698 * A compressed instruction must be in Align1 access mode. Align16
699 * mode instructions cannot be compressed.
700 *
701 * Similar text exists in the g45 PRM.
702 *
703 * On these platforms, if we're building a SIMD16 shader, we need to
704 * manually unroll to a pair of SIMD8 instructions.
705 */
706 bool unroll_to_simd8 =
707 (dispatch_width == 16 &&
708 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
709
710 /* produce accurate derivatives */
711 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
712 BRW_REGISTER_TYPE_F,
713 BRW_VERTICAL_STRIDE_4,
714 BRW_WIDTH_4,
715 BRW_HORIZONTAL_STRIDE_1,
716 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
717 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
718 BRW_REGISTER_TYPE_F,
719 BRW_VERTICAL_STRIDE_4,
720 BRW_WIDTH_4,
721 BRW_HORIZONTAL_STRIDE_1,
722 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
723 brw_push_insn_state(p);
724 brw_set_access_mode(p, BRW_ALIGN_16);
725 if (unroll_to_simd8)
726 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
727 if (negate_value)
728 brw_ADD(p, dst, src1, negate(src0));
729 else
730 brw_ADD(p, dst, src0, negate(src1));
731 if (unroll_to_simd8) {
732 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
733 src0 = sechalf(src0);
734 src1 = sechalf(src1);
735 dst = sechalf(dst);
736 if (negate_value)
737 brw_ADD(p, dst, src1, negate(src0));
738 else
739 brw_ADD(p, dst, src0, negate(src1));
740 }
741 brw_pop_insn_state(p);
742 } else {
743 /* replicate the derivative at the top-left pixel to other pixels */
744 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
745 BRW_REGISTER_TYPE_F,
746 BRW_VERTICAL_STRIDE_4,
747 BRW_WIDTH_4,
748 BRW_HORIZONTAL_STRIDE_0,
749 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
750 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
751 BRW_REGISTER_TYPE_F,
752 BRW_VERTICAL_STRIDE_4,
753 BRW_WIDTH_4,
754 BRW_HORIZONTAL_STRIDE_0,
755 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
756 if (negate_value)
757 brw_ADD(p, dst, src1, negate(src0));
758 else
759 brw_ADD(p, dst, src0, negate(src1));
760 }
761 }
762
763 void
764 fs_generator::generate_discard_jump(fs_inst *inst)
765 {
766 assert(brw->gen >= 6);
767
768 /* This HALT will be patched up at FB write time to point UIP at the end of
769 * the program, and at brw_uip_jip() JIP will be set to the end of the
770 * current block (or the program).
771 */
772 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
773
774 brw_push_insn_state(p);
775 brw_set_mask_control(p, BRW_MASK_DISABLE);
776 gen6_HALT(p);
777 brw_pop_insn_state(p);
778 }
779
780 void
781 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
782 {
783 assert(inst->mlen != 0);
784
785 brw_MOV(p,
786 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
787 retype(src, BRW_REGISTER_TYPE_UD));
788 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
789 dispatch_width / 8, inst->offset);
790 }
791
792 void
793 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
794 {
795 assert(inst->mlen != 0);
796
797 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
798 dispatch_width / 8, inst->offset);
799 }
800
801 void
802 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
803 {
804 gen7_block_read_scratch(p, dst, dispatch_width / 8, inst->offset);
805 }
806
807 void
808 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
809 struct brw_reg dst,
810 struct brw_reg index,
811 struct brw_reg offset)
812 {
813 assert(inst->mlen != 0);
814
815 assert(index.file == BRW_IMMEDIATE_VALUE &&
816 index.type == BRW_REGISTER_TYPE_UD);
817 uint32_t surf_index = index.dw1.ud;
818
819 assert(offset.file == BRW_IMMEDIATE_VALUE &&
820 offset.type == BRW_REGISTER_TYPE_UD);
821 uint32_t read_offset = offset.dw1.ud;
822
823 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
824 read_offset, surf_index);
825
826 brw_mark_surface_used(&prog_data->base, surf_index);
827 }
828
829 void
830 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
831 struct brw_reg dst,
832 struct brw_reg index,
833 struct brw_reg offset)
834 {
835 assert(inst->mlen == 0);
836
837 assert(index.file == BRW_IMMEDIATE_VALUE &&
838 index.type == BRW_REGISTER_TYPE_UD);
839 uint32_t surf_index = index.dw1.ud;
840
841 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
842 /* Reference just the dword we need, to avoid angering validate_reg(). */
843 offset = brw_vec1_grf(offset.nr, 0);
844
845 brw_push_insn_state(p);
846 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
847 brw_set_mask_control(p, BRW_MASK_DISABLE);
848 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
849 brw_pop_insn_state(p);
850
851 /* We use the SIMD4x2 mode because we want to end up with 4 components in
852 * the destination loaded consecutively from the same offset (which appears
853 * in the first component, and the rest are ignored).
854 */
855 dst.width = BRW_WIDTH_4;
856 brw_set_dest(p, send, dst);
857 brw_set_src0(p, send, offset);
858 brw_set_sampler_message(p, send,
859 surf_index,
860 0, /* LD message ignores sampler unit */
861 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
862 1, /* rlen */
863 1, /* mlen */
864 false, /* no header */
865 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
866 0);
867
868 brw_mark_surface_used(&prog_data->base, surf_index);
869 }
870
871 void
872 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
873 struct brw_reg dst,
874 struct brw_reg index,
875 struct brw_reg offset)
876 {
877 assert(brw->gen < 7); /* Should use the gen7 variant. */
878 assert(inst->header_present);
879 assert(inst->mlen);
880
881 assert(index.file == BRW_IMMEDIATE_VALUE &&
882 index.type == BRW_REGISTER_TYPE_UD);
883 uint32_t surf_index = index.dw1.ud;
884
885 uint32_t simd_mode, rlen, msg_type;
886 if (dispatch_width == 16) {
887 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
888 rlen = 8;
889 } else {
890 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
891 rlen = 4;
892 }
893
894 if (brw->gen >= 5)
895 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
896 else {
897 /* We always use the SIMD16 message so that we only have to load U, and
898 * not V or R.
899 */
900 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
901 assert(inst->mlen == 3);
902 assert(inst->regs_written == 8);
903 rlen = 8;
904 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
905 }
906
907 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
908 BRW_REGISTER_TYPE_D);
909 brw_MOV(p, offset_mrf, offset);
910
911 struct brw_reg header = brw_vec8_grf(0, 0);
912 gen6_resolve_implied_move(p, &header, inst->base_mrf);
913
914 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
915 send->header.compression_control = BRW_COMPRESSION_NONE;
916 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
917 brw_set_src0(p, send, header);
918 if (brw->gen < 6)
919 send->header.destreg__conditionalmod = inst->base_mrf;
920
921 /* Our surface is set up as floats, regardless of what actual data is
922 * stored in it.
923 */
924 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
925 brw_set_sampler_message(p, send,
926 surf_index,
927 0, /* sampler (unused) */
928 msg_type,
929 rlen,
930 inst->mlen,
931 inst->header_present,
932 simd_mode,
933 return_format);
934
935 brw_mark_surface_used(&prog_data->base, surf_index);
936 }
937
938 void
939 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
940 struct brw_reg dst,
941 struct brw_reg index,
942 struct brw_reg offset)
943 {
944 assert(brw->gen >= 7);
945 /* Varying-offset pull constant loads are treated as a normal expression on
946 * gen7, so the fact that it's a send message is hidden at the IR level.
947 */
948 assert(!inst->header_present);
949 assert(!inst->mlen);
950
951 assert(index.file == BRW_IMMEDIATE_VALUE &&
952 index.type == BRW_REGISTER_TYPE_UD);
953 uint32_t surf_index = index.dw1.ud;
954
955 uint32_t simd_mode, rlen, mlen;
956 if (dispatch_width == 16) {
957 mlen = 2;
958 rlen = 8;
959 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
960 } else {
961 mlen = 1;
962 rlen = 4;
963 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
964 }
965
966 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
967 brw_set_dest(p, send, dst);
968 brw_set_src0(p, send, offset);
969 brw_set_sampler_message(p, send,
970 surf_index,
971 0, /* LD message ignores sampler unit */
972 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
973 rlen,
974 mlen,
975 false, /* no header */
976 simd_mode,
977 0);
978
979 brw_mark_surface_used(&prog_data->base, surf_index);
980 }
981
982 /**
983 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
984 * into the flags register (f0.0).
985 *
986 * Used only on Gen6 and above.
987 */
988 void
989 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
990 {
991 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
992 struct brw_reg dispatch_mask;
993
994 if (brw->gen >= 6)
995 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
996 else
997 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
998
999 brw_push_insn_state(p);
1000 brw_set_mask_control(p, BRW_MASK_DISABLE);
1001 brw_MOV(p, flags, dispatch_mask);
1002 brw_pop_insn_state(p);
1003 }
1004
1005
1006 static uint32_t brw_file_from_reg(fs_reg *reg)
1007 {
1008 switch (reg->file) {
1009 case GRF:
1010 return BRW_GENERAL_REGISTER_FILE;
1011 case MRF:
1012 return BRW_MESSAGE_REGISTER_FILE;
1013 case IMM:
1014 return BRW_IMMEDIATE_VALUE;
1015 default:
1016 assert(!"not reached");
1017 return BRW_GENERAL_REGISTER_FILE;
1018 }
1019 }
1020
1021 struct brw_reg
1022 brw_reg_from_fs_reg(fs_reg *reg)
1023 {
1024 struct brw_reg brw_reg;
1025
1026 switch (reg->file) {
1027 case GRF:
1028 case MRF:
1029 if (reg->stride == 0) {
1030 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
1031 } else {
1032 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1033 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
1034 }
1035
1036 brw_reg = retype(brw_reg, reg->type);
1037 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
1038 break;
1039 case IMM:
1040 switch (reg->type) {
1041 case BRW_REGISTER_TYPE_F:
1042 brw_reg = brw_imm_f(reg->imm.f);
1043 break;
1044 case BRW_REGISTER_TYPE_D:
1045 brw_reg = brw_imm_d(reg->imm.i);
1046 break;
1047 case BRW_REGISTER_TYPE_UD:
1048 brw_reg = brw_imm_ud(reg->imm.u);
1049 break;
1050 default:
1051 assert(!"not reached");
1052 brw_reg = brw_null_reg();
1053 break;
1054 }
1055 break;
1056 case HW_REG:
1057 assert(reg->type == reg->fixed_hw_reg.type);
1058 brw_reg = reg->fixed_hw_reg;
1059 break;
1060 case BAD_FILE:
1061 /* Probably unused. */
1062 brw_reg = brw_null_reg();
1063 break;
1064 case UNIFORM:
1065 assert(!"not reached");
1066 brw_reg = brw_null_reg();
1067 break;
1068 default:
1069 assert(!"not reached");
1070 brw_reg = brw_null_reg();
1071 break;
1072 }
1073 if (reg->abs)
1074 brw_reg = brw_abs(brw_reg);
1075 if (reg->negate)
1076 brw_reg = negate(brw_reg);
1077
1078 return brw_reg;
1079 }
1080
1081 /**
1082 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1083 * sampler LD messages.
1084 *
1085 * We don't want to bake it into the send message's code generation because
1086 * that means we don't get a chance to schedule the instructions.
1087 */
1088 void
1089 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1090 struct brw_reg dst,
1091 struct brw_reg value)
1092 {
1093 assert(value.file == BRW_IMMEDIATE_VALUE);
1094
1095 brw_push_insn_state(p);
1096 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1097 brw_set_mask_control(p, BRW_MASK_DISABLE);
1098 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1099 brw_pop_insn_state(p);
1100 }
1101
1102 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1103 * (when mask is passed as a uniform) of register mask before moving it
1104 * to register dst.
1105 */
1106 void
1107 fs_generator::generate_set_omask(fs_inst *inst,
1108 struct brw_reg dst,
1109 struct brw_reg mask)
1110 {
1111 bool stride_8_8_1 =
1112 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1113 mask.width == BRW_WIDTH_8 &&
1114 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1115
1116 bool stride_0_1_0 =
1117 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1118 mask.width == BRW_WIDTH_1 &&
1119 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1120
1121 assert(stride_8_8_1 || stride_0_1_0);
1122 assert(dst.type == BRW_REGISTER_TYPE_UW);
1123
1124 if (dispatch_width == 16)
1125 dst = vec16(dst);
1126 brw_push_insn_state(p);
1127 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1128 brw_set_mask_control(p, BRW_MASK_DISABLE);
1129
1130 if (stride_8_8_1) {
1131 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1132 } else if (stride_0_1_0) {
1133 brw_MOV(p, dst, retype(mask, dst.type));
1134 }
1135 brw_pop_insn_state(p);
1136 }
1137
1138 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1139 * the ADD instruction.
1140 */
1141 void
1142 fs_generator::generate_set_sample_id(fs_inst *inst,
1143 struct brw_reg dst,
1144 struct brw_reg src0,
1145 struct brw_reg src1)
1146 {
1147 assert(dst.type == BRW_REGISTER_TYPE_D ||
1148 dst.type == BRW_REGISTER_TYPE_UD);
1149 assert(src0.type == BRW_REGISTER_TYPE_D ||
1150 src0.type == BRW_REGISTER_TYPE_UD);
1151
1152 brw_push_insn_state(p);
1153 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1154 brw_set_mask_control(p, BRW_MASK_DISABLE);
1155 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1156 brw_ADD(p, dst, src0, reg);
1157 if (dispatch_width == 16)
1158 brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
1159 brw_pop_insn_state(p);
1160 }
1161
1162 /**
1163 * Change the register's data type from UD to W, doubling the strides in order
1164 * to compensate for halving the data type width.
1165 */
1166 static struct brw_reg
1167 ud_reg_to_w(struct brw_reg r)
1168 {
1169 assert(r.type == BRW_REGISTER_TYPE_UD);
1170 r.type = BRW_REGISTER_TYPE_W;
1171
1172 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1173 * doubles the real stride.
1174 */
1175 if (r.hstride != 0)
1176 ++r.hstride;
1177 if (r.vstride != 0)
1178 ++r.vstride;
1179
1180 return r;
1181 }
1182
1183 void
1184 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1185 struct brw_reg dst,
1186 struct brw_reg x,
1187 struct brw_reg y)
1188 {
1189 assert(brw->gen >= 7);
1190 assert(dst.type == BRW_REGISTER_TYPE_UD);
1191 assert(x.type == BRW_REGISTER_TYPE_F);
1192 assert(y.type == BRW_REGISTER_TYPE_F);
1193
1194 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1195 *
1196 * Because this instruction does not have a 16-bit floating-point type,
1197 * the destination data type must be Word (W).
1198 *
1199 * The destination must be DWord-aligned and specify a horizontal stride
1200 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1201 * each destination channel and the upper word is not modified.
1202 */
1203 struct brw_reg dst_w = ud_reg_to_w(dst);
1204
1205 /* Give each 32-bit channel of dst the form below , where "." means
1206 * unchanged.
1207 * 0x....hhhh
1208 */
1209 brw_F32TO16(p, dst_w, y);
1210
1211 /* Now the form:
1212 * 0xhhhh0000
1213 */
1214 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1215
1216 /* And, finally the form of packHalf2x16's output:
1217 * 0xhhhhllll
1218 */
1219 brw_F32TO16(p, dst_w, x);
1220 }
1221
1222 void
1223 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1224 struct brw_reg dst,
1225 struct brw_reg src)
1226 {
1227 assert(brw->gen >= 7);
1228 assert(dst.type == BRW_REGISTER_TYPE_F);
1229 assert(src.type == BRW_REGISTER_TYPE_UD);
1230
1231 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1232 *
1233 * Because this instruction does not have a 16-bit floating-point type,
1234 * the source data type must be Word (W). The destination type must be
1235 * F (Float).
1236 */
1237 struct brw_reg src_w = ud_reg_to_w(src);
1238
1239 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1240 * For the Y case, we wish to access only the upper word; therefore
1241 * a 16-bit subregister offset is needed.
1242 */
1243 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1244 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1245 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1246 src_w.subnr += 2;
1247
1248 brw_F16TO32(p, dst, src_w);
1249 }
1250
1251 void
1252 fs_generator::generate_shader_time_add(fs_inst *inst,
1253 struct brw_reg payload,
1254 struct brw_reg offset,
1255 struct brw_reg value)
1256 {
1257 assert(brw->gen >= 7);
1258 brw_push_insn_state(p);
1259 brw_set_mask_control(p, true);
1260
1261 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1262 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1263 offset.type);
1264 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1265 value.type);
1266
1267 assert(offset.file == BRW_IMMEDIATE_VALUE);
1268 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1269 value.width = BRW_WIDTH_1;
1270 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1271 value.vstride = BRW_VERTICAL_STRIDE_0;
1272 } else {
1273 assert(value.file == BRW_IMMEDIATE_VALUE);
1274 }
1275
1276 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1277 * case, and we don't really care about squeezing every bit of performance
1278 * out of this path, so we just emit the MOVs from here.
1279 */
1280 brw_MOV(p, payload_offset, offset);
1281 brw_MOV(p, payload_value, value);
1282 brw_shader_time_add(p, payload,
1283 prog_data->base.binding_table.shader_time_start);
1284 brw_pop_insn_state(p);
1285
1286 brw_mark_surface_used(&prog_data->base,
1287 prog_data->base.binding_table.shader_time_start);
1288 }
1289
1290 void
1291 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1292 struct brw_reg atomic_op,
1293 struct brw_reg surf_index)
1294 {
1295 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1296 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1297 surf_index.file == BRW_IMMEDIATE_VALUE &&
1298 surf_index.type == BRW_REGISTER_TYPE_UD);
1299
1300 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1301 atomic_op.dw1.ud, surf_index.dw1.ud,
1302 inst->mlen, dispatch_width / 8);
1303
1304 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1305 }
1306
1307 void
1308 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1309 struct brw_reg surf_index)
1310 {
1311 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1312 surf_index.type == BRW_REGISTER_TYPE_UD);
1313
1314 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1315 surf_index.dw1.ud,
1316 inst->mlen, dispatch_width / 8);
1317
1318 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1319 }
1320
1321 void
1322 fs_generator::generate_code(exec_list *instructions, FILE *dump_file)
1323 {
1324 int last_native_insn_offset = p->next_insn_offset;
1325 const char *last_annotation_string = NULL;
1326 const void *last_annotation_ir = NULL;
1327
1328 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1329 if (prog) {
1330 fprintf(stderr,
1331 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
1332 prog->Label ? prog->Label : "unnamed",
1333 prog->Name, dispatch_width);
1334 } else if (fp) {
1335 fprintf(stderr,
1336 "Native code for fragment program %d (SIMD%d dispatch):\n",
1337 fp->Base.Id, dispatch_width);
1338 } else {
1339 fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
1340 dispatch_width);
1341 }
1342 }
1343
1344 cfg_t *cfg = NULL;
1345 if (unlikely(INTEL_DEBUG & DEBUG_WM))
1346 cfg = new(mem_ctx) cfg_t(instructions);
1347
1348 foreach_list(node, instructions) {
1349 fs_inst *inst = (fs_inst *)node;
1350 struct brw_reg src[3], dst;
1351
1352 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1353 foreach_list(node, &cfg->block_list) {
1354 bblock_link *link = (bblock_link *)node;
1355 bblock_t *block = link->block;
1356
1357 if (block->start == inst) {
1358 fprintf(stderr, " START B%d", block->block_num);
1359 foreach_list(predecessor_node, &block->parents) {
1360 bblock_link *predecessor_link =
1361 (bblock_link *)predecessor_node;
1362 bblock_t *predecessor_block = predecessor_link->block;
1363 fprintf(stderr, " <-B%d", predecessor_block->block_num);
1364 }
1365 fprintf(stderr, "\n");
1366 }
1367 }
1368
1369 if (last_annotation_ir != inst->ir) {
1370 last_annotation_ir = inst->ir;
1371 if (last_annotation_ir) {
1372 fprintf(stderr, " ");
1373 if (prog)
1374 ((ir_instruction *)inst->ir)->fprint(stderr);
1375 else {
1376 const prog_instruction *fpi;
1377 fpi = (const prog_instruction *)inst->ir;
1378 fprintf(stderr, "%d: ",
1379 (int)(fpi - (fp ? fp->Base.Instructions : 0)));
1380 _mesa_fprint_instruction_opt(stderr,
1381 fpi,
1382 0, PROG_PRINT_DEBUG, NULL);
1383 }
1384 fprintf(stderr, "\n");
1385 }
1386 }
1387 if (last_annotation_string != inst->annotation) {
1388 last_annotation_string = inst->annotation;
1389 if (last_annotation_string)
1390 fprintf(stderr, " %s\n", last_annotation_string);
1391 }
1392 }
1393
1394 for (unsigned int i = 0; i < 3; i++) {
1395 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1396
1397 /* The accumulator result appears to get used for the
1398 * conditional modifier generation. When negating a UD
1399 * value, there is a 33rd bit generated for the sign in the
1400 * accumulator value, so now you can't check, for example,
1401 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1402 */
1403 assert(!inst->conditional_mod ||
1404 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1405 !inst->src[i].negate);
1406 }
1407 dst = brw_reg_from_fs_reg(&inst->dst);
1408
1409 brw_set_conditionalmod(p, inst->conditional_mod);
1410 brw_set_predicate_control(p, inst->predicate);
1411 brw_set_predicate_inverse(p, inst->predicate_inverse);
1412 brw_set_flag_reg(p, 0, inst->flag_subreg);
1413 brw_set_saturate(p, inst->saturate);
1414 brw_set_mask_control(p, inst->force_writemask_all);
1415 brw_set_acc_write_control(p, inst->writes_accumulator);
1416
1417 if (inst->force_uncompressed || dispatch_width == 8) {
1418 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1419 } else if (inst->force_sechalf) {
1420 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1421 } else {
1422 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1423 }
1424
1425 switch (inst->opcode) {
1426 case BRW_OPCODE_MOV:
1427 brw_MOV(p, dst, src[0]);
1428 break;
1429 case BRW_OPCODE_ADD:
1430 brw_ADD(p, dst, src[0], src[1]);
1431 break;
1432 case BRW_OPCODE_MUL:
1433 brw_MUL(p, dst, src[0], src[1]);
1434 break;
1435 case BRW_OPCODE_AVG:
1436 brw_AVG(p, dst, src[0], src[1]);
1437 break;
1438 case BRW_OPCODE_MACH:
1439 brw_MACH(p, dst, src[0], src[1]);
1440 break;
1441
1442 case BRW_OPCODE_MAD:
1443 assert(brw->gen >= 6);
1444 brw_set_access_mode(p, BRW_ALIGN_16);
1445 if (dispatch_width == 16 && !brw->is_haswell) {
1446 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1447 brw_MAD(p, dst, src[0], src[1], src[2]);
1448 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1449 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1450 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1451 } else {
1452 brw_MAD(p, dst, src[0], src[1], src[2]);
1453 }
1454 brw_set_access_mode(p, BRW_ALIGN_1);
1455 break;
1456
1457 case BRW_OPCODE_LRP:
1458 assert(brw->gen >= 6);
1459 brw_set_access_mode(p, BRW_ALIGN_16);
1460 if (dispatch_width == 16 && !brw->is_haswell) {
1461 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1462 brw_LRP(p, dst, src[0], src[1], src[2]);
1463 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1464 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1465 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1466 } else {
1467 brw_LRP(p, dst, src[0], src[1], src[2]);
1468 }
1469 brw_set_access_mode(p, BRW_ALIGN_1);
1470 break;
1471
1472 case BRW_OPCODE_FRC:
1473 brw_FRC(p, dst, src[0]);
1474 break;
1475 case BRW_OPCODE_RNDD:
1476 brw_RNDD(p, dst, src[0]);
1477 break;
1478 case BRW_OPCODE_RNDE:
1479 brw_RNDE(p, dst, src[0]);
1480 break;
1481 case BRW_OPCODE_RNDZ:
1482 brw_RNDZ(p, dst, src[0]);
1483 break;
1484
1485 case BRW_OPCODE_AND:
1486 brw_AND(p, dst, src[0], src[1]);
1487 break;
1488 case BRW_OPCODE_OR:
1489 brw_OR(p, dst, src[0], src[1]);
1490 break;
1491 case BRW_OPCODE_XOR:
1492 brw_XOR(p, dst, src[0], src[1]);
1493 break;
1494 case BRW_OPCODE_NOT:
1495 brw_NOT(p, dst, src[0]);
1496 break;
1497 case BRW_OPCODE_ASR:
1498 brw_ASR(p, dst, src[0], src[1]);
1499 break;
1500 case BRW_OPCODE_SHR:
1501 brw_SHR(p, dst, src[0], src[1]);
1502 break;
1503 case BRW_OPCODE_SHL:
1504 brw_SHL(p, dst, src[0], src[1]);
1505 break;
1506 case BRW_OPCODE_F32TO16:
1507 assert(brw->gen >= 7);
1508 brw_F32TO16(p, dst, src[0]);
1509 break;
1510 case BRW_OPCODE_F16TO32:
1511 assert(brw->gen >= 7);
1512 brw_F16TO32(p, dst, src[0]);
1513 break;
1514 case BRW_OPCODE_CMP:
1515 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1516 break;
1517 case BRW_OPCODE_SEL:
1518 brw_SEL(p, dst, src[0], src[1]);
1519 break;
1520 case BRW_OPCODE_BFREV:
1521 assert(brw->gen >= 7);
1522 /* BFREV only supports UD type for src and dst. */
1523 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1524 retype(src[0], BRW_REGISTER_TYPE_UD));
1525 break;
1526 case BRW_OPCODE_FBH:
1527 assert(brw->gen >= 7);
1528 /* FBH only supports UD type for dst. */
1529 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1530 break;
1531 case BRW_OPCODE_FBL:
1532 assert(brw->gen >= 7);
1533 /* FBL only supports UD type for dst. */
1534 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1535 break;
1536 case BRW_OPCODE_CBIT:
1537 assert(brw->gen >= 7);
1538 /* CBIT only supports UD type for dst. */
1539 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1540 break;
1541 case BRW_OPCODE_ADDC:
1542 assert(brw->gen >= 7);
1543 brw_ADDC(p, dst, src[0], src[1]);
1544 break;
1545 case BRW_OPCODE_SUBB:
1546 assert(brw->gen >= 7);
1547 brw_SUBB(p, dst, src[0], src[1]);
1548 break;
1549 case BRW_OPCODE_MAC:
1550 brw_MAC(p, dst, src[0], src[1]);
1551 break;
1552
1553 case BRW_OPCODE_BFE:
1554 assert(brw->gen >= 7);
1555 brw_set_access_mode(p, BRW_ALIGN_16);
1556 if (dispatch_width == 16 && !brw->is_haswell) {
1557 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1558 brw_BFE(p, dst, src[0], src[1], src[2]);
1559 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1560 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1561 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1562 } else {
1563 brw_BFE(p, dst, src[0], src[1], src[2]);
1564 }
1565 brw_set_access_mode(p, BRW_ALIGN_1);
1566 break;
1567
1568 case BRW_OPCODE_BFI1:
1569 assert(brw->gen >= 7);
1570 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1571 * should
1572 *
1573 * "Force BFI instructions to be executed always in SIMD8."
1574 */
1575 if (dispatch_width == 16 && brw->is_haswell) {
1576 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1577 brw_BFI1(p, dst, src[0], src[1]);
1578 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1579 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1580 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1581 } else {
1582 brw_BFI1(p, dst, src[0], src[1]);
1583 }
1584 break;
1585 case BRW_OPCODE_BFI2:
1586 assert(brw->gen >= 7);
1587 brw_set_access_mode(p, BRW_ALIGN_16);
1588 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1589 * should
1590 *
1591 * "Force BFI instructions to be executed always in SIMD8."
1592 *
1593 * Otherwise we would be able to emit compressed instructions like we
1594 * do for the other three-source instructions.
1595 */
1596 if (dispatch_width == 16) {
1597 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1598 brw_BFI2(p, dst, src[0], src[1], src[2]);
1599 brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
1600 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1601 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1602 } else {
1603 brw_BFI2(p, dst, src[0], src[1], src[2]);
1604 }
1605 brw_set_access_mode(p, BRW_ALIGN_1);
1606 break;
1607
1608 case BRW_OPCODE_IF:
1609 if (inst->src[0].file != BAD_FILE) {
1610 /* The instruction has an embedded compare (only allowed on gen6) */
1611 assert(brw->gen == 6);
1612 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1613 } else {
1614 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1615 }
1616 break;
1617
1618 case BRW_OPCODE_ELSE:
1619 brw_ELSE(p);
1620 break;
1621 case BRW_OPCODE_ENDIF:
1622 brw_ENDIF(p);
1623 break;
1624
1625 case BRW_OPCODE_DO:
1626 brw_DO(p, BRW_EXECUTE_8);
1627 break;
1628
1629 case BRW_OPCODE_BREAK:
1630 brw_BREAK(p);
1631 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1632 break;
1633 case BRW_OPCODE_CONTINUE:
1634 /* FINISHME: We need to write the loop instruction support still. */
1635 if (brw->gen >= 6)
1636 gen6_CONT(p);
1637 else
1638 brw_CONT(p);
1639 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1640 break;
1641
1642 case BRW_OPCODE_WHILE:
1643 brw_WHILE(p);
1644 break;
1645
1646 case SHADER_OPCODE_RCP:
1647 case SHADER_OPCODE_RSQ:
1648 case SHADER_OPCODE_SQRT:
1649 case SHADER_OPCODE_EXP2:
1650 case SHADER_OPCODE_LOG2:
1651 case SHADER_OPCODE_SIN:
1652 case SHADER_OPCODE_COS:
1653 if (brw->gen >= 7) {
1654 generate_math1_gen7(inst, dst, src[0]);
1655 } else if (brw->gen == 6) {
1656 generate_math1_gen6(inst, dst, src[0]);
1657 } else if (brw->gen == 5 || brw->is_g4x) {
1658 generate_math_g45(inst, dst, src[0]);
1659 } else {
1660 generate_math_gen4(inst, dst, src[0]);
1661 }
1662 break;
1663 case SHADER_OPCODE_INT_QUOTIENT:
1664 case SHADER_OPCODE_INT_REMAINDER:
1665 case SHADER_OPCODE_POW:
1666 if (brw->gen >= 7) {
1667 generate_math2_gen7(inst, dst, src[0], src[1]);
1668 } else if (brw->gen == 6) {
1669 generate_math2_gen6(inst, dst, src[0], src[1]);
1670 } else {
1671 generate_math_gen4(inst, dst, src[0]);
1672 }
1673 break;
1674 case FS_OPCODE_PIXEL_X:
1675 generate_pixel_xy(dst, true);
1676 break;
1677 case FS_OPCODE_PIXEL_Y:
1678 generate_pixel_xy(dst, false);
1679 break;
1680 case FS_OPCODE_CINTERP:
1681 brw_MOV(p, dst, src[0]);
1682 break;
1683 case FS_OPCODE_LINTERP:
1684 generate_linterp(inst, dst, src);
1685 break;
1686 case SHADER_OPCODE_TEX:
1687 case FS_OPCODE_TXB:
1688 case SHADER_OPCODE_TXD:
1689 case SHADER_OPCODE_TXF:
1690 case SHADER_OPCODE_TXF_CMS:
1691 case SHADER_OPCODE_TXF_UMS:
1692 case SHADER_OPCODE_TXF_MCS:
1693 case SHADER_OPCODE_TXL:
1694 case SHADER_OPCODE_TXS:
1695 case SHADER_OPCODE_LOD:
1696 case SHADER_OPCODE_TG4:
1697 case SHADER_OPCODE_TG4_OFFSET:
1698 generate_tex(inst, dst, src[0]);
1699 break;
1700 case FS_OPCODE_DDX:
1701 generate_ddx(inst, dst, src[0]);
1702 break;
1703 case FS_OPCODE_DDY:
1704 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1705 * guarantee that key->render_to_fbo is set).
1706 */
1707 assert(fp->UsesDFdy);
1708 generate_ddy(inst, dst, src[0], key->render_to_fbo);
1709 break;
1710
1711 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1712 generate_scratch_write(inst, src[0]);
1713 break;
1714
1715 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1716 generate_scratch_read(inst, dst);
1717 break;
1718
1719 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1720 generate_scratch_read_gen7(inst, dst);
1721 break;
1722
1723 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1724 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1725 break;
1726
1727 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1728 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1729 break;
1730
1731 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1732 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1733 break;
1734
1735 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1736 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1737 break;
1738
1739 case FS_OPCODE_FB_WRITE:
1740 generate_fb_write(inst);
1741 break;
1742
1743 case FS_OPCODE_BLORP_FB_WRITE:
1744 generate_blorp_fb_write(inst);
1745 break;
1746
1747 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1748 generate_mov_dispatch_to_flags(inst);
1749 break;
1750
1751 case FS_OPCODE_DISCARD_JUMP:
1752 generate_discard_jump(inst);
1753 break;
1754
1755 case SHADER_OPCODE_SHADER_TIME_ADD:
1756 generate_shader_time_add(inst, src[0], src[1], src[2]);
1757 break;
1758
1759 case SHADER_OPCODE_UNTYPED_ATOMIC:
1760 generate_untyped_atomic(inst, dst, src[0], src[1]);
1761 break;
1762
1763 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1764 generate_untyped_surface_read(inst, dst, src[0]);
1765 break;
1766
1767 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1768 generate_set_simd4x2_offset(inst, dst, src[0]);
1769 break;
1770
1771 case FS_OPCODE_SET_OMASK:
1772 generate_set_omask(inst, dst, src[0]);
1773 break;
1774
1775 case FS_OPCODE_SET_SAMPLE_ID:
1776 generate_set_sample_id(inst, dst, src[0], src[1]);
1777 break;
1778
1779 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1780 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1781 break;
1782
1783 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1784 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1785 generate_unpack_half_2x16_split(inst, dst, src[0]);
1786 break;
1787
1788 case FS_OPCODE_PLACEHOLDER_HALT:
1789 /* This is the place where the final HALT needs to be inserted if
1790 * we've emitted any discards. If not, this will emit no code.
1791 */
1792 patch_discard_jumps_to_fb_writes();
1793 break;
1794
1795 default:
1796 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1797 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1798 opcode_descs[inst->opcode].name);
1799 } else {
1800 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1801 }
1802 abort();
1803 }
1804
1805 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1806 brw_disassemble(brw, p->store, last_native_insn_offset, p->next_insn_offset, stderr);
1807
1808 foreach_list(node, &cfg->block_list) {
1809 bblock_link *link = (bblock_link *)node;
1810 bblock_t *block = link->block;
1811
1812 if (block->end == inst) {
1813 fprintf(stderr, " END B%d", block->block_num);
1814 foreach_list(successor_node, &block->children) {
1815 bblock_link *successor_link =
1816 (bblock_link *)successor_node;
1817 bblock_t *successor_block = successor_link->block;
1818 fprintf(stderr, " ->B%d", successor_block->block_num);
1819 }
1820 fprintf(stderr, "\n");
1821 }
1822 }
1823 }
1824
1825 last_native_insn_offset = p->next_insn_offset;
1826 }
1827
1828 if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
1829 fprintf(stderr, "\n");
1830 }
1831
1832 brw_set_uip_jip(p);
1833
1834 /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
1835 * emit issues, it doesn't get the jump distances into the output,
1836 * which is often something we want to debug. So this is here in
1837 * case you're doing that.
1838 */
1839 if (dump_file) {
1840 brw_disassemble(brw, p->store, 0, p->next_insn_offset, dump_file);
1841 }
1842 }
1843
1844 const unsigned *
1845 fs_generator::generate_assembly(exec_list *simd8_instructions,
1846 exec_list *simd16_instructions,
1847 unsigned *assembly_size,
1848 FILE *dump_file)
1849 {
1850 assert(simd8_instructions || simd16_instructions);
1851
1852 if (simd8_instructions) {
1853 dispatch_width = 8;
1854 generate_code(simd8_instructions, dump_file);
1855 brw_compact_instructions(p);
1856 }
1857
1858 if (simd16_instructions) {
1859 /* align to 64 byte boundary. */
1860 while ((p->nr_insn * sizeof(struct brw_instruction)) % 64) {
1861 brw_NOP(p);
1862 }
1863
1864 /* Save off the start of this SIMD16 program */
1865 prog_data->prog_offset_16 = p->nr_insn * sizeof(struct brw_instruction);
1866
1867 brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1868
1869 dispatch_width = 16;
1870 generate_code(simd16_instructions, dump_file);
1871 brw_compact_instructions(p);
1872 }
1873
1874 return brw_get_program(p, assembly_size);
1875 }