2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
30 #include "main/macros.h"
31 #include "brw_context.h"
36 static uint32_t brw_file_from_reg(fs_reg
*reg
)
40 return BRW_GENERAL_REGISTER_FILE
;
42 return BRW_MESSAGE_REGISTER_FILE
;
44 return BRW_IMMEDIATE_VALUE
;
46 unreachable("not reached");
51 brw_reg_from_fs_reg(fs_inst
*inst
, fs_reg
*reg
)
53 struct brw_reg brw_reg
;
58 if (reg
->stride
== 0) {
59 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
60 } else if (inst
->exec_size
< 8) {
61 brw_reg
= brw_vec8_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
62 brw_reg
= stride(brw_reg
, inst
->exec_size
* reg
->stride
,
63 inst
->exec_size
, reg
->stride
);
65 /* From the Haswell PRM:
67 * VertStride must be used to cross GRF register boundaries. This
68 * rule implies that elements within a 'Width' cannot cross GRF
71 * So, for registers with width > 8, we have to use a width of 8
72 * and trust the compression state to sort out the exec size.
74 brw_reg
= brw_vec8_reg(brw_file_from_reg(reg
), reg
->reg
, 0);
75 brw_reg
= stride(brw_reg
, 8 * reg
->stride
, 8, reg
->stride
);
78 brw_reg
= retype(brw_reg
, reg
->type
);
79 brw_reg
= byte_offset(brw_reg
, reg
->subreg_offset
);
82 assert(reg
->stride
== ((reg
->type
== BRW_REGISTER_TYPE_V
||
83 reg
->type
== BRW_REGISTER_TYPE_UV
||
84 reg
->type
== BRW_REGISTER_TYPE_VF
) ? 1 : 0));
87 case BRW_REGISTER_TYPE_F
:
88 brw_reg
= brw_imm_f(reg
->fixed_hw_reg
.dw1
.f
);
90 case BRW_REGISTER_TYPE_D
:
91 brw_reg
= brw_imm_d(reg
->fixed_hw_reg
.dw1
.d
);
93 case BRW_REGISTER_TYPE_UD
:
94 brw_reg
= brw_imm_ud(reg
->fixed_hw_reg
.dw1
.ud
);
96 case BRW_REGISTER_TYPE_W
:
97 brw_reg
= brw_imm_w(reg
->fixed_hw_reg
.dw1
.d
);
99 case BRW_REGISTER_TYPE_UW
:
100 brw_reg
= brw_imm_uw(reg
->fixed_hw_reg
.dw1
.ud
);
102 case BRW_REGISTER_TYPE_VF
:
103 brw_reg
= brw_imm_vf(reg
->fixed_hw_reg
.dw1
.ud
);
106 unreachable("not reached");
110 assert(reg
->type
== reg
->fixed_hw_reg
.type
);
111 brw_reg
= reg
->fixed_hw_reg
;
114 /* Probably unused. */
115 brw_reg
= brw_null_reg();
118 unreachable("not reached");
121 brw_reg
= brw_abs(brw_reg
);
123 brw_reg
= negate(brw_reg
);
128 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
131 struct brw_stage_prog_data
*prog_data
,
132 struct gl_program
*prog
,
133 unsigned promoted_constants
,
134 bool runtime_check_aads_emit
,
135 const char *stage_abbrev
)
137 : compiler(compiler
), log_data(log_data
),
138 devinfo(compiler
->devinfo
), key(key
),
139 prog_data(prog_data
),
140 prog(prog
), promoted_constants(promoted_constants
),
141 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
142 stage_abbrev(stage_abbrev
), mem_ctx(mem_ctx
)
144 p
= rzalloc(mem_ctx
, struct brw_codegen
);
145 brw_init_codegen(devinfo
, p
, mem_ctx
);
148 fs_generator::~fs_generator()
152 class ip_record
: public exec_node
{
154 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
165 fs_generator::patch_discard_jumps_to_fb_writes()
167 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
170 int scale
= brw_jump_scale(p
->devinfo
);
172 /* There is a somewhat strange undocumented requirement of using
173 * HALT, according to the simulator. If some channel has HALTed to
174 * a particular UIP, then by the end of the program, every channel
175 * must have HALTed to that UIP. Furthermore, the tracking is a
176 * stack, so you can't do the final halt of a UIP after starting
177 * halting to a new UIP.
179 * Symptoms of not emitting this instruction on actual hardware
180 * included GPU hangs and sparkly rendering on the piglit discard
183 brw_inst
*last_halt
= gen6_HALT(p
);
184 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
185 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
189 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
190 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
192 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
193 /* HALT takes a half-instruction distance from the pre-incremented IP. */
194 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
197 this->discard_halt_patches
.make_empty();
202 fs_generator::fire_fb_write(fs_inst
*inst
,
203 struct brw_reg payload
,
204 struct brw_reg implied_header
,
207 uint32_t msg_control
;
209 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
211 if (devinfo
->gen
< 6) {
212 brw_push_insn_state(p
);
213 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
214 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
215 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
216 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
217 brw_MOV(p
, offset(payload
, 1), brw_vec8_grf(1, 0));
218 brw_pop_insn_state(p
);
221 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
)
222 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
223 else if (prog_data
->dual_src_blend
) {
224 if (!inst
->force_sechalf
)
225 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
227 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
228 } else if (inst
->exec_size
== 16)
229 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
231 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
233 uint32_t surf_index
=
234 prog_data
->binding_table
.render_target_start
+ inst
->target
;
236 bool last_render_target
= inst
->eot
||
237 (prog_data
->dual_src_blend
&& dispatch_width
== 16);
250 inst
->header_size
!= 0);
252 brw_mark_surface_used(&prog_data
->base
, surf_index
);
256 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
258 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
259 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
260 struct brw_reg implied_header
;
262 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
263 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
266 if (inst
->base_mrf
>= 0)
267 payload
= brw_message_reg(inst
->base_mrf
);
269 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
272 if (inst
->header_size
!= 0) {
273 brw_push_insn_state(p
);
274 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
275 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
276 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
277 brw_set_default_flag_reg(p
, 0, 0);
279 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
282 if (prog_data
->uses_kill
) {
283 struct brw_reg pixel_mask
;
285 if (devinfo
->gen
>= 6)
286 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
288 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
290 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
293 if (devinfo
->gen
>= 6) {
294 brw_push_insn_state(p
);
295 brw_set_default_exec_size(p
, BRW_EXECUTE_16
);
296 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
298 retype(payload
, BRW_REGISTER_TYPE_UD
),
299 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
300 brw_pop_insn_state(p
);
302 if (inst
->target
> 0 && key
->replicate_alpha
) {
303 /* Set "Source0 Alpha Present to RenderTarget" bit in message
307 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
308 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
309 brw_imm_ud(0x1 << 11));
312 if (inst
->target
> 0) {
313 /* Set the render target index for choosing BLEND_STATE. */
314 brw_MOV(p
, retype(vec1(suboffset(payload
, 2)),
315 BRW_REGISTER_TYPE_UD
),
316 brw_imm_ud(inst
->target
));
319 implied_header
= brw_null_reg();
321 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
324 brw_pop_insn_state(p
);
326 implied_header
= brw_null_reg();
329 if (!runtime_check_aads_emit
) {
330 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
332 /* This can only happen in gen < 6 */
333 assert(devinfo
->gen
< 6);
335 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
337 /* Check runtime bit to detect if we have to send AA data or not */
338 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
341 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
343 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
345 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
346 brw_inst_set_exec_size(p
->devinfo
, brw_last_inst
, BRW_EXECUTE_1
);
348 /* Don't send AA data */
349 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
351 brw_land_fwd_jump(p
, jmp
);
352 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
357 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
361 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
363 brw_set_dest(p
, insn
, brw_null_reg());
364 brw_set_src0(p
, insn
, payload
);
365 brw_set_src1(p
, insn
, brw_imm_d(0));
367 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
368 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
370 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
371 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
372 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
373 brw_inst_set_header_present(p
->devinfo
, insn
, true);
374 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
378 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
380 struct brw_inst
*insn
;
382 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
384 brw_set_dest(p
, insn
, brw_null_reg());
385 brw_set_src0(p
, insn
, payload
);
386 brw_set_src1(p
, insn
, brw_imm_d(0));
388 /* Terminate a compute shader by sending a message to the thread spawner.
390 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
391 brw_inst_set_mlen(devinfo
, insn
, 1);
392 brw_inst_set_rlen(devinfo
, insn
, 0);
393 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
394 brw_inst_set_header_present(devinfo
, insn
, false);
396 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
397 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
399 /* Note that even though the thread has a URB resource associated with it,
400 * we set the "do not dereference URB" bit, because the URB resource is
401 * managed by the fixed-function unit, so it will free it automatically.
403 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
405 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
409 fs_generator::generate_barrier(fs_inst
*inst
, struct brw_reg src
)
416 fs_generator::generate_blorp_fb_write(fs_inst
*inst
)
419 16 /* dispatch_width */,
420 brw_message_reg(inst
->base_mrf
),
421 brw_reg_from_fs_reg(inst
, &inst
->src
[0]),
422 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
,
428 inst
->header_size
!= 0);
432 fs_generator::generate_linterp(fs_inst
*inst
,
433 struct brw_reg dst
, struct brw_reg
*src
)
437 * -----------------------------------
438 * | src1+0 | src1+1 | src1+2 | src1+3 |
439 * |-----------------------------------|
440 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
441 * -----------------------------------
443 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
445 * -----------------------------------
446 * | src1+0 | src1+1 | src1+2 | src1+3 |
447 * |-----------------------------------|
448 * |(x0, x1)|(y0, y1)| | | in SIMD8
449 * |-----------------------------------|
450 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
451 * -----------------------------------
453 * See also: emit_interpolation_setup_gen4().
455 struct brw_reg delta_x
= src
[0];
456 struct brw_reg delta_y
= offset(src
[0], dispatch_width
/ 8);
457 struct brw_reg interp
= src
[1];
459 if (devinfo
->has_pln
&&
460 (devinfo
->gen
>= 7 || (delta_x
.nr
& 1) == 0)) {
461 brw_PLN(p
, dst
, interp
, delta_x
);
463 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
464 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
469 fs_generator::generate_math_gen6(fs_inst
*inst
,
474 int op
= brw_math_function(inst
->opcode
);
475 bool binop
= src1
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
;
477 if (dispatch_width
== 8) {
478 gen6_math(p
, dst
, op
, src0
, src1
);
479 } else if (dispatch_width
== 16) {
480 brw_push_insn_state(p
);
481 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
482 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
483 gen6_math(p
, firsthalf(dst
), op
, firsthalf(src0
), firsthalf(src1
));
484 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
485 gen6_math(p
, sechalf(dst
), op
, sechalf(src0
),
486 binop
? sechalf(src1
) : brw_null_reg());
487 brw_pop_insn_state(p
);
492 fs_generator::generate_math_gen4(fs_inst
*inst
,
496 int op
= brw_math_function(inst
->opcode
);
498 assert(inst
->mlen
>= 1);
500 if (dispatch_width
== 8) {
504 BRW_MATH_PRECISION_FULL
);
505 } else if (dispatch_width
== 16) {
506 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
507 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
508 gen4_math(p
, firsthalf(dst
),
510 inst
->base_mrf
, firsthalf(src
),
511 BRW_MATH_PRECISION_FULL
);
512 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
513 gen4_math(p
, sechalf(dst
),
515 inst
->base_mrf
+ 1, sechalf(src
),
516 BRW_MATH_PRECISION_FULL
);
518 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
523 fs_generator::generate_math_g45(fs_inst
*inst
,
527 if (inst
->opcode
== SHADER_OPCODE_POW
||
528 inst
->opcode
== SHADER_OPCODE_INT_QUOTIENT
||
529 inst
->opcode
== SHADER_OPCODE_INT_REMAINDER
) {
530 generate_math_gen4(inst
, dst
, src
);
534 int op
= brw_math_function(inst
->opcode
);
536 assert(inst
->mlen
>= 1);
541 BRW_MATH_PRECISION_FULL
);
545 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
546 struct brw_reg sampler_index
)
551 uint32_t return_format
;
552 bool is_combined_send
= inst
->eot
;
555 case BRW_REGISTER_TYPE_D
:
556 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
558 case BRW_REGISTER_TYPE_UD
:
559 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
562 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
566 switch (inst
->exec_size
) {
568 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
571 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
574 unreachable("Invalid width for texture instruction");
577 if (devinfo
->gen
>= 5) {
578 switch (inst
->opcode
) {
579 case SHADER_OPCODE_TEX
:
580 if (inst
->shadow_compare
) {
581 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
583 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
587 if (inst
->shadow_compare
) {
588 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
590 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
593 case SHADER_OPCODE_TXL
:
594 if (inst
->shadow_compare
) {
595 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
597 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
600 case SHADER_OPCODE_TXS
:
601 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
603 case SHADER_OPCODE_TXD
:
604 if (inst
->shadow_compare
) {
605 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
606 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
607 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
609 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
612 case SHADER_OPCODE_TXF
:
613 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
615 case SHADER_OPCODE_TXF_CMS
:
616 if (devinfo
->gen
>= 7)
617 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
619 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
621 case SHADER_OPCODE_TXF_UMS
:
622 assert(devinfo
->gen
>= 7);
623 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
625 case SHADER_OPCODE_TXF_MCS
:
626 assert(devinfo
->gen
>= 7);
627 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
629 case SHADER_OPCODE_LOD
:
630 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
632 case SHADER_OPCODE_TG4
:
633 if (inst
->shadow_compare
) {
634 assert(devinfo
->gen
>= 7);
635 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
637 assert(devinfo
->gen
>= 6);
638 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
641 case SHADER_OPCODE_TG4_OFFSET
:
642 assert(devinfo
->gen
>= 7);
643 if (inst
->shadow_compare
) {
644 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
646 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
650 unreachable("not reached");
653 switch (inst
->opcode
) {
654 case SHADER_OPCODE_TEX
:
655 /* Note that G45 and older determines shadow compare and dispatch width
656 * from message length for most messages.
658 if (inst
->exec_size
== 8) {
659 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
660 if (inst
->shadow_compare
) {
661 assert(inst
->mlen
== 6);
663 assert(inst
->mlen
<= 4);
666 if (inst
->shadow_compare
) {
667 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
668 assert(inst
->mlen
== 9);
670 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
671 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
676 if (inst
->shadow_compare
) {
677 assert(inst
->exec_size
== 8);
678 assert(inst
->mlen
== 6);
679 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
681 assert(inst
->mlen
== 9);
682 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
683 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
686 case SHADER_OPCODE_TXL
:
687 if (inst
->shadow_compare
) {
688 assert(inst
->exec_size
== 8);
689 assert(inst
->mlen
== 6);
690 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
692 assert(inst
->mlen
== 9);
693 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
694 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
697 case SHADER_OPCODE_TXD
:
698 /* There is no sample_d_c message; comparisons are done manually */
699 assert(inst
->exec_size
== 8);
700 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
701 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
703 case SHADER_OPCODE_TXF
:
704 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
705 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
706 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
708 case SHADER_OPCODE_TXS
:
709 assert(inst
->mlen
== 3);
710 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
711 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
714 unreachable("not reached");
717 assert(msg_type
!= -1);
719 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
724 if (is_combined_send
) {
725 assert(devinfo
->gen
>= 9 || devinfo
->is_cherryview
);
729 assert(devinfo
->gen
< 7 || inst
->header_size
== 0 ||
730 src
.file
== BRW_GENERAL_REGISTER_FILE
);
732 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
734 /* Load the message header if present. If there's a texture offset,
735 * we need to set it up explicitly and load the offset bitfield.
736 * Otherwise, we can use an implied move from g0 to the first message reg.
738 if (inst
->header_size
!= 0) {
739 if (devinfo
->gen
< 6 && !inst
->offset
) {
740 /* Set up an implied move from g0 to the MRF. */
741 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
743 struct brw_reg header_reg
;
745 if (devinfo
->gen
>= 7) {
748 assert(inst
->base_mrf
!= -1);
749 header_reg
= brw_message_reg(inst
->base_mrf
);
752 brw_push_insn_state(p
);
753 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
754 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
755 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
756 /* Explicitly set up the message header by copying g0 to the MRF. */
757 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
760 /* Set the offset bits in DWord 2. */
761 brw_MOV(p
, get_element_ud(header_reg
, 2),
762 brw_imm_ud(inst
->offset
));
765 brw_adjust_sampler_state_pointer(p
, header_reg
, sampler_index
);
766 brw_pop_insn_state(p
);
770 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
771 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
772 ? prog_data
->binding_table
.gather_texture_start
773 : prog_data
->binding_table
.texture_start
;
775 if (sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
776 uint32_t sampler
= sampler_index
.dw1
.ud
;
779 retype(dst
, BRW_REGISTER_TYPE_UW
),
782 sampler
+ base_binding_table_index
,
787 inst
->header_size
!= 0,
791 brw_mark_surface_used(prog_data
, sampler
+ base_binding_table_index
);
793 /* Non-const sampler index */
795 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
796 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
798 brw_push_insn_state(p
);
799 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
800 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
802 /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
803 brw_MUL(p
, addr
, sampler_reg
, brw_imm_uw(0x101));
804 if (base_binding_table_index
)
805 brw_ADD(p
, addr
, addr
, brw_imm_ud(base_binding_table_index
));
806 brw_AND(p
, addr
, addr
, brw_imm_ud(0xfff));
808 brw_pop_insn_state(p
);
810 /* dst = send(offset, a0.0 | <descriptor>) */
811 brw_inst
*insn
= brw_send_indirect_message(
812 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
813 brw_set_sampler_message(p
, insn
,
818 inst
->mlen
/* mlen */,
819 inst
->header_size
!= 0 /* header */,
823 /* visitor knows more than we do about the surface limit required,
824 * so has already done marking.
828 if (is_combined_send
) {
829 brw_inst_set_eot(p
->devinfo
, brw_last_inst
, true);
830 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
835 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
838 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
840 * Ideally, we want to produce:
843 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
844 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
845 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
846 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
847 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
848 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
849 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
850 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
852 * and add another set of two more subspans if in 16-pixel dispatch mode.
854 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
855 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
856 * pair. But the ideal approximation may impose a huge performance cost on
857 * sample_d. On at least Haswell, sample_d instruction does some
858 * optimizations if the same LOD is used for all pixels in the subspan.
860 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
861 * appropriate swizzling.
864 fs_generator::generate_ddx(enum opcode opcode
,
865 struct brw_reg dst
, struct brw_reg src
)
867 unsigned vstride
, width
;
869 if (opcode
== FS_OPCODE_DDX_FINE
) {
870 /* produce accurate derivatives */
871 vstride
= BRW_VERTICAL_STRIDE_2
;
874 /* replicate the derivative at the top-left pixel to other pixels */
875 vstride
= BRW_VERTICAL_STRIDE_4
;
879 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
884 BRW_HORIZONTAL_STRIDE_0
,
885 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
886 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
891 BRW_HORIZONTAL_STRIDE_0
,
892 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
893 brw_ADD(p
, dst
, src0
, negate(src1
));
896 /* The negate_value boolean is used to negate the derivative computation for
897 * FBOs, since they place the origin at the upper left instead of the lower
901 fs_generator::generate_ddy(enum opcode opcode
,
902 struct brw_reg dst
, struct brw_reg src
,
905 if (opcode
== FS_OPCODE_DDY_FINE
) {
906 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
907 * Region Restrictions):
909 * In Align16 access mode, SIMD16 is not allowed for DW operations
910 * and SIMD8 is not allowed for DF operations.
912 * In this context, "DW operations" means "operations acting on 32-bit
913 * values", so it includes operations on floats.
915 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
916 * (Instruction Compression -> Rules and Restrictions):
918 * A compressed instruction must be in Align1 access mode. Align16
919 * mode instructions cannot be compressed.
921 * Similar text exists in the g45 PRM.
923 * On these platforms, if we're building a SIMD16 shader, we need to
924 * manually unroll to a pair of SIMD8 instructions.
926 bool unroll_to_simd8
=
927 (dispatch_width
== 16 &&
928 (devinfo
->gen
== 4 || (devinfo
->gen
== 7 && !devinfo
->is_haswell
)));
930 /* produce accurate derivatives */
931 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
934 BRW_VERTICAL_STRIDE_4
,
936 BRW_HORIZONTAL_STRIDE_1
,
937 BRW_SWIZZLE_XYXY
, WRITEMASK_XYZW
);
938 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
941 BRW_VERTICAL_STRIDE_4
,
943 BRW_HORIZONTAL_STRIDE_1
,
944 BRW_SWIZZLE_ZWZW
, WRITEMASK_XYZW
);
945 brw_push_insn_state(p
);
946 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
947 if (unroll_to_simd8
) {
948 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
949 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
951 brw_ADD(p
, firsthalf(dst
), firsthalf(src1
), negate(firsthalf(src0
)));
952 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
953 brw_ADD(p
, sechalf(dst
), sechalf(src1
), negate(sechalf(src0
)));
955 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), negate(firsthalf(src1
)));
956 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
957 brw_ADD(p
, sechalf(dst
), sechalf(src0
), negate(sechalf(src1
)));
961 brw_ADD(p
, dst
, src1
, negate(src0
));
963 brw_ADD(p
, dst
, src0
, negate(src1
));
965 brw_pop_insn_state(p
);
967 /* replicate the derivative at the top-left pixel to other pixels */
968 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
971 BRW_VERTICAL_STRIDE_4
,
973 BRW_HORIZONTAL_STRIDE_0
,
974 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
975 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
978 BRW_VERTICAL_STRIDE_4
,
980 BRW_HORIZONTAL_STRIDE_0
,
981 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
983 brw_ADD(p
, dst
, src1
, negate(src0
));
985 brw_ADD(p
, dst
, src0
, negate(src1
));
990 fs_generator::generate_discard_jump(fs_inst
*inst
)
992 assert(devinfo
->gen
>= 6);
994 /* This HALT will be patched up at FB write time to point UIP at the end of
995 * the program, and at brw_uip_jip() JIP will be set to the end of the
996 * current block (or the program).
998 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1000 brw_push_insn_state(p
);
1001 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1003 brw_pop_insn_state(p
);
1007 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1009 assert(inst
->mlen
!= 0);
1012 brw_uvec_mrf(inst
->exec_size
, (inst
->base_mrf
+ 1), 0),
1013 retype(src
, BRW_REGISTER_TYPE_UD
));
1014 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1015 inst
->exec_size
/ 8, inst
->offset
);
1019 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1021 assert(inst
->mlen
!= 0);
1023 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1024 inst
->exec_size
/ 8, inst
->offset
);
1028 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1030 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1034 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1036 struct brw_reg index
,
1037 struct brw_reg offset
)
1039 assert(inst
->mlen
!= 0);
1041 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1042 index
.type
== BRW_REGISTER_TYPE_UD
);
1043 uint32_t surf_index
= index
.dw1
.ud
;
1045 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1046 offset
.type
== BRW_REGISTER_TYPE_UD
);
1047 uint32_t read_offset
= offset
.dw1
.ud
;
1049 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1050 read_offset
, surf_index
);
1052 brw_mark_surface_used(prog_data
, surf_index
);
1056 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1058 struct brw_reg index
,
1059 struct brw_reg offset
)
1061 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1063 assert(offset
.file
== BRW_GENERAL_REGISTER_FILE
);
1064 /* Reference just the dword we need, to avoid angering validate_reg(). */
1065 offset
= brw_vec1_grf(offset
.nr
, 0);
1067 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1068 * the destination loaded consecutively from the same offset (which appears
1069 * in the first component, and the rest are ignored).
1071 dst
.width
= BRW_WIDTH_4
;
1073 struct brw_reg src
= offset
;
1074 bool header_present
= false;
1076 if (devinfo
->gen
>= 9) {
1077 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1078 src
= retype(brw_vec4_grf(offset
.nr
, 0), BRW_REGISTER_TYPE_UD
);
1079 header_present
= true;
1081 brw_push_insn_state(p
);
1082 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1083 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1084 brw_MOV(p
, vec8(src
), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1085 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1087 brw_MOV(p
, get_element_ud(src
, 2),
1088 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
));
1089 brw_pop_insn_state(p
);
1092 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1094 uint32_t surf_index
= index
.dw1
.ud
;
1096 brw_push_insn_state(p
);
1097 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1098 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1099 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1100 brw_pop_insn_state(p
);
1102 brw_set_dest(p
, send
, dst
);
1103 brw_set_src0(p
, send
, src
);
1104 brw_set_sampler_message(p
, send
,
1106 0, /* LD message ignores sampler unit */
1107 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1111 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1114 brw_mark_surface_used(prog_data
, surf_index
);
1118 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1120 brw_push_insn_state(p
);
1121 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1122 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1124 /* a0.0 = surf_index & 0xff */
1125 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1126 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1127 brw_set_dest(p
, insn_and
, addr
);
1128 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1129 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1131 /* dst = send(payload, a0.0 | <descriptor>) */
1132 brw_inst
*insn
= brw_send_indirect_message(
1133 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
1134 brw_set_sampler_message(p
, insn
,
1136 0, /* LD message ignores sampler unit */
1137 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1141 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1144 brw_pop_insn_state(p
);
1146 /* visitor knows more than we do about the surface limit required,
1147 * so has already done marking.
1154 fs_generator::generate_varying_pull_constant_load(fs_inst
*inst
,
1156 struct brw_reg index
,
1157 struct brw_reg offset
)
1159 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1160 assert(inst
->header_size
!= 0);
1163 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1164 index
.type
== BRW_REGISTER_TYPE_UD
);
1165 uint32_t surf_index
= index
.dw1
.ud
;
1167 uint32_t simd_mode
, rlen
, msg_type
;
1168 if (dispatch_width
== 16) {
1169 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1172 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1176 if (devinfo
->gen
>= 5)
1177 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1179 /* We always use the SIMD16 message so that we only have to load U, and
1182 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1183 assert(inst
->mlen
== 3);
1184 assert(inst
->regs_written
== 8);
1186 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1189 struct brw_reg offset_mrf
= retype(brw_message_reg(inst
->base_mrf
+ 1),
1190 BRW_REGISTER_TYPE_D
);
1191 brw_MOV(p
, offset_mrf
, offset
);
1193 struct brw_reg header
= brw_vec8_grf(0, 0);
1194 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1196 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1197 brw_inst_set_qtr_control(p
->devinfo
, send
, BRW_COMPRESSION_NONE
);
1198 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1199 brw_set_src0(p
, send
, header
);
1200 if (devinfo
->gen
< 6)
1201 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1203 /* Our surface is set up as floats, regardless of what actual data is
1206 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1207 brw_set_sampler_message(p
, send
,
1209 0, /* sampler (unused) */
1213 inst
->header_size
!= 0,
1217 brw_mark_surface_used(prog_data
, surf_index
);
1221 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1223 struct brw_reg index
,
1224 struct brw_reg offset
)
1226 assert(devinfo
->gen
>= 7);
1227 /* Varying-offset pull constant loads are treated as a normal expression on
1228 * gen7, so the fact that it's a send message is hidden at the IR level.
1230 assert(inst
->header_size
== 0);
1231 assert(!inst
->mlen
);
1232 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1234 uint32_t simd_mode
, rlen
, mlen
;
1235 if (dispatch_width
== 16) {
1238 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1242 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1245 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1247 uint32_t surf_index
= index
.dw1
.ud
;
1249 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1250 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1251 brw_set_src0(p
, send
, offset
);
1252 brw_set_sampler_message(p
, send
,
1254 0, /* LD message ignores sampler unit */
1255 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1258 false, /* no header */
1262 brw_mark_surface_used(prog_data
, surf_index
);
1266 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1268 brw_push_insn_state(p
);
1269 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1270 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1272 /* a0.0 = surf_index & 0xff */
1273 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1274 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1275 brw_set_dest(p
, insn_and
, addr
);
1276 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1277 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1279 brw_pop_insn_state(p
);
1281 /* dst = send(offset, a0.0 | <descriptor>) */
1282 brw_inst
*insn
= brw_send_indirect_message(
1283 p
, BRW_SFID_SAMPLER
, retype(dst
, BRW_REGISTER_TYPE_UW
),
1285 brw_set_sampler_message(p
, insn
,
1288 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1295 /* visitor knows more than we do about the surface limit required,
1296 * so has already done marking.
1302 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1303 * into the flags register (f0.0).
1305 * Used only on Gen6 and above.
1308 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
1310 struct brw_reg flags
= brw_flag_reg(0, inst
->flag_subreg
);
1311 struct brw_reg dispatch_mask
;
1313 if (devinfo
->gen
>= 6)
1314 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1316 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1318 brw_push_insn_state(p
);
1319 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1320 brw_MOV(p
, flags
, dispatch_mask
);
1321 brw_pop_insn_state(p
);
1325 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1328 struct brw_reg msg_data
,
1331 assert(msg_data
.file
== BRW_IMMEDIATE_VALUE
&&
1332 msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1334 brw_pixel_interpolator_query(p
,
1335 retype(dst
, BRW_REGISTER_TYPE_UW
),
1337 inst
->pi_noperspective
,
1341 inst
->regs_written
);
1346 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1347 * sampler LD messages.
1349 * We don't want to bake it into the send message's code generation because
1350 * that means we don't get a chance to schedule the instructions.
1353 fs_generator::generate_set_simd4x2_offset(fs_inst
*inst
,
1355 struct brw_reg value
)
1357 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1359 brw_push_insn_state(p
);
1360 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1361 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1362 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1363 brw_MOV(p
, retype(brw_vec1_reg(dst
.file
, dst
.nr
, 0), value
.type
), value
);
1364 brw_pop_insn_state(p
);
1367 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1368 * the ADD instruction.
1371 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1373 struct brw_reg src0
,
1374 struct brw_reg src1
)
1376 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1377 dst
.type
== BRW_REGISTER_TYPE_UD
);
1378 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1379 src0
.type
== BRW_REGISTER_TYPE_UD
);
1381 brw_push_insn_state(p
);
1382 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1383 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1384 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1385 struct brw_reg reg
= retype(stride(src1
, 1, 4, 0), BRW_REGISTER_TYPE_UW
);
1386 if (dispatch_width
== 8) {
1387 brw_ADD(p
, dst
, src0
, reg
);
1388 } else if (dispatch_width
== 16) {
1389 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), reg
);
1390 brw_ADD(p
, sechalf(dst
), sechalf(src0
), suboffset(reg
, 2));
1392 brw_pop_insn_state(p
);
1396 fs_generator::generate_pack_half_2x16_split(fs_inst
*inst
,
1401 assert(devinfo
->gen
>= 7);
1402 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1403 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1404 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1406 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1408 * Because this instruction does not have a 16-bit floating-point type,
1409 * the destination data type must be Word (W).
1411 * The destination must be DWord-aligned and specify a horizontal stride
1412 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1413 * each destination channel and the upper word is not modified.
1415 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1417 /* Give each 32-bit channel of dst the form below, where "." means
1421 brw_F32TO16(p
, dst_w
, y
);
1426 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1428 /* And, finally the form of packHalf2x16's output:
1431 brw_F32TO16(p
, dst_w
, x
);
1435 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
1439 assert(devinfo
->gen
>= 7);
1440 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1441 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1443 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1445 * Because this instruction does not have a 16-bit floating-point type,
1446 * the source data type must be Word (W). The destination type must be
1449 struct brw_reg src_w
= spread(retype(src
, BRW_REGISTER_TYPE_W
), 2);
1451 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1452 * For the Y case, we wish to access only the upper word; therefore
1453 * a 16-bit subregister offset is needed.
1455 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1456 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1457 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1460 brw_F16TO32(p
, dst
, src_w
);
1464 fs_generator::generate_shader_time_add(fs_inst
*inst
,
1465 struct brw_reg payload
,
1466 struct brw_reg offset
,
1467 struct brw_reg value
)
1469 assert(devinfo
->gen
>= 7);
1470 brw_push_insn_state(p
);
1471 brw_set_default_mask_control(p
, true);
1473 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1474 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1476 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1479 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1480 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1481 value
.width
= BRW_WIDTH_1
;
1482 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1483 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1485 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1488 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1489 * case, and we don't really care about squeezing every bit of performance
1490 * out of this path, so we just emit the MOVs from here.
1492 brw_MOV(p
, payload_offset
, offset
);
1493 brw_MOV(p
, payload_value
, value
);
1494 brw_shader_time_add(p
, payload
,
1495 prog_data
->binding_table
.shader_time_start
);
1496 brw_pop_insn_state(p
);
1498 brw_mark_surface_used(prog_data
,
1499 prog_data
->binding_table
.shader_time_start
);
1503 fs_generator::enable_debug(const char *shader_name
)
1506 this->shader_name
= shader_name
;
1510 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1512 /* align to 64 byte boundary. */
1513 while (p
->next_insn_offset
% 64)
1516 this->dispatch_width
= dispatch_width
;
1517 if (dispatch_width
== 16)
1518 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1520 int start_offset
= p
->next_insn_offset
;
1521 int spill_count
= 0, fill_count
= 0;
1524 struct annotation_info annotation
;
1525 memset(&annotation
, 0, sizeof(annotation
));
1527 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1528 struct brw_reg src
[3], dst
;
1529 unsigned int last_insn_offset
= p
->next_insn_offset
;
1530 bool multiple_instructions_emitted
= false;
1532 if (unlikely(debug_flag
))
1533 annotate(p
->devinfo
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1535 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1536 src
[i
] = brw_reg_from_fs_reg(inst
, &inst
->src
[i
]);
1538 /* The accumulator result appears to get used for the
1539 * conditional modifier generation. When negating a UD
1540 * value, there is a 33rd bit generated for the sign in the
1541 * accumulator value, so now you can't check, for example,
1542 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1544 assert(!inst
->conditional_mod
||
1545 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1546 !inst
->src
[i
].negate
);
1548 dst
= brw_reg_from_fs_reg(inst
, &inst
->dst
);
1550 brw_set_default_predicate_control(p
, inst
->predicate
);
1551 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1552 brw_set_default_flag_reg(p
, 0, inst
->flag_subreg
);
1553 brw_set_default_saturate(p
, inst
->saturate
);
1554 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1555 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1556 brw_set_default_exec_size(p
, cvt(inst
->exec_size
) - 1);
1558 switch (inst
->exec_size
) {
1562 assert(inst
->force_writemask_all
);
1563 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1566 if (inst
->force_sechalf
) {
1567 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1569 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1574 /* If the instruction writes to more than one register, it needs to
1575 * be a "compressed" instruction on Gen <= 5.
1577 if (inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
)
1578 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1580 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1583 unreachable("Invalid instruction width");
1586 switch (inst
->opcode
) {
1587 case BRW_OPCODE_MOV
:
1588 brw_MOV(p
, dst
, src
[0]);
1590 case BRW_OPCODE_ADD
:
1591 brw_ADD(p
, dst
, src
[0], src
[1]);
1593 case BRW_OPCODE_MUL
:
1594 brw_MUL(p
, dst
, src
[0], src
[1]);
1596 case BRW_OPCODE_AVG
:
1597 brw_AVG(p
, dst
, src
[0], src
[1]);
1599 case BRW_OPCODE_MACH
:
1600 brw_MACH(p
, dst
, src
[0], src
[1]);
1603 case BRW_OPCODE_LINE
:
1604 brw_LINE(p
, dst
, src
[0], src
[1]);
1607 case BRW_OPCODE_MAD
:
1608 assert(devinfo
->gen
>= 6);
1609 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1610 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1611 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1612 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1613 brw_inst
*f
= brw_MAD(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1614 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1615 brw_inst
*s
= brw_MAD(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1616 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1618 if (inst
->conditional_mod
) {
1619 brw_inst_set_cond_modifier(p
->devinfo
, f
, inst
->conditional_mod
);
1620 brw_inst_set_cond_modifier(p
->devinfo
, s
, inst
->conditional_mod
);
1621 multiple_instructions_emitted
= true;
1624 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1626 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1629 case BRW_OPCODE_LRP
:
1630 assert(devinfo
->gen
>= 6);
1631 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1632 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1633 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1634 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1635 brw_inst
*f
= brw_LRP(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1636 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1637 brw_inst
*s
= brw_LRP(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1638 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1640 if (inst
->conditional_mod
) {
1641 brw_inst_set_cond_modifier(p
->devinfo
, f
, inst
->conditional_mod
);
1642 brw_inst_set_cond_modifier(p
->devinfo
, s
, inst
->conditional_mod
);
1643 multiple_instructions_emitted
= true;
1646 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1648 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1651 case BRW_OPCODE_FRC
:
1652 brw_FRC(p
, dst
, src
[0]);
1654 case BRW_OPCODE_RNDD
:
1655 brw_RNDD(p
, dst
, src
[0]);
1657 case BRW_OPCODE_RNDE
:
1658 brw_RNDE(p
, dst
, src
[0]);
1660 case BRW_OPCODE_RNDZ
:
1661 brw_RNDZ(p
, dst
, src
[0]);
1664 case BRW_OPCODE_AND
:
1665 brw_AND(p
, dst
, src
[0], src
[1]);
1668 brw_OR(p
, dst
, src
[0], src
[1]);
1670 case BRW_OPCODE_XOR
:
1671 brw_XOR(p
, dst
, src
[0], src
[1]);
1673 case BRW_OPCODE_NOT
:
1674 brw_NOT(p
, dst
, src
[0]);
1676 case BRW_OPCODE_ASR
:
1677 brw_ASR(p
, dst
, src
[0], src
[1]);
1679 case BRW_OPCODE_SHR
:
1680 brw_SHR(p
, dst
, src
[0], src
[1]);
1682 case BRW_OPCODE_SHL
:
1683 brw_SHL(p
, dst
, src
[0], src
[1]);
1685 case BRW_OPCODE_F32TO16
:
1686 assert(devinfo
->gen
>= 7);
1687 brw_F32TO16(p
, dst
, src
[0]);
1689 case BRW_OPCODE_F16TO32
:
1690 assert(devinfo
->gen
>= 7);
1691 brw_F16TO32(p
, dst
, src
[0]);
1693 case BRW_OPCODE_CMP
:
1694 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1695 * that when the destination is a GRF that the dependency-clear bit on
1696 * the flag register is cleared early.
1698 * Suggested workarounds are to disable coissuing CMP instructions
1699 * or to split CMP(16) instructions into two CMP(8) instructions.
1701 * We choose to split into CMP(8) instructions since disabling
1702 * coissuing would affect CMP instructions not otherwise affected by
1705 if (dispatch_width
== 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1706 if (dst
.file
== BRW_GENERAL_REGISTER_FILE
) {
1707 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1708 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1709 brw_CMP(p
, firsthalf(dst
), inst
->conditional_mod
,
1710 firsthalf(src
[0]), firsthalf(src
[1]));
1711 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1712 brw_CMP(p
, sechalf(dst
), inst
->conditional_mod
,
1713 sechalf(src
[0]), sechalf(src
[1]));
1714 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1716 multiple_instructions_emitted
= true;
1717 } else if (dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1718 /* For unknown reasons, the aforementioned workaround is not
1719 * sufficient. Overriding the type when the destination is the
1720 * null register is necessary but not sufficient by itself.
1722 assert(dst
.nr
== BRW_ARF_NULL
);
1723 dst
.type
= BRW_REGISTER_TYPE_D
;
1724 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1726 unreachable("not reached");
1729 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1732 case BRW_OPCODE_SEL
:
1733 brw_SEL(p
, dst
, src
[0], src
[1]);
1735 case BRW_OPCODE_BFREV
:
1736 assert(devinfo
->gen
>= 7);
1737 /* BFREV only supports UD type for src and dst. */
1738 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1739 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1741 case BRW_OPCODE_FBH
:
1742 assert(devinfo
->gen
>= 7);
1743 /* FBH only supports UD type for dst. */
1744 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1746 case BRW_OPCODE_FBL
:
1747 assert(devinfo
->gen
>= 7);
1748 /* FBL only supports UD type for dst. */
1749 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1751 case BRW_OPCODE_CBIT
:
1752 assert(devinfo
->gen
>= 7);
1753 /* CBIT only supports UD type for dst. */
1754 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1756 case BRW_OPCODE_ADDC
:
1757 assert(devinfo
->gen
>= 7);
1758 brw_ADDC(p
, dst
, src
[0], src
[1]);
1760 case BRW_OPCODE_SUBB
:
1761 assert(devinfo
->gen
>= 7);
1762 brw_SUBB(p
, dst
, src
[0], src
[1]);
1764 case BRW_OPCODE_MAC
:
1765 brw_MAC(p
, dst
, src
[0], src
[1]);
1768 case BRW_OPCODE_BFE
:
1769 assert(devinfo
->gen
>= 7);
1770 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1771 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1772 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1773 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1774 brw_BFE(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1775 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1776 brw_BFE(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1777 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1779 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1781 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1784 case BRW_OPCODE_BFI1
:
1785 assert(devinfo
->gen
>= 7);
1786 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1789 * "Force BFI instructions to be executed always in SIMD8."
1791 if (dispatch_width
== 16 && devinfo
->is_haswell
) {
1792 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1793 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1794 brw_BFI1(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]));
1795 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1796 brw_BFI1(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]));
1797 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1799 brw_BFI1(p
, dst
, src
[0], src
[1]);
1802 case BRW_OPCODE_BFI2
:
1803 assert(devinfo
->gen
>= 7);
1804 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1805 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1808 * "Force BFI instructions to be executed always in SIMD8."
1810 * Otherwise we would be able to emit compressed instructions like we
1811 * do for the other three-source instructions.
1813 if (dispatch_width
== 16 &&
1814 (devinfo
->is_haswell
|| !devinfo
->supports_simd16_3src
)) {
1815 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1816 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1817 brw_BFI2(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1818 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1819 brw_BFI2(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1820 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1822 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1824 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1828 if (inst
->src
[0].file
!= BAD_FILE
) {
1829 /* The instruction has an embedded compare (only allowed on gen6) */
1830 assert(devinfo
->gen
== 6);
1831 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1833 brw_IF(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
1837 case BRW_OPCODE_ELSE
:
1840 case BRW_OPCODE_ENDIF
:
1845 brw_DO(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
1848 case BRW_OPCODE_BREAK
:
1850 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1852 case BRW_OPCODE_CONTINUE
:
1854 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1857 case BRW_OPCODE_WHILE
:
1862 case SHADER_OPCODE_RCP
:
1863 case SHADER_OPCODE_RSQ
:
1864 case SHADER_OPCODE_SQRT
:
1865 case SHADER_OPCODE_EXP2
:
1866 case SHADER_OPCODE_LOG2
:
1867 case SHADER_OPCODE_SIN
:
1868 case SHADER_OPCODE_COS
:
1869 assert(devinfo
->gen
< 6 || inst
->mlen
== 0);
1870 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1871 if (devinfo
->gen
>= 7) {
1872 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
1874 } else if (devinfo
->gen
== 6) {
1875 generate_math_gen6(inst
, dst
, src
[0], brw_null_reg());
1876 } else if (devinfo
->gen
== 5 || devinfo
->is_g4x
) {
1877 generate_math_g45(inst
, dst
, src
[0]);
1879 generate_math_gen4(inst
, dst
, src
[0]);
1882 case SHADER_OPCODE_INT_QUOTIENT
:
1883 case SHADER_OPCODE_INT_REMAINDER
:
1884 case SHADER_OPCODE_POW
:
1885 assert(devinfo
->gen
< 6 || inst
->mlen
== 0);
1886 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1887 if (devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) {
1888 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1889 } else if (devinfo
->gen
>= 6) {
1890 generate_math_gen6(inst
, dst
, src
[0], src
[1]);
1892 generate_math_gen4(inst
, dst
, src
[0]);
1895 case FS_OPCODE_CINTERP
:
1896 brw_MOV(p
, dst
, src
[0]);
1898 case FS_OPCODE_LINTERP
:
1899 generate_linterp(inst
, dst
, src
);
1901 case FS_OPCODE_PIXEL_X
:
1902 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1903 src
[0].subnr
= 0 * type_sz(src
[0].type
);
1904 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1906 case FS_OPCODE_PIXEL_Y
:
1907 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1908 src
[0].subnr
= 4 * type_sz(src
[0].type
);
1909 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1911 case SHADER_OPCODE_TEX
:
1913 case SHADER_OPCODE_TXD
:
1914 case SHADER_OPCODE_TXF
:
1915 case SHADER_OPCODE_TXF_CMS
:
1916 case SHADER_OPCODE_TXF_UMS
:
1917 case SHADER_OPCODE_TXF_MCS
:
1918 case SHADER_OPCODE_TXL
:
1919 case SHADER_OPCODE_TXS
:
1920 case SHADER_OPCODE_LOD
:
1921 case SHADER_OPCODE_TG4
:
1922 case SHADER_OPCODE_TG4_OFFSET
:
1923 generate_tex(inst
, dst
, src
[0], src
[1]);
1925 case FS_OPCODE_DDX_COARSE
:
1926 case FS_OPCODE_DDX_FINE
:
1927 generate_ddx(inst
->opcode
, dst
, src
[0]);
1929 case FS_OPCODE_DDY_COARSE
:
1930 case FS_OPCODE_DDY_FINE
:
1931 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
1932 generate_ddy(inst
->opcode
, dst
, src
[0], src
[1].dw1
.ud
);
1935 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1936 generate_scratch_write(inst
, src
[0]);
1940 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1941 generate_scratch_read(inst
, dst
);
1945 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
1946 generate_scratch_read_gen7(inst
, dst
);
1950 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1951 generate_urb_write(inst
, src
[0]);
1954 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1955 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1958 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
1959 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1962 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
1963 generate_varying_pull_constant_load(inst
, dst
, src
[0], src
[1]);
1966 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
1967 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
1970 case FS_OPCODE_REP_FB_WRITE
:
1971 case FS_OPCODE_FB_WRITE
:
1972 generate_fb_write(inst
, src
[0]);
1975 case FS_OPCODE_BLORP_FB_WRITE
:
1976 generate_blorp_fb_write(inst
);
1979 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
1980 generate_mov_dispatch_to_flags(inst
);
1983 case FS_OPCODE_DISCARD_JUMP
:
1984 generate_discard_jump(inst
);
1987 case SHADER_OPCODE_SHADER_TIME_ADD
:
1988 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
1991 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1992 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1993 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].dw1
.ud
,
1994 inst
->mlen
, !inst
->dst
.is_null());
1997 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1998 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1999 brw_untyped_surface_read(p
, dst
, src
[0], src
[1],
2000 inst
->mlen
, src
[2].dw1
.ud
);
2003 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
2004 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2005 brw_untyped_surface_write(p
, src
[0], src
[1],
2006 inst
->mlen
, src
[2].dw1
.ud
);
2009 case SHADER_OPCODE_TYPED_ATOMIC
:
2010 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2011 brw_typed_atomic(p
, dst
, src
[0], src
[1],
2012 src
[2].dw1
.ud
, inst
->mlen
, !inst
->dst
.is_null());
2015 case SHADER_OPCODE_TYPED_SURFACE_READ
:
2016 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2017 brw_typed_surface_read(p
, dst
, src
[0], src
[1],
2018 inst
->mlen
, src
[2].dw1
.ud
);
2021 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
2022 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2023 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
, src
[2].dw1
.ud
);
2026 case SHADER_OPCODE_MEMORY_FENCE
:
2027 brw_memory_fence(p
, dst
);
2030 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
2031 generate_set_simd4x2_offset(inst
, dst
, src
[0]);
2034 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2035 brw_find_live_channel(p
, dst
);
2038 case SHADER_OPCODE_BROADCAST
:
2039 brw_broadcast(p
, dst
, src
[0], src
[1]);
2042 case FS_OPCODE_SET_SAMPLE_ID
:
2043 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2046 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2047 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2050 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
2051 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
2052 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
2055 case FS_OPCODE_PLACEHOLDER_HALT
:
2056 /* This is the place where the final HALT needs to be inserted if
2057 * we've emitted any discards. If not, this will emit no code.
2059 if (!patch_discard_jumps_to_fb_writes()) {
2060 if (unlikely(debug_flag
)) {
2061 annotation
.ann_count
--;
2066 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
2067 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2068 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID
);
2071 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2072 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2073 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2076 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2077 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2078 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2081 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2082 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2083 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2086 case CS_OPCODE_CS_TERMINATE
:
2087 generate_cs_terminate(inst
, src
[0]);
2090 case SHADER_OPCODE_BARRIER
:
2091 generate_barrier(inst
, src
[0]);
2095 unreachable("Unsupported opcode");
2097 case SHADER_OPCODE_LOAD_PAYLOAD
:
2098 unreachable("Should be lowered by lower_load_payload()");
2101 if (multiple_instructions_emitted
)
2104 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2105 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2106 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2107 "emitting more than 1 instruction");
2109 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2111 if (inst
->conditional_mod
)
2112 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2113 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2114 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2119 annotation_finalize(&annotation
, p
->next_insn_offset
);
2121 int before_size
= p
->next_insn_offset
- start_offset
;
2122 brw_compact_instructions(p
, start_offset
, annotation
.ann_count
,
2124 int after_size
= p
->next_insn_offset
- start_offset
;
2126 if (unlikely(debug_flag
)) {
2127 fprintf(stderr
, "Native code for %s\n"
2128 "SIMD%d shader: %d instructions. %d loops. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2129 " bytes (%.0f%%)\n",
2130 shader_name
, dispatch_width
, before_size
/ 16, loop_count
,
2131 spill_count
, fill_count
, promoted_constants
, before_size
, after_size
,
2132 100.0f
* (before_size
- after_size
) / before_size
);
2134 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
,
2136 ralloc_free(annotation
.ann
);
2139 compiler
->shader_debug_log(log_data
,
2140 "%s SIMD%d shader: %d inst, %d loops, "
2141 "%d:%d spills:fills, Promoted %u constants, "
2142 "compacted %d to %d bytes.\n",
2143 stage_abbrev
, dispatch_width
, before_size
/ 16,
2144 loop_count
, spill_count
, fill_count
,
2145 promoted_constants
, before_size
, after_size
);
2147 return start_offset
;
2151 fs_generator::get_assembly(unsigned int *assembly_size
)
2153 return brw_get_program(p
, assembly_size
);