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[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 fs_generator::fs_generator(struct brw_context *brw,
40 void *mem_ctx,
41 const struct brw_wm_prog_key *key,
42 struct brw_wm_prog_data *prog_data,
43 struct gl_shader_program *prog,
44 struct gl_fragment_program *fp,
45 bool dual_source_output,
46 bool runtime_check_aads_emit,
47 bool debug_flag)
48
49 : brw(brw), key(key), prog_data(prog_data), prog(prog), fp(fp),
50 dual_source_output(dual_source_output),
51 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(debug_flag),
52 mem_ctx(mem_ctx)
53 {
54 ctx = &brw->ctx;
55
56 p = rzalloc(mem_ctx, struct brw_compile);
57 brw_init_compile(brw, p, mem_ctx);
58 }
59
60 fs_generator::~fs_generator()
61 {
62 }
63
64 bool
65 fs_generator::patch_discard_jumps_to_fb_writes()
66 {
67 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
68 return false;
69
70 /* There is a somewhat strange undocumented requirement of using
71 * HALT, according to the simulator. If some channel has HALTed to
72 * a particular UIP, then by the end of the program, every channel
73 * must have HALTed to that UIP. Furthermore, the tracking is a
74 * stack, so you can't do the final halt of a UIP after starting
75 * halting to a new UIP.
76 *
77 * Symptoms of not emitting this instruction on actual hardware
78 * included GPU hangs and sparkly rendering on the piglit discard
79 * tests.
80 */
81 struct brw_instruction *last_halt = gen6_HALT(p);
82 last_halt->bits3.break_cont.uip = 2;
83 last_halt->bits3.break_cont.jip = 2;
84
85 int ip = p->nr_insn;
86
87 foreach_list(node, &this->discard_halt_patches) {
88 ip_record *patch_ip = (ip_record *)node;
89 struct brw_instruction *patch = &p->store[patch_ip->ip];
90
91 assert(patch->header.opcode == BRW_OPCODE_HALT);
92 /* HALT takes a half-instruction distance from the pre-incremented IP. */
93 patch->bits3.break_cont.uip = (ip - patch_ip->ip) * 2;
94 }
95
96 this->discard_halt_patches.make_empty();
97 return true;
98 }
99
100 void
101 fs_generator::fire_fb_write(fs_inst *inst,
102 GLuint base_reg,
103 struct brw_reg implied_header,
104 GLuint nr)
105 {
106 uint32_t msg_control;
107
108 if (brw->gen < 6) {
109 brw_push_insn_state(p);
110 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
111 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
112 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
113 brw_MOV(p,
114 brw_message_reg(base_reg + 1),
115 brw_vec8_grf(1, 0));
116 brw_pop_insn_state(p);
117 }
118
119 if (this->dual_source_output)
120 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
121 else if (dispatch_width == 16)
122 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
123 else
124 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
125
126 uint32_t surf_index =
127 prog_data->binding_table.render_target_start + inst->target;
128
129 brw_fb_WRITE(p,
130 dispatch_width,
131 base_reg,
132 implied_header,
133 msg_control,
134 surf_index,
135 nr,
136 0,
137 inst->eot,
138 inst->header_present);
139
140 brw_mark_surface_used(&prog_data->base, surf_index);
141 }
142
143 void
144 fs_generator::generate_fb_write(fs_inst *inst)
145 {
146 struct brw_reg implied_header;
147
148 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
149 * move, here's g1.
150 */
151 brw_push_insn_state(p);
152 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
153 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
154 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
155
156 if (inst->header_present) {
157 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
158 * present.
159 */
160 if ((fp && fp->UsesKill) || key->alpha_test_func) {
161 struct brw_reg pixel_mask;
162
163 if (brw->gen >= 6)
164 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
165 else
166 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
167
168 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
169 }
170
171 if (brw->gen >= 6) {
172 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
173 brw_MOV(p,
174 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
175 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
176 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
177
178 if (inst->target > 0 && key->replicate_alpha) {
179 /* Set "Source0 Alpha Present to RenderTarget" bit in message
180 * header.
181 */
182 brw_OR(p,
183 vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)),
184 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
185 brw_imm_ud(0x1 << 11));
186 }
187
188 if (inst->target > 0) {
189 /* Set the render target index for choosing BLEND_STATE. */
190 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
191 inst->base_mrf, 2),
192 BRW_REGISTER_TYPE_UD),
193 brw_imm_ud(inst->target));
194 }
195
196 implied_header = brw_null_reg();
197 } else {
198 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
199 }
200 } else {
201 implied_header = brw_null_reg();
202 }
203
204 brw_pop_insn_state(p);
205
206 if (!runtime_check_aads_emit) {
207 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
208 } else {
209 /* This can only happen in gen < 6 */
210 assert(brw->gen < 6);
211
212 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
213
214 /* Check runtime bit to detect if we have to send AA data or not */
215 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
216 brw_AND(p,
217 v1_null_ud,
218 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
219 brw_imm_ud(1<<26));
220 brw_last_inst->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ;
221
222 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
223 brw_last_inst->header.execution_size = BRW_EXECUTE_1;
224 {
225 /* Don't send AA data */
226 fire_fb_write(inst, inst->base_mrf+1, implied_header, inst->mlen-1);
227 }
228 brw_land_fwd_jump(p, jmp);
229 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
230 }
231 }
232
233 void
234 fs_generator::generate_blorp_fb_write(fs_inst *inst)
235 {
236 brw_fb_WRITE(p,
237 16 /* dispatch_width */,
238 inst->base_mrf,
239 brw_reg_from_fs_reg(&inst->src[0]),
240 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
241 inst->target,
242 inst->mlen,
243 0,
244 true,
245 inst->header_present);
246 }
247
248 /* Computes the integer pixel x,y values from the origin.
249 *
250 * This is the basis of gl_FragCoord computation, but is also used
251 * pre-gen6 for computing the deltas from v0 for computing
252 * interpolation.
253 */
254 void
255 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
256 {
257 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
258 struct brw_reg src;
259 struct brw_reg deltas;
260
261 if (is_x) {
262 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
263 deltas = brw_imm_v(0x10101010);
264 } else {
265 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
266 deltas = brw_imm_v(0x11001100);
267 }
268
269 if (dispatch_width == 16) {
270 dst = vec16(dst);
271 }
272
273 /* We do this SIMD8 or SIMD16, but since the destination is UW we
274 * don't do compression in the SIMD16 case.
275 */
276 brw_push_insn_state(p);
277 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
278 brw_ADD(p, dst, src, deltas);
279 brw_pop_insn_state(p);
280 }
281
282 void
283 fs_generator::generate_linterp(fs_inst *inst,
284 struct brw_reg dst, struct brw_reg *src)
285 {
286 struct brw_reg delta_x = src[0];
287 struct brw_reg delta_y = src[1];
288 struct brw_reg interp = src[2];
289
290 if (brw->has_pln &&
291 delta_y.nr == delta_x.nr + 1 &&
292 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
293 brw_PLN(p, dst, interp, delta_x);
294 } else {
295 brw_LINE(p, brw_null_reg(), interp, delta_x);
296 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
297 }
298 }
299
300 void
301 fs_generator::generate_math_gen6(fs_inst *inst,
302 struct brw_reg dst,
303 struct brw_reg src0,
304 struct brw_reg src1)
305 {
306 int op = brw_math_function(inst->opcode);
307 bool binop = src1.file == BRW_GENERAL_REGISTER_FILE;
308
309 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
310 gen6_math(p, dst, op, src0, src1);
311
312 if (dispatch_width == 16) {
313 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
314 gen6_math(p, sechalf(dst), op, sechalf(src0),
315 binop ? sechalf(src1) : brw_null_reg());
316 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
317 }
318 }
319
320 void
321 fs_generator::generate_math_gen4(fs_inst *inst,
322 struct brw_reg dst,
323 struct brw_reg src)
324 {
325 int op = brw_math_function(inst->opcode);
326
327 assert(inst->mlen >= 1);
328
329 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
330 gen4_math(p, dst,
331 op,
332 inst->base_mrf, src,
333 BRW_MATH_DATA_VECTOR,
334 BRW_MATH_PRECISION_FULL);
335
336 if (dispatch_width == 16) {
337 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
338 gen4_math(p, sechalf(dst),
339 op,
340 inst->base_mrf + 1, sechalf(src),
341 BRW_MATH_DATA_VECTOR,
342 BRW_MATH_PRECISION_FULL);
343
344 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
345 }
346 }
347
348 void
349 fs_generator::generate_math_g45(fs_inst *inst,
350 struct brw_reg dst,
351 struct brw_reg src)
352 {
353 if (inst->opcode == SHADER_OPCODE_POW ||
354 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
355 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
356 generate_math_gen4(inst, dst, src);
357 return;
358 }
359
360 int op = brw_math_function(inst->opcode);
361
362 assert(inst->mlen >= 1);
363
364 gen4_math(p, dst,
365 op,
366 inst->base_mrf, src,
367 BRW_MATH_DATA_VECTOR,
368 BRW_MATH_PRECISION_FULL);
369 }
370
371 void
372 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
373 {
374 int msg_type = -1;
375 int rlen = 4;
376 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
377 uint32_t return_format;
378
379 switch (dst.type) {
380 case BRW_REGISTER_TYPE_D:
381 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
382 break;
383 case BRW_REGISTER_TYPE_UD:
384 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
385 break;
386 default:
387 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
388 break;
389 }
390
391 if (dispatch_width == 16 &&
392 !inst->force_uncompressed && !inst->force_sechalf)
393 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
394
395 if (brw->gen >= 5) {
396 switch (inst->opcode) {
397 case SHADER_OPCODE_TEX:
398 if (inst->shadow_compare) {
399 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
400 } else {
401 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
402 }
403 break;
404 case FS_OPCODE_TXB:
405 if (inst->shadow_compare) {
406 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
407 } else {
408 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
409 }
410 break;
411 case SHADER_OPCODE_TXL:
412 if (inst->shadow_compare) {
413 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
414 } else {
415 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
416 }
417 break;
418 case SHADER_OPCODE_TXS:
419 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
420 break;
421 case SHADER_OPCODE_TXD:
422 if (inst->shadow_compare) {
423 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
424 assert(brw->is_haswell);
425 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
426 } else {
427 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
428 }
429 break;
430 case SHADER_OPCODE_TXF:
431 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
432 break;
433 case SHADER_OPCODE_TXF_CMS:
434 if (brw->gen >= 7)
435 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
436 else
437 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
438 break;
439 case SHADER_OPCODE_TXF_UMS:
440 assert(brw->gen >= 7);
441 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
442 break;
443 case SHADER_OPCODE_TXF_MCS:
444 assert(brw->gen >= 7);
445 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
446 break;
447 case SHADER_OPCODE_LOD:
448 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
449 break;
450 case SHADER_OPCODE_TG4:
451 if (inst->shadow_compare) {
452 assert(brw->gen >= 7);
453 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
454 } else {
455 assert(brw->gen >= 6);
456 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
457 }
458 break;
459 case SHADER_OPCODE_TG4_OFFSET:
460 assert(brw->gen >= 7);
461 if (inst->shadow_compare) {
462 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
463 } else {
464 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
465 }
466 break;
467 default:
468 assert(!"not reached");
469 break;
470 }
471 } else {
472 switch (inst->opcode) {
473 case SHADER_OPCODE_TEX:
474 /* Note that G45 and older determines shadow compare and dispatch width
475 * from message length for most messages.
476 */
477 assert(dispatch_width == 8);
478 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
479 if (inst->shadow_compare) {
480 assert(inst->mlen == 6);
481 } else {
482 assert(inst->mlen <= 4);
483 }
484 break;
485 case FS_OPCODE_TXB:
486 if (inst->shadow_compare) {
487 assert(inst->mlen == 6);
488 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
489 } else {
490 assert(inst->mlen == 9);
491 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
492 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
493 }
494 break;
495 case SHADER_OPCODE_TXL:
496 if (inst->shadow_compare) {
497 assert(inst->mlen == 6);
498 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
499 } else {
500 assert(inst->mlen == 9);
501 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
502 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
503 }
504 break;
505 case SHADER_OPCODE_TXD:
506 /* There is no sample_d_c message; comparisons are done manually */
507 assert(inst->mlen == 7 || inst->mlen == 10);
508 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
509 break;
510 case SHADER_OPCODE_TXF:
511 assert(inst->mlen == 9);
512 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
513 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
514 break;
515 case SHADER_OPCODE_TXS:
516 assert(inst->mlen == 3);
517 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
518 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
519 break;
520 default:
521 assert(!"not reached");
522 break;
523 }
524 }
525 assert(msg_type != -1);
526
527 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
528 rlen = 8;
529 dst = vec16(dst);
530 }
531
532 if (brw->gen >= 7 && inst->header_present && dispatch_width == 16) {
533 /* The send-from-GRF for SIMD16 texturing with a header has an extra
534 * hardware register allocated to it, which we need to skip over (since
535 * our coordinates in the payload are in the even-numbered registers,
536 * and the header comes right before the first one).
537 */
538 assert(src.file == BRW_GENERAL_REGISTER_FILE);
539 src.nr++;
540 }
541
542 /* Load the message header if present. If there's a texture offset,
543 * we need to set it up explicitly and load the offset bitfield.
544 * Otherwise, we can use an implied move from g0 to the first message reg.
545 */
546 if (inst->header_present) {
547 if (brw->gen < 6 && !inst->texture_offset) {
548 /* Set up an implied move from g0 to the MRF. */
549 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
550 } else {
551 struct brw_reg header_reg;
552
553 if (brw->gen >= 7) {
554 header_reg = src;
555 } else {
556 assert(inst->base_mrf != -1);
557 header_reg = brw_message_reg(inst->base_mrf);
558 }
559
560 brw_push_insn_state(p);
561 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
562 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
563 /* Explicitly set up the message header by copying g0 to the MRF. */
564 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
565
566 if (inst->texture_offset) {
567 /* Set the offset bits in DWord 2. */
568 brw_MOV(p, get_element_ud(header_reg, 2),
569 brw_imm_ud(inst->texture_offset));
570 }
571
572 if (inst->sampler >= 16) {
573 /* The "Sampler Index" field can only store values between 0 and 15.
574 * However, we can add an offset to the "Sampler State Pointer"
575 * field, effectively selecting a different set of 16 samplers.
576 *
577 * The "Sampler State Pointer" needs to be aligned to a 32-byte
578 * offset, and each sampler state is only 16-bytes, so we can't
579 * exclusively use the offset - we have to use both.
580 */
581 assert(brw->is_haswell); /* field only exists on Haswell */
582 brw_ADD(p,
583 get_element_ud(header_reg, 3),
584 get_element_ud(brw_vec8_grf(0, 0), 3),
585 brw_imm_ud(16 * (inst->sampler / 16) *
586 sizeof(gen7_sampler_state)));
587 }
588 brw_pop_insn_state(p);
589 }
590 }
591
592 uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
593 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
594 ? prog_data->base.binding_table.gather_texture_start
595 : prog_data->base.binding_table.texture_start) + inst->sampler;
596
597 brw_SAMPLE(p,
598 retype(dst, BRW_REGISTER_TYPE_UW),
599 inst->base_mrf,
600 src,
601 surface_index,
602 inst->sampler % 16,
603 msg_type,
604 rlen,
605 inst->mlen,
606 inst->header_present,
607 simd_mode,
608 return_format);
609
610 brw_mark_surface_used(&prog_data->base, surface_index);
611 }
612
613
614 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
615 * looking like:
616 *
617 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
618 *
619 * Ideally, we want to produce:
620 *
621 * DDX DDY
622 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
623 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
624 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
625 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
626 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
627 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
628 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
629 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
630 *
631 * and add another set of two more subspans if in 16-pixel dispatch mode.
632 *
633 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
634 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
635 * pair. But the ideal approximation may impose a huge performance cost on
636 * sample_d. On at least Haswell, sample_d instruction does some
637 * optimizations if the same LOD is used for all pixels in the subspan.
638 *
639 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
640 * appropriate swizzling.
641 */
642 void
643 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
644 {
645 unsigned vstride, width;
646
647 if (key->high_quality_derivatives) {
648 /* produce accurate derivatives */
649 vstride = BRW_VERTICAL_STRIDE_2;
650 width = BRW_WIDTH_2;
651 }
652 else {
653 /* replicate the derivative at the top-left pixel to other pixels */
654 vstride = BRW_VERTICAL_STRIDE_4;
655 width = BRW_WIDTH_4;
656 }
657
658 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
659 BRW_REGISTER_TYPE_F,
660 vstride,
661 width,
662 BRW_HORIZONTAL_STRIDE_0,
663 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
664 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
665 BRW_REGISTER_TYPE_F,
666 vstride,
667 width,
668 BRW_HORIZONTAL_STRIDE_0,
669 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
670 brw_ADD(p, dst, src0, negate(src1));
671 }
672
673 /* The negate_value boolean is used to negate the derivative computation for
674 * FBOs, since they place the origin at the upper left instead of the lower
675 * left.
676 */
677 void
678 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
679 bool negate_value)
680 {
681 if (key->high_quality_derivatives) {
682 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
683 * Region Restrictions):
684 *
685 * In Align16 access mode, SIMD16 is not allowed for DW operations
686 * and SIMD8 is not allowed for DF operations.
687 *
688 * In this context, "DW operations" means "operations acting on 32-bit
689 * values", so it includes operations on floats.
690 *
691 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
692 * (Instruction Compression -> Rules and Restrictions):
693 *
694 * A compressed instruction must be in Align1 access mode. Align16
695 * mode instructions cannot be compressed.
696 *
697 * Similar text exists in the g45 PRM.
698 *
699 * On these platforms, if we're building a SIMD16 shader, we need to
700 * manually unroll to a pair of SIMD8 instructions.
701 */
702 bool unroll_to_simd8 =
703 (dispatch_width == 16 &&
704 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
705
706 /* produce accurate derivatives */
707 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
708 BRW_REGISTER_TYPE_F,
709 BRW_VERTICAL_STRIDE_4,
710 BRW_WIDTH_4,
711 BRW_HORIZONTAL_STRIDE_1,
712 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
713 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
714 BRW_REGISTER_TYPE_F,
715 BRW_VERTICAL_STRIDE_4,
716 BRW_WIDTH_4,
717 BRW_HORIZONTAL_STRIDE_1,
718 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
719 brw_push_insn_state(p);
720 brw_set_default_access_mode(p, BRW_ALIGN_16);
721 if (unroll_to_simd8)
722 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
723 if (negate_value)
724 brw_ADD(p, dst, src1, negate(src0));
725 else
726 brw_ADD(p, dst, src0, negate(src1));
727 if (unroll_to_simd8) {
728 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
729 src0 = sechalf(src0);
730 src1 = sechalf(src1);
731 dst = sechalf(dst);
732 if (negate_value)
733 brw_ADD(p, dst, src1, negate(src0));
734 else
735 brw_ADD(p, dst, src0, negate(src1));
736 }
737 brw_pop_insn_state(p);
738 } else {
739 /* replicate the derivative at the top-left pixel to other pixels */
740 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
741 BRW_REGISTER_TYPE_F,
742 BRW_VERTICAL_STRIDE_4,
743 BRW_WIDTH_4,
744 BRW_HORIZONTAL_STRIDE_0,
745 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
746 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
747 BRW_REGISTER_TYPE_F,
748 BRW_VERTICAL_STRIDE_4,
749 BRW_WIDTH_4,
750 BRW_HORIZONTAL_STRIDE_0,
751 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
752 if (negate_value)
753 brw_ADD(p, dst, src1, negate(src0));
754 else
755 brw_ADD(p, dst, src0, negate(src1));
756 }
757 }
758
759 void
760 fs_generator::generate_discard_jump(fs_inst *inst)
761 {
762 assert(brw->gen >= 6);
763
764 /* This HALT will be patched up at FB write time to point UIP at the end of
765 * the program, and at brw_uip_jip() JIP will be set to the end of the
766 * current block (or the program).
767 */
768 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
769
770 brw_push_insn_state(p);
771 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
772 gen6_HALT(p);
773 brw_pop_insn_state(p);
774 }
775
776 void
777 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
778 {
779 assert(inst->mlen != 0);
780
781 brw_MOV(p,
782 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
783 retype(src, BRW_REGISTER_TYPE_UD));
784 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
785 dispatch_width / 8, inst->offset);
786 }
787
788 void
789 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
790 {
791 assert(inst->mlen != 0);
792
793 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
794 dispatch_width / 8, inst->offset);
795 }
796
797 void
798 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
799 {
800 gen7_block_read_scratch(p, dst, dispatch_width / 8, inst->offset);
801 }
802
803 void
804 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
805 struct brw_reg dst,
806 struct brw_reg index,
807 struct brw_reg offset)
808 {
809 assert(inst->mlen != 0);
810
811 assert(index.file == BRW_IMMEDIATE_VALUE &&
812 index.type == BRW_REGISTER_TYPE_UD);
813 uint32_t surf_index = index.dw1.ud;
814
815 assert(offset.file == BRW_IMMEDIATE_VALUE &&
816 offset.type == BRW_REGISTER_TYPE_UD);
817 uint32_t read_offset = offset.dw1.ud;
818
819 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
820 read_offset, surf_index);
821
822 brw_mark_surface_used(&prog_data->base, surf_index);
823 }
824
825 void
826 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
827 struct brw_reg dst,
828 struct brw_reg index,
829 struct brw_reg offset)
830 {
831 assert(inst->mlen == 0);
832
833 assert(index.file == BRW_IMMEDIATE_VALUE &&
834 index.type == BRW_REGISTER_TYPE_UD);
835 uint32_t surf_index = index.dw1.ud;
836
837 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
838 /* Reference just the dword we need, to avoid angering validate_reg(). */
839 offset = brw_vec1_grf(offset.nr, 0);
840
841 brw_push_insn_state(p);
842 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
843 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
844 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
845 brw_pop_insn_state(p);
846
847 /* We use the SIMD4x2 mode because we want to end up with 4 components in
848 * the destination loaded consecutively from the same offset (which appears
849 * in the first component, and the rest are ignored).
850 */
851 dst.width = BRW_WIDTH_4;
852 brw_set_dest(p, send, dst);
853 brw_set_src0(p, send, offset);
854 brw_set_sampler_message(p, send,
855 surf_index,
856 0, /* LD message ignores sampler unit */
857 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
858 1, /* rlen */
859 1, /* mlen */
860 false, /* no header */
861 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
862 0);
863
864 brw_mark_surface_used(&prog_data->base, surf_index);
865 }
866
867 void
868 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
869 struct brw_reg dst,
870 struct brw_reg index,
871 struct brw_reg offset)
872 {
873 assert(brw->gen < 7); /* Should use the gen7 variant. */
874 assert(inst->header_present);
875 assert(inst->mlen);
876
877 assert(index.file == BRW_IMMEDIATE_VALUE &&
878 index.type == BRW_REGISTER_TYPE_UD);
879 uint32_t surf_index = index.dw1.ud;
880
881 uint32_t simd_mode, rlen, msg_type;
882 if (dispatch_width == 16) {
883 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
884 rlen = 8;
885 } else {
886 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
887 rlen = 4;
888 }
889
890 if (brw->gen >= 5)
891 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
892 else {
893 /* We always use the SIMD16 message so that we only have to load U, and
894 * not V or R.
895 */
896 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
897 assert(inst->mlen == 3);
898 assert(inst->regs_written == 8);
899 rlen = 8;
900 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
901 }
902
903 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
904 BRW_REGISTER_TYPE_D);
905 brw_MOV(p, offset_mrf, offset);
906
907 struct brw_reg header = brw_vec8_grf(0, 0);
908 gen6_resolve_implied_move(p, &header, inst->base_mrf);
909
910 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
911 send->header.compression_control = BRW_COMPRESSION_NONE;
912 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
913 brw_set_src0(p, send, header);
914 if (brw->gen < 6)
915 send->header.destreg__conditionalmod = inst->base_mrf;
916
917 /* Our surface is set up as floats, regardless of what actual data is
918 * stored in it.
919 */
920 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
921 brw_set_sampler_message(p, send,
922 surf_index,
923 0, /* sampler (unused) */
924 msg_type,
925 rlen,
926 inst->mlen,
927 inst->header_present,
928 simd_mode,
929 return_format);
930
931 brw_mark_surface_used(&prog_data->base, surf_index);
932 }
933
934 void
935 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
936 struct brw_reg dst,
937 struct brw_reg index,
938 struct brw_reg offset)
939 {
940 assert(brw->gen >= 7);
941 /* Varying-offset pull constant loads are treated as a normal expression on
942 * gen7, so the fact that it's a send message is hidden at the IR level.
943 */
944 assert(!inst->header_present);
945 assert(!inst->mlen);
946
947 assert(index.file == BRW_IMMEDIATE_VALUE &&
948 index.type == BRW_REGISTER_TYPE_UD);
949 uint32_t surf_index = index.dw1.ud;
950
951 uint32_t simd_mode, rlen, mlen;
952 if (dispatch_width == 16) {
953 mlen = 2;
954 rlen = 8;
955 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
956 } else {
957 mlen = 1;
958 rlen = 4;
959 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
960 }
961
962 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
963 brw_set_dest(p, send, dst);
964 brw_set_src0(p, send, offset);
965 brw_set_sampler_message(p, send,
966 surf_index,
967 0, /* LD message ignores sampler unit */
968 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
969 rlen,
970 mlen,
971 false, /* no header */
972 simd_mode,
973 0);
974
975 brw_mark_surface_used(&prog_data->base, surf_index);
976 }
977
978 /**
979 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
980 * into the flags register (f0.0).
981 *
982 * Used only on Gen6 and above.
983 */
984 void
985 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
986 {
987 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
988 struct brw_reg dispatch_mask;
989
990 if (brw->gen >= 6)
991 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
992 else
993 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
994
995 brw_push_insn_state(p);
996 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
997 brw_MOV(p, flags, dispatch_mask);
998 brw_pop_insn_state(p);
999 }
1000
1001
1002 static uint32_t brw_file_from_reg(fs_reg *reg)
1003 {
1004 switch (reg->file) {
1005 case GRF:
1006 return BRW_GENERAL_REGISTER_FILE;
1007 case MRF:
1008 return BRW_MESSAGE_REGISTER_FILE;
1009 case IMM:
1010 return BRW_IMMEDIATE_VALUE;
1011 default:
1012 assert(!"not reached");
1013 return BRW_GENERAL_REGISTER_FILE;
1014 }
1015 }
1016
1017 struct brw_reg
1018 brw_reg_from_fs_reg(fs_reg *reg)
1019 {
1020 struct brw_reg brw_reg;
1021
1022 switch (reg->file) {
1023 case GRF:
1024 case MRF:
1025 if (reg->stride == 0) {
1026 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
1027 } else {
1028 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1029 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
1030 }
1031
1032 brw_reg = retype(brw_reg, reg->type);
1033 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
1034 break;
1035 case IMM:
1036 switch (reg->type) {
1037 case BRW_REGISTER_TYPE_F:
1038 brw_reg = brw_imm_f(reg->imm.f);
1039 break;
1040 case BRW_REGISTER_TYPE_D:
1041 brw_reg = brw_imm_d(reg->imm.i);
1042 break;
1043 case BRW_REGISTER_TYPE_UD:
1044 brw_reg = brw_imm_ud(reg->imm.u);
1045 break;
1046 default:
1047 assert(!"not reached");
1048 brw_reg = brw_null_reg();
1049 break;
1050 }
1051 break;
1052 case HW_REG:
1053 assert(reg->type == reg->fixed_hw_reg.type);
1054 brw_reg = reg->fixed_hw_reg;
1055 break;
1056 case BAD_FILE:
1057 /* Probably unused. */
1058 brw_reg = brw_null_reg();
1059 break;
1060 case UNIFORM:
1061 assert(!"not reached");
1062 brw_reg = brw_null_reg();
1063 break;
1064 default:
1065 assert(!"not reached");
1066 brw_reg = brw_null_reg();
1067 break;
1068 }
1069 if (reg->abs)
1070 brw_reg = brw_abs(brw_reg);
1071 if (reg->negate)
1072 brw_reg = negate(brw_reg);
1073
1074 return brw_reg;
1075 }
1076
1077 /**
1078 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1079 * sampler LD messages.
1080 *
1081 * We don't want to bake it into the send message's code generation because
1082 * that means we don't get a chance to schedule the instructions.
1083 */
1084 void
1085 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1086 struct brw_reg dst,
1087 struct brw_reg value)
1088 {
1089 assert(value.file == BRW_IMMEDIATE_VALUE);
1090
1091 brw_push_insn_state(p);
1092 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1093 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1094 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1095 brw_pop_insn_state(p);
1096 }
1097
1098 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1099 * (when mask is passed as a uniform) of register mask before moving it
1100 * to register dst.
1101 */
1102 void
1103 fs_generator::generate_set_omask(fs_inst *inst,
1104 struct brw_reg dst,
1105 struct brw_reg mask)
1106 {
1107 bool stride_8_8_1 =
1108 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1109 mask.width == BRW_WIDTH_8 &&
1110 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1111
1112 bool stride_0_1_0 =
1113 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1114 mask.width == BRW_WIDTH_1 &&
1115 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1116
1117 assert(stride_8_8_1 || stride_0_1_0);
1118 assert(dst.type == BRW_REGISTER_TYPE_UW);
1119
1120 if (dispatch_width == 16)
1121 dst = vec16(dst);
1122 brw_push_insn_state(p);
1123 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1124 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1125
1126 if (stride_8_8_1) {
1127 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1128 } else if (stride_0_1_0) {
1129 brw_MOV(p, dst, retype(mask, dst.type));
1130 }
1131 brw_pop_insn_state(p);
1132 }
1133
1134 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1135 * the ADD instruction.
1136 */
1137 void
1138 fs_generator::generate_set_sample_id(fs_inst *inst,
1139 struct brw_reg dst,
1140 struct brw_reg src0,
1141 struct brw_reg src1)
1142 {
1143 assert(dst.type == BRW_REGISTER_TYPE_D ||
1144 dst.type == BRW_REGISTER_TYPE_UD);
1145 assert(src0.type == BRW_REGISTER_TYPE_D ||
1146 src0.type == BRW_REGISTER_TYPE_UD);
1147
1148 brw_push_insn_state(p);
1149 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1150 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1151 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1152 brw_ADD(p, dst, src0, reg);
1153 if (dispatch_width == 16)
1154 brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
1155 brw_pop_insn_state(p);
1156 }
1157
1158 /**
1159 * Change the register's data type from UD to W, doubling the strides in order
1160 * to compensate for halving the data type width.
1161 */
1162 static struct brw_reg
1163 ud_reg_to_w(struct brw_reg r)
1164 {
1165 assert(r.type == BRW_REGISTER_TYPE_UD);
1166 r.type = BRW_REGISTER_TYPE_W;
1167
1168 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1169 * doubles the real stride.
1170 */
1171 if (r.hstride != 0)
1172 ++r.hstride;
1173 if (r.vstride != 0)
1174 ++r.vstride;
1175
1176 return r;
1177 }
1178
1179 void
1180 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1181 struct brw_reg dst,
1182 struct brw_reg x,
1183 struct brw_reg y)
1184 {
1185 assert(brw->gen >= 7);
1186 assert(dst.type == BRW_REGISTER_TYPE_UD);
1187 assert(x.type == BRW_REGISTER_TYPE_F);
1188 assert(y.type == BRW_REGISTER_TYPE_F);
1189
1190 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1191 *
1192 * Because this instruction does not have a 16-bit floating-point type,
1193 * the destination data type must be Word (W).
1194 *
1195 * The destination must be DWord-aligned and specify a horizontal stride
1196 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1197 * each destination channel and the upper word is not modified.
1198 */
1199 struct brw_reg dst_w = ud_reg_to_w(dst);
1200
1201 /* Give each 32-bit channel of dst the form below , where "." means
1202 * unchanged.
1203 * 0x....hhhh
1204 */
1205 brw_F32TO16(p, dst_w, y);
1206
1207 /* Now the form:
1208 * 0xhhhh0000
1209 */
1210 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1211
1212 /* And, finally the form of packHalf2x16's output:
1213 * 0xhhhhllll
1214 */
1215 brw_F32TO16(p, dst_w, x);
1216 }
1217
1218 void
1219 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1220 struct brw_reg dst,
1221 struct brw_reg src)
1222 {
1223 assert(brw->gen >= 7);
1224 assert(dst.type == BRW_REGISTER_TYPE_F);
1225 assert(src.type == BRW_REGISTER_TYPE_UD);
1226
1227 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1228 *
1229 * Because this instruction does not have a 16-bit floating-point type,
1230 * the source data type must be Word (W). The destination type must be
1231 * F (Float).
1232 */
1233 struct brw_reg src_w = ud_reg_to_w(src);
1234
1235 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1236 * For the Y case, we wish to access only the upper word; therefore
1237 * a 16-bit subregister offset is needed.
1238 */
1239 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1240 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1241 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1242 src_w.subnr += 2;
1243
1244 brw_F16TO32(p, dst, src_w);
1245 }
1246
1247 void
1248 fs_generator::generate_shader_time_add(fs_inst *inst,
1249 struct brw_reg payload,
1250 struct brw_reg offset,
1251 struct brw_reg value)
1252 {
1253 assert(brw->gen >= 7);
1254 brw_push_insn_state(p);
1255 brw_set_default_mask_control(p, true);
1256
1257 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1258 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1259 offset.type);
1260 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1261 value.type);
1262
1263 assert(offset.file == BRW_IMMEDIATE_VALUE);
1264 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1265 value.width = BRW_WIDTH_1;
1266 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1267 value.vstride = BRW_VERTICAL_STRIDE_0;
1268 } else {
1269 assert(value.file == BRW_IMMEDIATE_VALUE);
1270 }
1271
1272 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1273 * case, and we don't really care about squeezing every bit of performance
1274 * out of this path, so we just emit the MOVs from here.
1275 */
1276 brw_MOV(p, payload_offset, offset);
1277 brw_MOV(p, payload_value, value);
1278 brw_shader_time_add(p, payload,
1279 prog_data->base.binding_table.shader_time_start);
1280 brw_pop_insn_state(p);
1281
1282 brw_mark_surface_used(&prog_data->base,
1283 prog_data->base.binding_table.shader_time_start);
1284 }
1285
1286 void
1287 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1288 struct brw_reg atomic_op,
1289 struct brw_reg surf_index)
1290 {
1291 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1292 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1293 surf_index.file == BRW_IMMEDIATE_VALUE &&
1294 surf_index.type == BRW_REGISTER_TYPE_UD);
1295
1296 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1297 atomic_op.dw1.ud, surf_index.dw1.ud,
1298 inst->mlen, dispatch_width / 8);
1299
1300 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1301 }
1302
1303 void
1304 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1305 struct brw_reg surf_index)
1306 {
1307 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1308 surf_index.type == BRW_REGISTER_TYPE_UD);
1309
1310 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1311 surf_index.dw1.ud,
1312 inst->mlen, dispatch_width / 8);
1313
1314 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1315 }
1316
1317 void
1318 fs_generator::generate_code(exec_list *instructions)
1319 {
1320 int start_offset = p->next_insn_offset;
1321
1322 struct annotation_info annotation;
1323 memset(&annotation, 0, sizeof(annotation));
1324
1325 cfg_t *cfg = NULL;
1326 if (unlikely(debug_flag))
1327 cfg = new(mem_ctx) cfg_t(instructions);
1328
1329 foreach_list(node, instructions) {
1330 fs_inst *inst = (fs_inst *)node;
1331 struct brw_reg src[3], dst;
1332 unsigned int last_insn_offset = p->next_insn_offset;
1333
1334 if (unlikely(debug_flag))
1335 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1336
1337 for (unsigned int i = 0; i < inst->sources; i++) {
1338 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1339
1340 /* The accumulator result appears to get used for the
1341 * conditional modifier generation. When negating a UD
1342 * value, there is a 33rd bit generated for the sign in the
1343 * accumulator value, so now you can't check, for example,
1344 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1345 */
1346 assert(!inst->conditional_mod ||
1347 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1348 !inst->src[i].negate);
1349 }
1350 dst = brw_reg_from_fs_reg(&inst->dst);
1351
1352 brw_set_default_predicate_control(p, inst->predicate);
1353 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1354 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1355 brw_set_default_saturate(p, inst->saturate);
1356 brw_set_default_mask_control(p, inst->force_writemask_all);
1357 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1358
1359 if (inst->force_uncompressed || dispatch_width == 8) {
1360 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1361 } else if (inst->force_sechalf) {
1362 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1363 } else {
1364 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1365 }
1366
1367 switch (inst->opcode) {
1368 case BRW_OPCODE_MOV:
1369 brw_MOV(p, dst, src[0]);
1370 break;
1371 case BRW_OPCODE_ADD:
1372 brw_ADD(p, dst, src[0], src[1]);
1373 break;
1374 case BRW_OPCODE_MUL:
1375 brw_MUL(p, dst, src[0], src[1]);
1376 break;
1377 case BRW_OPCODE_AVG:
1378 brw_AVG(p, dst, src[0], src[1]);
1379 break;
1380 case BRW_OPCODE_MACH:
1381 brw_MACH(p, dst, src[0], src[1]);
1382 break;
1383
1384 case BRW_OPCODE_MAD:
1385 assert(brw->gen >= 6);
1386 brw_set_default_access_mode(p, BRW_ALIGN_16);
1387 if (dispatch_width == 16 && !brw->is_haswell) {
1388 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1389 brw_MAD(p, dst, src[0], src[1], src[2]);
1390 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1391 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1392 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1393 } else {
1394 brw_MAD(p, dst, src[0], src[1], src[2]);
1395 }
1396 brw_set_default_access_mode(p, BRW_ALIGN_1);
1397 break;
1398
1399 case BRW_OPCODE_LRP:
1400 assert(brw->gen >= 6);
1401 brw_set_default_access_mode(p, BRW_ALIGN_16);
1402 if (dispatch_width == 16 && !brw->is_haswell) {
1403 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1404 brw_LRP(p, dst, src[0], src[1], src[2]);
1405 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1406 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1407 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1408 } else {
1409 brw_LRP(p, dst, src[0], src[1], src[2]);
1410 }
1411 brw_set_default_access_mode(p, BRW_ALIGN_1);
1412 break;
1413
1414 case BRW_OPCODE_FRC:
1415 brw_FRC(p, dst, src[0]);
1416 break;
1417 case BRW_OPCODE_RNDD:
1418 brw_RNDD(p, dst, src[0]);
1419 break;
1420 case BRW_OPCODE_RNDE:
1421 brw_RNDE(p, dst, src[0]);
1422 break;
1423 case BRW_OPCODE_RNDZ:
1424 brw_RNDZ(p, dst, src[0]);
1425 break;
1426
1427 case BRW_OPCODE_AND:
1428 brw_AND(p, dst, src[0], src[1]);
1429 break;
1430 case BRW_OPCODE_OR:
1431 brw_OR(p, dst, src[0], src[1]);
1432 break;
1433 case BRW_OPCODE_XOR:
1434 brw_XOR(p, dst, src[0], src[1]);
1435 break;
1436 case BRW_OPCODE_NOT:
1437 brw_NOT(p, dst, src[0]);
1438 break;
1439 case BRW_OPCODE_ASR:
1440 brw_ASR(p, dst, src[0], src[1]);
1441 break;
1442 case BRW_OPCODE_SHR:
1443 brw_SHR(p, dst, src[0], src[1]);
1444 break;
1445 case BRW_OPCODE_SHL:
1446 brw_SHL(p, dst, src[0], src[1]);
1447 break;
1448 case BRW_OPCODE_F32TO16:
1449 assert(brw->gen >= 7);
1450 brw_F32TO16(p, dst, src[0]);
1451 break;
1452 case BRW_OPCODE_F16TO32:
1453 assert(brw->gen >= 7);
1454 brw_F16TO32(p, dst, src[0]);
1455 break;
1456 case BRW_OPCODE_CMP:
1457 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1458 break;
1459 case BRW_OPCODE_SEL:
1460 brw_SEL(p, dst, src[0], src[1]);
1461 break;
1462 case BRW_OPCODE_BFREV:
1463 assert(brw->gen >= 7);
1464 /* BFREV only supports UD type for src and dst. */
1465 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1466 retype(src[0], BRW_REGISTER_TYPE_UD));
1467 break;
1468 case BRW_OPCODE_FBH:
1469 assert(brw->gen >= 7);
1470 /* FBH only supports UD type for dst. */
1471 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1472 break;
1473 case BRW_OPCODE_FBL:
1474 assert(brw->gen >= 7);
1475 /* FBL only supports UD type for dst. */
1476 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1477 break;
1478 case BRW_OPCODE_CBIT:
1479 assert(brw->gen >= 7);
1480 /* CBIT only supports UD type for dst. */
1481 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1482 break;
1483 case BRW_OPCODE_ADDC:
1484 assert(brw->gen >= 7);
1485 brw_ADDC(p, dst, src[0], src[1]);
1486 break;
1487 case BRW_OPCODE_SUBB:
1488 assert(brw->gen >= 7);
1489 brw_SUBB(p, dst, src[0], src[1]);
1490 break;
1491 case BRW_OPCODE_MAC:
1492 brw_MAC(p, dst, src[0], src[1]);
1493 break;
1494
1495 case BRW_OPCODE_BFE:
1496 assert(brw->gen >= 7);
1497 brw_set_default_access_mode(p, BRW_ALIGN_16);
1498 if (dispatch_width == 16 && !brw->is_haswell) {
1499 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1500 brw_BFE(p, dst, src[0], src[1], src[2]);
1501 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1502 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1503 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1504 } else {
1505 brw_BFE(p, dst, src[0], src[1], src[2]);
1506 }
1507 brw_set_default_access_mode(p, BRW_ALIGN_1);
1508 break;
1509
1510 case BRW_OPCODE_BFI1:
1511 assert(brw->gen >= 7);
1512 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1513 * should
1514 *
1515 * "Force BFI instructions to be executed always in SIMD8."
1516 */
1517 if (dispatch_width == 16 && brw->is_haswell) {
1518 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1519 brw_BFI1(p, dst, src[0], src[1]);
1520 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1521 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1522 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1523 } else {
1524 brw_BFI1(p, dst, src[0], src[1]);
1525 }
1526 break;
1527 case BRW_OPCODE_BFI2:
1528 assert(brw->gen >= 7);
1529 brw_set_default_access_mode(p, BRW_ALIGN_16);
1530 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1531 * should
1532 *
1533 * "Force BFI instructions to be executed always in SIMD8."
1534 *
1535 * Otherwise we would be able to emit compressed instructions like we
1536 * do for the other three-source instructions.
1537 */
1538 if (dispatch_width == 16) {
1539 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1540 brw_BFI2(p, dst, src[0], src[1], src[2]);
1541 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1542 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1543 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1544 } else {
1545 brw_BFI2(p, dst, src[0], src[1], src[2]);
1546 }
1547 brw_set_default_access_mode(p, BRW_ALIGN_1);
1548 break;
1549
1550 case BRW_OPCODE_IF:
1551 if (inst->src[0].file != BAD_FILE) {
1552 /* The instruction has an embedded compare (only allowed on gen6) */
1553 assert(brw->gen == 6);
1554 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1555 } else {
1556 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1557 }
1558 break;
1559
1560 case BRW_OPCODE_ELSE:
1561 brw_ELSE(p);
1562 break;
1563 case BRW_OPCODE_ENDIF:
1564 brw_ENDIF(p);
1565 break;
1566
1567 case BRW_OPCODE_DO:
1568 brw_DO(p, BRW_EXECUTE_8);
1569 break;
1570
1571 case BRW_OPCODE_BREAK:
1572 brw_BREAK(p);
1573 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1574 break;
1575 case BRW_OPCODE_CONTINUE:
1576 /* FINISHME: We need to write the loop instruction support still. */
1577 if (brw->gen >= 6)
1578 gen6_CONT(p);
1579 else
1580 brw_CONT(p);
1581 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1582 break;
1583
1584 case BRW_OPCODE_WHILE:
1585 brw_WHILE(p);
1586 break;
1587
1588 case SHADER_OPCODE_RCP:
1589 case SHADER_OPCODE_RSQ:
1590 case SHADER_OPCODE_SQRT:
1591 case SHADER_OPCODE_EXP2:
1592 case SHADER_OPCODE_LOG2:
1593 case SHADER_OPCODE_SIN:
1594 case SHADER_OPCODE_COS:
1595 assert(brw->gen < 6 || inst->mlen == 0);
1596 if (brw->gen >= 7) {
1597 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1598 brw_null_reg());
1599 } else if (brw->gen == 6) {
1600 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1601 } else if (brw->gen == 5 || brw->is_g4x) {
1602 generate_math_g45(inst, dst, src[0]);
1603 } else {
1604 generate_math_gen4(inst, dst, src[0]);
1605 }
1606 break;
1607 case SHADER_OPCODE_INT_QUOTIENT:
1608 case SHADER_OPCODE_INT_REMAINDER:
1609 case SHADER_OPCODE_POW:
1610 assert(brw->gen < 6 || inst->mlen == 0);
1611 if (brw->gen >= 7) {
1612 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1613 } else if (brw->gen == 6) {
1614 generate_math_gen6(inst, dst, src[0], src[1]);
1615 } else {
1616 generate_math_gen4(inst, dst, src[0]);
1617 }
1618 break;
1619 case FS_OPCODE_PIXEL_X:
1620 generate_pixel_xy(dst, true);
1621 break;
1622 case FS_OPCODE_PIXEL_Y:
1623 generate_pixel_xy(dst, false);
1624 break;
1625 case FS_OPCODE_CINTERP:
1626 brw_MOV(p, dst, src[0]);
1627 break;
1628 case FS_OPCODE_LINTERP:
1629 generate_linterp(inst, dst, src);
1630 break;
1631 case SHADER_OPCODE_TEX:
1632 case FS_OPCODE_TXB:
1633 case SHADER_OPCODE_TXD:
1634 case SHADER_OPCODE_TXF:
1635 case SHADER_OPCODE_TXF_CMS:
1636 case SHADER_OPCODE_TXF_UMS:
1637 case SHADER_OPCODE_TXF_MCS:
1638 case SHADER_OPCODE_TXL:
1639 case SHADER_OPCODE_TXS:
1640 case SHADER_OPCODE_LOD:
1641 case SHADER_OPCODE_TG4:
1642 case SHADER_OPCODE_TG4_OFFSET:
1643 generate_tex(inst, dst, src[0]);
1644 break;
1645 case FS_OPCODE_DDX:
1646 generate_ddx(inst, dst, src[0]);
1647 break;
1648 case FS_OPCODE_DDY:
1649 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1650 * guarantee that key->render_to_fbo is set).
1651 */
1652 assert(fp->UsesDFdy);
1653 generate_ddy(inst, dst, src[0], key->render_to_fbo);
1654 break;
1655
1656 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1657 generate_scratch_write(inst, src[0]);
1658 break;
1659
1660 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1661 generate_scratch_read(inst, dst);
1662 break;
1663
1664 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1665 generate_scratch_read_gen7(inst, dst);
1666 break;
1667
1668 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1669 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1670 break;
1671
1672 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1673 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1674 break;
1675
1676 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1677 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1678 break;
1679
1680 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1681 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1682 break;
1683
1684 case FS_OPCODE_FB_WRITE:
1685 generate_fb_write(inst);
1686 break;
1687
1688 case FS_OPCODE_BLORP_FB_WRITE:
1689 generate_blorp_fb_write(inst);
1690 break;
1691
1692 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1693 generate_mov_dispatch_to_flags(inst);
1694 break;
1695
1696 case FS_OPCODE_DISCARD_JUMP:
1697 generate_discard_jump(inst);
1698 break;
1699
1700 case SHADER_OPCODE_SHADER_TIME_ADD:
1701 generate_shader_time_add(inst, src[0], src[1], src[2]);
1702 break;
1703
1704 case SHADER_OPCODE_UNTYPED_ATOMIC:
1705 generate_untyped_atomic(inst, dst, src[0], src[1]);
1706 break;
1707
1708 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1709 generate_untyped_surface_read(inst, dst, src[0]);
1710 break;
1711
1712 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1713 generate_set_simd4x2_offset(inst, dst, src[0]);
1714 break;
1715
1716 case FS_OPCODE_SET_OMASK:
1717 generate_set_omask(inst, dst, src[0]);
1718 break;
1719
1720 case FS_OPCODE_SET_SAMPLE_ID:
1721 generate_set_sample_id(inst, dst, src[0], src[1]);
1722 break;
1723
1724 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1725 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1726 break;
1727
1728 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1729 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1730 generate_unpack_half_2x16_split(inst, dst, src[0]);
1731 break;
1732
1733 case FS_OPCODE_PLACEHOLDER_HALT:
1734 /* This is the place where the final HALT needs to be inserted if
1735 * we've emitted any discards. If not, this will emit no code.
1736 */
1737 if (!patch_discard_jumps_to_fb_writes()) {
1738 if (unlikely(debug_flag)) {
1739 annotation.ann_count--;
1740 }
1741 }
1742 break;
1743
1744 default:
1745 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1746 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1747 opcode_descs[inst->opcode].name);
1748 } else {
1749 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1750 }
1751 abort();
1752 }
1753
1754 if (inst->conditional_mod) {
1755 /* Set the conditional modifier on the last instruction we generated.
1756 * Also, make sure we only emitted one instruction - anything else
1757 * doesn't make sense.
1758 */
1759 assert(p->next_insn_offset == last_insn_offset + 16);
1760 struct brw_instruction *last = &p->store[last_insn_offset / 16];
1761 last->header.destreg__conditionalmod = inst->conditional_mod;
1762 }
1763 }
1764
1765 brw_set_uip_jip(p);
1766 annotation_finalize(&annotation, p->next_insn_offset);
1767
1768 int before_size = p->next_insn_offset - start_offset;
1769 brw_compact_instructions(p, start_offset, annotation.ann_count,
1770 annotation.ann);
1771 int after_size = p->next_insn_offset - start_offset;
1772
1773 if (unlikely(debug_flag)) {
1774 if (prog) {
1775 fprintf(stderr,
1776 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
1777 prog->Label ? prog->Label : "unnamed",
1778 prog->Name, dispatch_width);
1779 } else if (fp) {
1780 fprintf(stderr,
1781 "Native code for fragment program %d (SIMD%d dispatch):\n",
1782 fp->Base.Id, dispatch_width);
1783 } else {
1784 fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
1785 dispatch_width);
1786 }
1787 fprintf(stderr, "SIMD%d shader: %d instructions. Compacted %d to %d"
1788 " bytes (%.0f%%)\n",
1789 dispatch_width, before_size / 16, before_size, after_size,
1790 100.0f * (before_size - after_size) / before_size);
1791
1792 const struct gl_program *prog = fp ? &fp->Base : NULL;
1793
1794 dump_assembly(p->store, annotation.ann_count, annotation.ann,
1795 brw, prog, brw_disassemble);
1796 ralloc_free(annotation.ann);
1797 }
1798 }
1799
1800 const unsigned *
1801 fs_generator::generate_assembly(exec_list *simd8_instructions,
1802 exec_list *simd16_instructions,
1803 unsigned *assembly_size)
1804 {
1805 assert(simd8_instructions || simd16_instructions);
1806
1807 if (simd8_instructions) {
1808 dispatch_width = 8;
1809 generate_code(simd8_instructions);
1810 }
1811
1812 if (simd16_instructions) {
1813 /* align to 64 byte boundary. */
1814 while (p->next_insn_offset % 64) {
1815 brw_NOP(p);
1816 }
1817
1818 /* Save off the start of this SIMD16 program */
1819 prog_data->prog_offset_16 = p->next_insn_offset;
1820
1821 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1822
1823 dispatch_width = 16;
1824 generate_code(simd16_instructions);
1825 }
1826
1827 return brw_get_program(p, assembly_size);
1828 }