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mesa/i965/i915/r200: eliminate gl_vertex_program
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "brw_eu.h"
31 #include "brw_fs.h"
32 #include "brw_cfg.h"
33 #include "brw_program.h"
34
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case ARF:
40 return BRW_ARCHITECTURE_REGISTER_FILE;
41 case FIXED_GRF:
42 case VGRF:
43 return BRW_GENERAL_REGISTER_FILE;
44 case MRF:
45 return BRW_MESSAGE_REGISTER_FILE;
46 case IMM:
47 return BRW_IMMEDIATE_VALUE;
48 case BAD_FILE:
49 case ATTR:
50 case UNIFORM:
51 unreachable("not reached");
52 }
53 return BRW_ARCHITECTURE_REGISTER_FILE;
54 }
55
56 static struct brw_reg
57 brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen, bool compressed)
58 {
59 struct brw_reg brw_reg;
60
61 switch (reg->file) {
62 case MRF:
63 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(gen));
64 /* Fallthrough */
65 case VGRF:
66 if (reg->stride == 0) {
67 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
68 } else {
69 /* From the Haswell PRM:
70 *
71 * "VertStride must be used to cross GRF register boundaries. This
72 * rule implies that elements within a 'Width' cannot cross GRF
73 * boundaries."
74 *
75 * The maximum width value that could satisfy this restriction is:
76 */
77 const unsigned reg_width = REG_SIZE / (reg->stride * type_sz(reg->type));
78
79 /* Because the hardware can only split source regions at a whole
80 * multiple of width during decompression (i.e. vertically), clamp
81 * the value obtained above to the physical execution size of a
82 * single decompressed chunk of the instruction:
83 */
84 const unsigned phys_width = compressed ? inst->exec_size / 2 :
85 inst->exec_size;
86
87 /* XXX - The equation above is strictly speaking not correct on
88 * hardware that supports unbalanced GRF writes -- On Gen9+
89 * each decompressed chunk of the instruction may have a
90 * different execution size when the number of components
91 * written to each destination GRF is not the same.
92 */
93 const unsigned width = MIN2(reg_width, phys_width);
94 brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
95 brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
96 }
97
98 brw_reg = retype(brw_reg, reg->type);
99 brw_reg = byte_offset(brw_reg, reg->offset);
100 brw_reg.abs = reg->abs;
101 brw_reg.negate = reg->negate;
102 break;
103 case ARF:
104 case FIXED_GRF:
105 case IMM:
106 assert(reg->offset == 0);
107 brw_reg = reg->as_brw_reg();
108 break;
109 case BAD_FILE:
110 /* Probably unused. */
111 brw_reg = brw_null_reg();
112 break;
113 case ATTR:
114 case UNIFORM:
115 unreachable("not reached");
116 }
117
118 return brw_reg;
119 }
120
121 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
122 void *mem_ctx,
123 const void *key,
124 struct brw_stage_prog_data *prog_data,
125 unsigned promoted_constants,
126 bool runtime_check_aads_emit,
127 gl_shader_stage stage)
128
129 : compiler(compiler), log_data(log_data),
130 devinfo(compiler->devinfo), key(key),
131 prog_data(prog_data),
132 promoted_constants(promoted_constants),
133 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
134 stage(stage), mem_ctx(mem_ctx)
135 {
136 p = rzalloc(mem_ctx, struct brw_codegen);
137 brw_init_codegen(devinfo, p, mem_ctx);
138 }
139
140 fs_generator::~fs_generator()
141 {
142 }
143
144 class ip_record : public exec_node {
145 public:
146 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
147
148 ip_record(int ip)
149 {
150 this->ip = ip;
151 }
152
153 int ip;
154 };
155
156 bool
157 fs_generator::patch_discard_jumps_to_fb_writes()
158 {
159 if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
160 return false;
161
162 int scale = brw_jump_scale(p->devinfo);
163
164 /* There is a somewhat strange undocumented requirement of using
165 * HALT, according to the simulator. If some channel has HALTed to
166 * a particular UIP, then by the end of the program, every channel
167 * must have HALTed to that UIP. Furthermore, the tracking is a
168 * stack, so you can't do the final halt of a UIP after starting
169 * halting to a new UIP.
170 *
171 * Symptoms of not emitting this instruction on actual hardware
172 * included GPU hangs and sparkly rendering on the piglit discard
173 * tests.
174 */
175 brw_inst *last_halt = gen6_HALT(p);
176 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
177 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
178
179 int ip = p->nr_insn;
180
181 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
182 brw_inst *patch = &p->store[patch_ip->ip];
183
184 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
185 /* HALT takes a half-instruction distance from the pre-incremented IP. */
186 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
187 }
188
189 this->discard_halt_patches.make_empty();
190 return true;
191 }
192
193 void
194 fs_generator::fire_fb_write(fs_inst *inst,
195 struct brw_reg payload,
196 struct brw_reg implied_header,
197 GLuint nr)
198 {
199 uint32_t msg_control;
200
201 struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
202
203 if (devinfo->gen < 6) {
204 brw_push_insn_state(p);
205 brw_set_default_exec_size(p, BRW_EXECUTE_8);
206 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
207 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
208 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
209 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
210 brw_pop_insn_state(p);
211 }
212
213 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
214 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
215 else if (prog_data->dual_src_blend) {
216 if (!inst->group)
217 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
218 else
219 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
220 } else if (inst->exec_size == 16)
221 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
222 else
223 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
224
225 uint32_t surf_index =
226 prog_data->binding_table.render_target_start + inst->target;
227
228 bool last_render_target = inst->eot ||
229 (prog_data->dual_src_blend && dispatch_width == 16);
230
231
232 brw_fb_WRITE(p,
233 payload,
234 implied_header,
235 msg_control,
236 surf_index,
237 nr,
238 0,
239 inst->eot,
240 last_render_target,
241 inst->header_size != 0);
242
243 brw_mark_surface_used(&prog_data->base, surf_index);
244 }
245
246 void
247 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
248 {
249 struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
250 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
251 struct brw_reg implied_header;
252
253 if (devinfo->gen < 8 && !devinfo->is_haswell) {
254 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
255 }
256
257 if (inst->base_mrf >= 0)
258 payload = brw_message_reg(inst->base_mrf);
259
260 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
261 * move, here's g1.
262 */
263 if (inst->header_size != 0) {
264 brw_push_insn_state(p);
265 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
266 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
267 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
268 brw_set_default_flag_reg(p, 0, 0);
269
270 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
271 * present.
272 */
273 if (prog_data->uses_kill) {
274 struct brw_reg pixel_mask;
275
276 if (devinfo->gen >= 6)
277 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
278 else
279 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
280
281 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
282 }
283
284 if (devinfo->gen >= 6) {
285 brw_push_insn_state(p);
286 brw_set_default_exec_size(p, BRW_EXECUTE_16);
287 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
288 brw_MOV(p,
289 retype(payload, BRW_REGISTER_TYPE_UD),
290 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
291 brw_pop_insn_state(p);
292
293 if (inst->target > 0 && key->replicate_alpha) {
294 /* Set "Source0 Alpha Present to RenderTarget" bit in message
295 * header.
296 */
297 brw_OR(p,
298 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
299 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
300 brw_imm_ud(0x1 << 11));
301 }
302
303 if (inst->target > 0) {
304 /* Set the render target index for choosing BLEND_STATE. */
305 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
306 BRW_REGISTER_TYPE_UD),
307 brw_imm_ud(inst->target));
308 }
309
310 /* Set computes stencil to render target */
311 if (prog_data->computed_stencil) {
312 brw_OR(p,
313 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
314 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
315 brw_imm_ud(0x1 << 14));
316 }
317
318 implied_header = brw_null_reg();
319 } else {
320 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
321 }
322
323 brw_pop_insn_state(p);
324 } else {
325 implied_header = brw_null_reg();
326 }
327
328 if (!runtime_check_aads_emit) {
329 fire_fb_write(inst, payload, implied_header, inst->mlen);
330 } else {
331 /* This can only happen in gen < 6 */
332 assert(devinfo->gen < 6);
333
334 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
335
336 /* Check runtime bit to detect if we have to send AA data or not */
337 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
338 brw_AND(p,
339 v1_null_ud,
340 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
341 brw_imm_ud(1<<26));
342 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
343
344 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
345 brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
346 {
347 /* Don't send AA data */
348 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
349 }
350 brw_land_fwd_jump(p, jmp);
351 fire_fb_write(inst, payload, implied_header, inst->mlen);
352 }
353 }
354
355 void
356 fs_generator::generate_fb_read(fs_inst *inst, struct brw_reg dst,
357 struct brw_reg payload)
358 {
359 assert(inst->size_written % REG_SIZE == 0);
360 struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
361 const unsigned surf_index =
362 prog_data->binding_table.render_target_start + inst->target;
363
364 gen9_fb_READ(p, dst, payload, surf_index,
365 inst->header_size, inst->size_written / REG_SIZE,
366 prog_data->persample_dispatch);
367
368 brw_mark_surface_used(&prog_data->base, surf_index);
369 }
370
371 void
372 fs_generator::generate_mov_indirect(fs_inst *inst,
373 struct brw_reg dst,
374 struct brw_reg reg,
375 struct brw_reg indirect_byte_offset)
376 {
377 assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD);
378 assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE);
379
380 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
381
382 if (indirect_byte_offset.file == BRW_IMMEDIATE_VALUE) {
383 imm_byte_offset += indirect_byte_offset.ud;
384
385 reg.nr = imm_byte_offset / REG_SIZE;
386 reg.subnr = imm_byte_offset % REG_SIZE;
387 brw_MOV(p, dst, reg);
388 } else {
389 /* Prior to Broadwell, there are only 8 address registers. */
390 assert(inst->exec_size == 8 || devinfo->gen >= 8);
391
392 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
393 struct brw_reg addr = vec8(brw_address_reg(0));
394
395 /* The destination stride of an instruction (in bytes) must be greater
396 * than or equal to the size of the rest of the instruction. Since the
397 * address register is of type UW, we can't use a D-type instruction.
398 * In order to get around this, re retype to UW and use a stride.
399 */
400 indirect_byte_offset =
401 retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);
402
403 struct brw_reg ind_src;
404 if (devinfo->gen < 8) {
405 /* From the Haswell PRM section "Register Region Restrictions":
406 *
407 * "The lower bits of the AddressImmediate must not overflow to
408 * change the register address. The lower 5 bits of Address
409 * Immediate when added to lower 5 bits of address register gives
410 * the sub-register offset. The upper bits of Address Immediate
411 * when added to upper bits of address register gives the register
412 * address. Any overflow from sub-register offset is dropped."
413 *
414 * This restriction is only listed in the Haswell PRM but emperical
415 * testing indicates that it applies on all older generations and is
416 * lifted on Broadwell.
417 *
418 * Since the indirect may cause us to cross a register boundary, this
419 * makes the base offset almost useless. We could try and do
420 * something clever where we use a actual base offset if
421 * base_offset % 32 == 0 but that would mean we were generating
422 * different code depending on the base offset. Instead, for the
423 * sake of consistency, we'll just do the add ourselves.
424 */
425 brw_ADD(p, addr, indirect_byte_offset, brw_imm_uw(imm_byte_offset));
426 ind_src = brw_VxH_indirect(0, 0);
427 } else {
428 brw_MOV(p, addr, indirect_byte_offset);
429 ind_src = brw_VxH_indirect(0, imm_byte_offset);
430 }
431
432 brw_inst *mov = brw_MOV(p, dst, retype(ind_src, dst.type));
433
434 if (devinfo->gen == 6 && dst.file == BRW_MESSAGE_REGISTER_FILE &&
435 !inst->get_next()->is_tail_sentinel() &&
436 ((fs_inst *)inst->get_next())->mlen > 0) {
437 /* From the Sandybridge PRM:
438 *
439 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
440 * instruction that “indexed/indirect” source AND is followed by a
441 * send, the instruction requires a “Switch”. This is to avoid
442 * race condition where send may dispatch before MRF is updated."
443 */
444 brw_inst_set_thread_control(devinfo, mov, BRW_THREAD_SWITCH);
445 }
446 }
447 }
448
449 void
450 fs_generator::generate_urb_read(fs_inst *inst,
451 struct brw_reg dst,
452 struct brw_reg header)
453 {
454 assert(inst->size_written % REG_SIZE == 0);
455 assert(header.file == BRW_GENERAL_REGISTER_FILE);
456 assert(header.type == BRW_REGISTER_TYPE_UD);
457
458 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
459 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UD));
460 brw_set_src0(p, send, header);
461 brw_set_src1(p, send, brw_imm_ud(0u));
462
463 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
464 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
465
466 if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
467 brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
468
469 brw_inst_set_mlen(p->devinfo, send, inst->mlen);
470 brw_inst_set_rlen(p->devinfo, send, inst->size_written / REG_SIZE);
471 brw_inst_set_header_present(p->devinfo, send, true);
472 brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
473 }
474
475 void
476 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
477 {
478 brw_inst *insn;
479
480 insn = brw_next_insn(p, BRW_OPCODE_SEND);
481
482 brw_set_dest(p, insn, brw_null_reg());
483 brw_set_src0(p, insn, payload);
484 brw_set_src1(p, insn, brw_imm_d(0));
485
486 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
487 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
488
489 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
490 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
491 brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
492
493 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
494 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
495 brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
496
497 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
498 brw_inst_set_rlen(p->devinfo, insn, 0);
499 brw_inst_set_eot(p->devinfo, insn, inst->eot);
500 brw_inst_set_header_present(p->devinfo, insn, true);
501 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
502 }
503
504 void
505 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
506 {
507 struct brw_inst *insn;
508
509 insn = brw_next_insn(p, BRW_OPCODE_SEND);
510
511 brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW));
512 brw_set_src0(p, insn, payload);
513 brw_set_src1(p, insn, brw_imm_d(0));
514
515 /* Terminate a compute shader by sending a message to the thread spawner.
516 */
517 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
518 brw_inst_set_mlen(devinfo, insn, 1);
519 brw_inst_set_rlen(devinfo, insn, 0);
520 brw_inst_set_eot(devinfo, insn, inst->eot);
521 brw_inst_set_header_present(devinfo, insn, false);
522
523 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
524 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
525
526 /* Note that even though the thread has a URB resource associated with it,
527 * we set the "do not dereference URB" bit, because the URB resource is
528 * managed by the fixed-function unit, so it will free it automatically.
529 */
530 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
531
532 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
533 }
534
535 void
536 fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
537 {
538 brw_barrier(p, src);
539 brw_WAIT(p);
540 }
541
542 void
543 fs_generator::generate_linterp(fs_inst *inst,
544 struct brw_reg dst, struct brw_reg *src)
545 {
546 /* PLN reads:
547 * / in SIMD16 \
548 * -----------------------------------
549 * | src1+0 | src1+1 | src1+2 | src1+3 |
550 * |-----------------------------------|
551 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
552 * -----------------------------------
553 *
554 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
555 *
556 * -----------------------------------
557 * | src1+0 | src1+1 | src1+2 | src1+3 |
558 * |-----------------------------------|
559 * |(x0, x1)|(y0, y1)| | | in SIMD8
560 * |-----------------------------------|
561 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
562 * -----------------------------------
563 *
564 * See also: emit_interpolation_setup_gen4().
565 */
566 struct brw_reg delta_x = src[0];
567 struct brw_reg delta_y = offset(src[0], inst->exec_size / 8);
568 struct brw_reg interp = src[1];
569
570 if (devinfo->has_pln &&
571 (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
572 brw_PLN(p, dst, interp, delta_x);
573 } else {
574 brw_LINE(p, brw_null_reg(), interp, delta_x);
575 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
576 }
577 }
578
579 void
580 fs_generator::generate_get_buffer_size(fs_inst *inst,
581 struct brw_reg dst,
582 struct brw_reg src,
583 struct brw_reg surf_index)
584 {
585 assert(devinfo->gen >= 7);
586 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
587
588 uint32_t simd_mode;
589 int rlen = 4;
590
591 switch (inst->exec_size) {
592 case 8:
593 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
594 break;
595 case 16:
596 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
597 break;
598 default:
599 unreachable("Invalid width for texture instruction");
600 }
601
602 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
603 rlen = 8;
604 dst = vec16(dst);
605 }
606
607 brw_SAMPLE(p,
608 retype(dst, BRW_REGISTER_TYPE_UW),
609 inst->base_mrf,
610 src,
611 surf_index.ud,
612 0,
613 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
614 rlen, /* response length */
615 inst->mlen,
616 inst->header_size > 0,
617 simd_mode,
618 BRW_SAMPLER_RETURN_FORMAT_SINT32);
619
620 brw_mark_surface_used(prog_data, surf_index.ud);
621 }
622
623 void
624 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
625 struct brw_reg surface_index,
626 struct brw_reg sampler_index)
627 {
628 assert(inst->size_written % REG_SIZE == 0);
629 int msg_type = -1;
630 uint32_t simd_mode;
631 uint32_t return_format;
632 bool is_combined_send = inst->eot;
633
634 switch (dst.type) {
635 case BRW_REGISTER_TYPE_D:
636 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
637 break;
638 case BRW_REGISTER_TYPE_UD:
639 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
640 break;
641 default:
642 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
643 break;
644 }
645
646 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
647 * is set as part of the message descriptor. On gen4, the PRM seems to
648 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
649 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
650 * gone from the message descriptor entirely and you just get UINT32 all
651 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
652 * just stomp it to UINT32 all the time.
653 */
654 if (inst->opcode == SHADER_OPCODE_TXS)
655 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
656
657 switch (inst->exec_size) {
658 case 8:
659 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
660 break;
661 case 16:
662 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
663 break;
664 default:
665 unreachable("Invalid width for texture instruction");
666 }
667
668 if (devinfo->gen >= 5) {
669 switch (inst->opcode) {
670 case SHADER_OPCODE_TEX:
671 if (inst->shadow_compare) {
672 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
673 } else {
674 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
675 }
676 break;
677 case FS_OPCODE_TXB:
678 if (inst->shadow_compare) {
679 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
680 } else {
681 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
682 }
683 break;
684 case SHADER_OPCODE_TXL:
685 if (inst->shadow_compare) {
686 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
687 } else {
688 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
689 }
690 break;
691 case SHADER_OPCODE_TXL_LZ:
692 assert(devinfo->gen >= 9);
693 if (inst->shadow_compare) {
694 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ;
695 } else {
696 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LZ;
697 }
698 break;
699 case SHADER_OPCODE_TXS:
700 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
701 break;
702 case SHADER_OPCODE_TXD:
703 if (inst->shadow_compare) {
704 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
705 assert(devinfo->gen >= 8 || devinfo->is_haswell);
706 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
707 } else {
708 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
709 }
710 break;
711 case SHADER_OPCODE_TXF:
712 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
713 break;
714 case SHADER_OPCODE_TXF_LZ:
715 assert(devinfo->gen >= 9);
716 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ;
717 break;
718 case SHADER_OPCODE_TXF_CMS_W:
719 assert(devinfo->gen >= 9);
720 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
721 break;
722 case SHADER_OPCODE_TXF_CMS:
723 if (devinfo->gen >= 7)
724 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
725 else
726 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
727 break;
728 case SHADER_OPCODE_TXF_UMS:
729 assert(devinfo->gen >= 7);
730 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
731 break;
732 case SHADER_OPCODE_TXF_MCS:
733 assert(devinfo->gen >= 7);
734 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
735 break;
736 case SHADER_OPCODE_LOD:
737 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
738 break;
739 case SHADER_OPCODE_TG4:
740 if (inst->shadow_compare) {
741 assert(devinfo->gen >= 7);
742 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
743 } else {
744 assert(devinfo->gen >= 6);
745 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
746 }
747 break;
748 case SHADER_OPCODE_TG4_OFFSET:
749 assert(devinfo->gen >= 7);
750 if (inst->shadow_compare) {
751 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
752 } else {
753 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
754 }
755 break;
756 case SHADER_OPCODE_SAMPLEINFO:
757 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
758 break;
759 default:
760 unreachable("not reached");
761 }
762 } else {
763 switch (inst->opcode) {
764 case SHADER_OPCODE_TEX:
765 /* Note that G45 and older determines shadow compare and dispatch width
766 * from message length for most messages.
767 */
768 if (inst->exec_size == 8) {
769 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
770 if (inst->shadow_compare) {
771 assert(inst->mlen == 6);
772 } else {
773 assert(inst->mlen <= 4);
774 }
775 } else {
776 if (inst->shadow_compare) {
777 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
778 assert(inst->mlen == 9);
779 } else {
780 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
781 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
782 }
783 }
784 break;
785 case FS_OPCODE_TXB:
786 if (inst->shadow_compare) {
787 assert(inst->exec_size == 8);
788 assert(inst->mlen == 6);
789 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
790 } else {
791 assert(inst->mlen == 9);
792 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
793 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
794 }
795 break;
796 case SHADER_OPCODE_TXL:
797 if (inst->shadow_compare) {
798 assert(inst->exec_size == 8);
799 assert(inst->mlen == 6);
800 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
801 } else {
802 assert(inst->mlen == 9);
803 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
804 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
805 }
806 break;
807 case SHADER_OPCODE_TXD:
808 /* There is no sample_d_c message; comparisons are done manually */
809 assert(inst->exec_size == 8);
810 assert(inst->mlen == 7 || inst->mlen == 10);
811 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
812 break;
813 case SHADER_OPCODE_TXF:
814 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
815 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
816 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
817 break;
818 case SHADER_OPCODE_TXS:
819 assert(inst->mlen == 3);
820 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
821 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
822 break;
823 default:
824 unreachable("not reached");
825 }
826 }
827 assert(msg_type != -1);
828
829 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
830 dst = vec16(dst);
831 }
832
833 assert(devinfo->gen < 7 || inst->header_size == 0 ||
834 src.file == BRW_GENERAL_REGISTER_FILE);
835
836 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
837
838 /* Load the message header if present. If there's a texture offset,
839 * we need to set it up explicitly and load the offset bitfield.
840 * Otherwise, we can use an implied move from g0 to the first message reg.
841 */
842 if (inst->header_size != 0) {
843 if (devinfo->gen < 6 && !inst->offset) {
844 /* Set up an implied move from g0 to the MRF. */
845 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
846 } else {
847 struct brw_reg header_reg;
848
849 if (devinfo->gen >= 7) {
850 header_reg = src;
851 } else {
852 assert(inst->base_mrf != -1);
853 header_reg = brw_message_reg(inst->base_mrf);
854 }
855
856 brw_push_insn_state(p);
857 brw_set_default_exec_size(p, BRW_EXECUTE_8);
858 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
859 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
860 /* Explicitly set up the message header by copying g0 to the MRF. */
861 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
862
863 if (inst->offset) {
864 /* Set the offset bits in DWord 2. */
865 brw_MOV(p, get_element_ud(header_reg, 2),
866 brw_imm_ud(inst->offset));
867 } else if (stage != MESA_SHADER_VERTEX &&
868 stage != MESA_SHADER_FRAGMENT) {
869 /* The vertex and fragment stages have g0.2 set to 0, so
870 * header0.2 is 0 when g0 is copied. Other stages may not, so we
871 * must set it to 0 to avoid setting undesirable bits in the
872 * message.
873 */
874 brw_MOV(p, get_element_ud(header_reg, 2), brw_imm_ud(0));
875 }
876
877 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
878 brw_pop_insn_state(p);
879 }
880 }
881
882 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
883 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
884 ? prog_data->binding_table.gather_texture_start
885 : prog_data->binding_table.texture_start;
886
887 if (surface_index.file == BRW_IMMEDIATE_VALUE &&
888 sampler_index.file == BRW_IMMEDIATE_VALUE) {
889 uint32_t surface = surface_index.ud;
890 uint32_t sampler = sampler_index.ud;
891
892 brw_SAMPLE(p,
893 retype(dst, BRW_REGISTER_TYPE_UW),
894 inst->base_mrf,
895 src,
896 surface + base_binding_table_index,
897 sampler % 16,
898 msg_type,
899 inst->size_written / REG_SIZE,
900 inst->mlen,
901 inst->header_size != 0,
902 simd_mode,
903 return_format);
904
905 brw_mark_surface_used(prog_data, surface + base_binding_table_index);
906 } else {
907 /* Non-const sampler index */
908
909 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
910 struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
911 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
912
913 brw_push_insn_state(p);
914 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
915 brw_set_default_access_mode(p, BRW_ALIGN_1);
916
917 if (brw_regs_equal(&surface_reg, &sampler_reg)) {
918 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
919 } else {
920 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
921 brw_OR(p, addr, addr, surface_reg);
922 }
923 if (base_binding_table_index)
924 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
925 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
926
927 brw_pop_insn_state(p);
928
929 /* dst = send(offset, a0.0 | <descriptor>) */
930 brw_inst *insn = brw_send_indirect_message(
931 p, BRW_SFID_SAMPLER, dst, src, addr);
932 brw_set_sampler_message(p, insn,
933 0 /* surface */,
934 0 /* sampler */,
935 msg_type,
936 inst->size_written / REG_SIZE,
937 inst->mlen /* mlen */,
938 inst->header_size != 0 /* header */,
939 simd_mode,
940 return_format);
941
942 /* visitor knows more than we do about the surface limit required,
943 * so has already done marking.
944 */
945 }
946
947 if (is_combined_send) {
948 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
949 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
950 }
951 }
952
953
954 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
955 * looking like:
956 *
957 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
958 *
959 * Ideally, we want to produce:
960 *
961 * DDX DDY
962 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
963 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
964 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
965 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
966 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
967 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
968 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
969 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
970 *
971 * and add another set of two more subspans if in 16-pixel dispatch mode.
972 *
973 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
974 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
975 * pair. But the ideal approximation may impose a huge performance cost on
976 * sample_d. On at least Haswell, sample_d instruction does some
977 * optimizations if the same LOD is used for all pixels in the subspan.
978 *
979 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
980 * appropriate swizzling.
981 */
982 void
983 fs_generator::generate_ddx(enum opcode opcode,
984 struct brw_reg dst, struct brw_reg src)
985 {
986 unsigned vstride, width;
987
988 if (opcode == FS_OPCODE_DDX_FINE) {
989 /* produce accurate derivatives */
990 vstride = BRW_VERTICAL_STRIDE_2;
991 width = BRW_WIDTH_2;
992 } else {
993 /* replicate the derivative at the top-left pixel to other pixels */
994 vstride = BRW_VERTICAL_STRIDE_4;
995 width = BRW_WIDTH_4;
996 }
997
998 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
999 src.negate, src.abs,
1000 BRW_REGISTER_TYPE_F,
1001 vstride,
1002 width,
1003 BRW_HORIZONTAL_STRIDE_0,
1004 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1005 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1006 src.negate, src.abs,
1007 BRW_REGISTER_TYPE_F,
1008 vstride,
1009 width,
1010 BRW_HORIZONTAL_STRIDE_0,
1011 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1012 brw_ADD(p, dst, src0, negate(src1));
1013 }
1014
1015 /* The negate_value boolean is used to negate the derivative computation for
1016 * FBOs, since they place the origin at the upper left instead of the lower
1017 * left.
1018 */
1019 void
1020 fs_generator::generate_ddy(enum opcode opcode,
1021 struct brw_reg dst, struct brw_reg src)
1022 {
1023 if (opcode == FS_OPCODE_DDY_FINE) {
1024 /* produce accurate derivatives */
1025 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1026 src.negate, src.abs,
1027 BRW_REGISTER_TYPE_F,
1028 BRW_VERTICAL_STRIDE_4,
1029 BRW_WIDTH_4,
1030 BRW_HORIZONTAL_STRIDE_1,
1031 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
1032 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1033 src.negate, src.abs,
1034 BRW_REGISTER_TYPE_F,
1035 BRW_VERTICAL_STRIDE_4,
1036 BRW_WIDTH_4,
1037 BRW_HORIZONTAL_STRIDE_1,
1038 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
1039 brw_push_insn_state(p);
1040 brw_set_default_access_mode(p, BRW_ALIGN_16);
1041 brw_ADD(p, dst, negate(src0), src1);
1042 brw_pop_insn_state(p);
1043 } else {
1044 /* replicate the derivative at the top-left pixel to other pixels */
1045 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1046 src.negate, src.abs,
1047 BRW_REGISTER_TYPE_F,
1048 BRW_VERTICAL_STRIDE_4,
1049 BRW_WIDTH_4,
1050 BRW_HORIZONTAL_STRIDE_0,
1051 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1052 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
1053 src.negate, src.abs,
1054 BRW_REGISTER_TYPE_F,
1055 BRW_VERTICAL_STRIDE_4,
1056 BRW_WIDTH_4,
1057 BRW_HORIZONTAL_STRIDE_0,
1058 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1059 brw_ADD(p, dst, negate(src0), src1);
1060 }
1061 }
1062
1063 void
1064 fs_generator::generate_discard_jump(fs_inst *inst)
1065 {
1066 assert(devinfo->gen >= 6);
1067
1068 /* This HALT will be patched up at FB write time to point UIP at the end of
1069 * the program, and at brw_uip_jip() JIP will be set to the end of the
1070 * current block (or the program).
1071 */
1072 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1073 gen6_HALT(p);
1074 }
1075
1076 void
1077 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1078 {
1079 /* The 32-wide messages only respect the first 16-wide half of the channel
1080 * enable signals which are replicated identically for the second group of
1081 * 16 channels, so we cannot use them unless the write is marked
1082 * force_writemask_all.
1083 */
1084 const unsigned lower_size = inst->force_writemask_all ? inst->exec_size :
1085 MIN2(16, inst->exec_size);
1086 const unsigned block_size = 4 * lower_size / REG_SIZE;
1087 assert(inst->mlen != 0);
1088
1089 brw_push_insn_state(p);
1090 brw_set_default_exec_size(p, cvt(lower_size) - 1);
1091 brw_set_default_compression(p, lower_size > 8);
1092
1093 for (unsigned i = 0; i < inst->exec_size / lower_size; i++) {
1094 brw_set_default_group(p, inst->group + lower_size * i);
1095
1096 brw_MOV(p, brw_uvec_mrf(lower_size, inst->base_mrf + 1, 0),
1097 retype(offset(src, block_size * i), BRW_REGISTER_TYPE_UD));
1098
1099 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1100 block_size,
1101 inst->offset + block_size * REG_SIZE * i);
1102 }
1103
1104 brw_pop_insn_state(p);
1105 }
1106
1107 void
1108 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1109 {
1110 assert(inst->exec_size <= 16 || inst->force_writemask_all);
1111 assert(inst->mlen != 0);
1112
1113 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1114 inst->exec_size / 8, inst->offset);
1115 }
1116
1117 void
1118 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1119 {
1120 assert(inst->exec_size <= 16 || inst->force_writemask_all);
1121
1122 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1123 }
1124
1125 void
1126 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1127 struct brw_reg dst,
1128 struct brw_reg index,
1129 struct brw_reg offset)
1130 {
1131 assert(inst->mlen != 0);
1132
1133 assert(index.file == BRW_IMMEDIATE_VALUE &&
1134 index.type == BRW_REGISTER_TYPE_UD);
1135 uint32_t surf_index = index.ud;
1136
1137 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1138 offset.type == BRW_REGISTER_TYPE_UD);
1139 uint32_t read_offset = offset.ud;
1140
1141 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1142 read_offset, surf_index);
1143 }
1144
1145 void
1146 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1147 struct brw_reg dst,
1148 struct brw_reg index,
1149 struct brw_reg offset)
1150 {
1151 assert(index.type == BRW_REGISTER_TYPE_UD);
1152
1153 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1154 /* Reference just the dword we need, to avoid angering validate_reg(). */
1155 offset = brw_vec1_grf(offset.nr, 0);
1156
1157 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1158 * the destination loaded consecutively from the same offset (which appears
1159 * in the first component, and the rest are ignored).
1160 */
1161 dst.width = BRW_WIDTH_4;
1162
1163 struct brw_reg src = offset;
1164 bool header_present = false;
1165
1166 if (devinfo->gen >= 9) {
1167 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1168 src = retype(brw_vec4_grf(offset.nr, 0), BRW_REGISTER_TYPE_UD);
1169 header_present = true;
1170
1171 brw_push_insn_state(p);
1172 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1173 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1174 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1175 brw_set_default_access_mode(p, BRW_ALIGN_1);
1176
1177 brw_MOV(p, get_element_ud(src, 2),
1178 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1179 brw_pop_insn_state(p);
1180 }
1181
1182 if (index.file == BRW_IMMEDIATE_VALUE) {
1183
1184 uint32_t surf_index = index.ud;
1185
1186 brw_push_insn_state(p);
1187 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1188 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1189 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1190 brw_inst_set_exec_size(devinfo, send, BRW_EXECUTE_4);
1191 brw_pop_insn_state(p);
1192
1193 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UD));
1194 brw_set_src0(p, send, src);
1195 brw_set_sampler_message(p, send,
1196 surf_index,
1197 0, /* LD message ignores sampler unit */
1198 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1199 1, /* rlen */
1200 inst->mlen,
1201 header_present,
1202 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1203 0);
1204 } else {
1205
1206 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1207
1208 brw_push_insn_state(p);
1209 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1210 brw_set_default_access_mode(p, BRW_ALIGN_1);
1211
1212 /* a0.0 = surf_index & 0xff */
1213 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1214 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1215 brw_set_dest(p, insn_and, addr);
1216 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1217 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1218
1219 /* dst = send(payload, a0.0 | <descriptor>) */
1220 brw_inst *insn = brw_send_indirect_message(
1221 p, BRW_SFID_SAMPLER, dst, src, addr);
1222 brw_set_sampler_message(p, insn,
1223 0,
1224 0, /* LD message ignores sampler unit */
1225 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1226 1, /* rlen */
1227 inst->mlen,
1228 header_present,
1229 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1230 0);
1231
1232 brw_pop_insn_state(p);
1233 }
1234 }
1235
1236 void
1237 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst *inst,
1238 struct brw_reg dst,
1239 struct brw_reg index)
1240 {
1241 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1242 assert(inst->header_size != 0);
1243 assert(inst->mlen);
1244
1245 assert(index.file == BRW_IMMEDIATE_VALUE &&
1246 index.type == BRW_REGISTER_TYPE_UD);
1247 uint32_t surf_index = index.ud;
1248
1249 uint32_t simd_mode, rlen, msg_type;
1250 if (inst->exec_size == 16) {
1251 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1252 rlen = 8;
1253 } else {
1254 assert(inst->exec_size == 8);
1255 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1256 rlen = 4;
1257 }
1258
1259 if (devinfo->gen >= 5)
1260 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1261 else {
1262 /* We always use the SIMD16 message so that we only have to load U, and
1263 * not V or R.
1264 */
1265 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1266 assert(inst->mlen == 3);
1267 assert(inst->size_written == 8 * REG_SIZE);
1268 rlen = 8;
1269 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1270 }
1271
1272 struct brw_reg header = brw_vec8_grf(0, 0);
1273 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1274
1275 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1276 brw_inst_set_compression(devinfo, send, false);
1277 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1278 brw_set_src0(p, send, header);
1279 if (devinfo->gen < 6)
1280 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1281
1282 /* Our surface is set up as floats, regardless of what actual data is
1283 * stored in it.
1284 */
1285 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1286 brw_set_sampler_message(p, send,
1287 surf_index,
1288 0, /* sampler (unused) */
1289 msg_type,
1290 rlen,
1291 inst->mlen,
1292 inst->header_size != 0,
1293 simd_mode,
1294 return_format);
1295 }
1296
1297 void
1298 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1299 struct brw_reg dst,
1300 struct brw_reg index,
1301 struct brw_reg offset)
1302 {
1303 assert(devinfo->gen >= 7);
1304 /* Varying-offset pull constant loads are treated as a normal expression on
1305 * gen7, so the fact that it's a send message is hidden at the IR level.
1306 */
1307 assert(inst->header_size == 0);
1308 assert(!inst->mlen);
1309 assert(index.type == BRW_REGISTER_TYPE_UD);
1310
1311 uint32_t simd_mode, rlen, mlen;
1312 if (inst->exec_size == 16) {
1313 mlen = 2;
1314 rlen = 8;
1315 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1316 } else {
1317 assert(inst->exec_size == 8);
1318 mlen = 1;
1319 rlen = 4;
1320 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1321 }
1322
1323 if (index.file == BRW_IMMEDIATE_VALUE) {
1324
1325 uint32_t surf_index = index.ud;
1326
1327 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1328 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1329 brw_set_src0(p, send, offset);
1330 brw_set_sampler_message(p, send,
1331 surf_index,
1332 0, /* LD message ignores sampler unit */
1333 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1334 rlen,
1335 mlen,
1336 false, /* no header */
1337 simd_mode,
1338 0);
1339
1340 } else {
1341
1342 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1343
1344 brw_push_insn_state(p);
1345 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1346 brw_set_default_access_mode(p, BRW_ALIGN_1);
1347
1348 /* a0.0 = surf_index & 0xff */
1349 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1350 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1351 brw_set_dest(p, insn_and, addr);
1352 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1353 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1354
1355 brw_pop_insn_state(p);
1356
1357 /* dst = send(offset, a0.0 | <descriptor>) */
1358 brw_inst *insn = brw_send_indirect_message(
1359 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1360 offset, addr);
1361 brw_set_sampler_message(p, insn,
1362 0 /* surface */,
1363 0 /* sampler */,
1364 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1365 rlen /* rlen */,
1366 mlen /* mlen */,
1367 false /* header */,
1368 simd_mode,
1369 0);
1370 }
1371 }
1372
1373 /**
1374 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1375 * into the flags register (f0.0).
1376 *
1377 * Used only on Gen6 and above.
1378 */
1379 void
1380 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1381 {
1382 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1383 struct brw_reg dispatch_mask;
1384
1385 if (devinfo->gen >= 6)
1386 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1387 else
1388 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1389
1390 brw_push_insn_state(p);
1391 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1392 brw_MOV(p, flags, dispatch_mask);
1393 brw_pop_insn_state(p);
1394 }
1395
1396 void
1397 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1398 struct brw_reg dst,
1399 struct brw_reg src,
1400 struct brw_reg msg_data,
1401 unsigned msg_type)
1402 {
1403 assert(inst->size_written % REG_SIZE == 0);
1404 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1405
1406 brw_pixel_interpolator_query(p,
1407 retype(dst, BRW_REGISTER_TYPE_UW),
1408 src,
1409 inst->pi_noperspective,
1410 msg_type,
1411 msg_data,
1412 inst->mlen,
1413 inst->size_written / REG_SIZE);
1414 }
1415
1416
1417 /**
1418 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1419 * sampler LD messages.
1420 *
1421 * We don't want to bake it into the send message's code generation because
1422 * that means we don't get a chance to schedule the instructions.
1423 */
1424 void
1425 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1426 struct brw_reg dst,
1427 struct brw_reg value)
1428 {
1429 assert(value.file == BRW_IMMEDIATE_VALUE);
1430
1431 brw_push_insn_state(p);
1432 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1433 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1434 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1435 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1436 brw_pop_insn_state(p);
1437 }
1438
1439 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1440 * the ADD instruction.
1441 */
1442 void
1443 fs_generator::generate_set_sample_id(fs_inst *inst,
1444 struct brw_reg dst,
1445 struct brw_reg src0,
1446 struct brw_reg src1)
1447 {
1448 assert(dst.type == BRW_REGISTER_TYPE_D ||
1449 dst.type == BRW_REGISTER_TYPE_UD);
1450 assert(src0.type == BRW_REGISTER_TYPE_D ||
1451 src0.type == BRW_REGISTER_TYPE_UD);
1452
1453 struct brw_reg reg = stride(src1, 1, 4, 0);
1454 if (devinfo->gen >= 8 || inst->exec_size == 8) {
1455 brw_ADD(p, dst, src0, reg);
1456 } else if (inst->exec_size == 16) {
1457 brw_push_insn_state(p);
1458 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1459 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1460 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1461 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1462 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1463 brw_pop_insn_state(p);
1464 }
1465 }
1466
1467 void
1468 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1469 struct brw_reg dst,
1470 struct brw_reg x,
1471 struct brw_reg y)
1472 {
1473 assert(devinfo->gen >= 7);
1474 assert(dst.type == BRW_REGISTER_TYPE_UD);
1475 assert(x.type == BRW_REGISTER_TYPE_F);
1476 assert(y.type == BRW_REGISTER_TYPE_F);
1477
1478 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1479 *
1480 * Because this instruction does not have a 16-bit floating-point type,
1481 * the destination data type must be Word (W).
1482 *
1483 * The destination must be DWord-aligned and specify a horizontal stride
1484 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1485 * each destination channel and the upper word is not modified.
1486 */
1487 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1488
1489 /* Give each 32-bit channel of dst the form below, where "." means
1490 * unchanged.
1491 * 0x....hhhh
1492 */
1493 brw_F32TO16(p, dst_w, y);
1494
1495 /* Now the form:
1496 * 0xhhhh0000
1497 */
1498 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1499
1500 /* And, finally the form of packHalf2x16's output:
1501 * 0xhhhhllll
1502 */
1503 brw_F32TO16(p, dst_w, x);
1504 }
1505
1506 void
1507 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1508 struct brw_reg dst,
1509 struct brw_reg src)
1510 {
1511 assert(devinfo->gen >= 7);
1512 assert(dst.type == BRW_REGISTER_TYPE_F);
1513 assert(src.type == BRW_REGISTER_TYPE_UD);
1514
1515 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1516 *
1517 * Because this instruction does not have a 16-bit floating-point type,
1518 * the source data type must be Word (W). The destination type must be
1519 * F (Float).
1520 */
1521 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1522
1523 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1524 * For the Y case, we wish to access only the upper word; therefore
1525 * a 16-bit subregister offset is needed.
1526 */
1527 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1528 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1529 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1530 src_w.subnr += 2;
1531
1532 brw_F16TO32(p, dst, src_w);
1533 }
1534
1535 void
1536 fs_generator::generate_shader_time_add(fs_inst *inst,
1537 struct brw_reg payload,
1538 struct brw_reg offset,
1539 struct brw_reg value)
1540 {
1541 assert(devinfo->gen >= 7);
1542 brw_push_insn_state(p);
1543 brw_set_default_mask_control(p, true);
1544
1545 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1546 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1547 offset.type);
1548 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1549 value.type);
1550
1551 assert(offset.file == BRW_IMMEDIATE_VALUE);
1552 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1553 value.width = BRW_WIDTH_1;
1554 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1555 value.vstride = BRW_VERTICAL_STRIDE_0;
1556 } else {
1557 assert(value.file == BRW_IMMEDIATE_VALUE);
1558 }
1559
1560 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1561 * case, and we don't really care about squeezing every bit of performance
1562 * out of this path, so we just emit the MOVs from here.
1563 */
1564 brw_MOV(p, payload_offset, offset);
1565 brw_MOV(p, payload_value, value);
1566 brw_shader_time_add(p, payload,
1567 prog_data->binding_table.shader_time_start);
1568 brw_pop_insn_state(p);
1569
1570 brw_mark_surface_used(prog_data,
1571 prog_data->binding_table.shader_time_start);
1572 }
1573
1574 void
1575 fs_generator::enable_debug(const char *shader_name)
1576 {
1577 debug_flag = true;
1578 this->shader_name = shader_name;
1579 }
1580
1581 int
1582 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1583 {
1584 /* align to 64 byte boundary. */
1585 while (p->next_insn_offset % 64)
1586 brw_NOP(p);
1587
1588 this->dispatch_width = dispatch_width;
1589
1590 int start_offset = p->next_insn_offset;
1591 int spill_count = 0, fill_count = 0;
1592 int loop_count = 0;
1593
1594 struct annotation_info annotation;
1595 memset(&annotation, 0, sizeof(annotation));
1596
1597 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1598 struct brw_reg src[3], dst;
1599 unsigned int last_insn_offset = p->next_insn_offset;
1600 bool multiple_instructions_emitted = false;
1601
1602 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1603 * "Register Region Restrictions" section: for BDW, SKL:
1604 *
1605 * "A POW/FDIV operation must not be followed by an instruction
1606 * that requires two destination registers."
1607 *
1608 * The documentation is often lacking annotations for Atom parts,
1609 * and empirically this affects CHV as well.
1610 */
1611 if (devinfo->gen >= 8 &&
1612 p->nr_insn > 1 &&
1613 brw_inst_opcode(devinfo, brw_last_inst) == BRW_OPCODE_MATH &&
1614 brw_inst_math_function(devinfo, brw_last_inst) == BRW_MATH_FUNCTION_POW &&
1615 inst->dst.component_size(inst->exec_size) > REG_SIZE) {
1616 brw_NOP(p);
1617 last_insn_offset = p->next_insn_offset;
1618 }
1619
1620 if (unlikely(debug_flag))
1621 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1622
1623 /* If the instruction writes to more than one register, it needs to be
1624 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1625 * hardware figures out by itself what the right compression mode is,
1626 * but we still need to know whether the instruction is compressed to
1627 * set up the source register regions appropriately.
1628 *
1629 * XXX - This is wrong for instructions that write a single register but
1630 * read more than one which should strictly speaking be treated as
1631 * compressed. For instructions that don't write any registers it
1632 * relies on the destination being a null register of the correct
1633 * type and regioning so the instruction is considered compressed
1634 * or not accordingly.
1635 */
1636 const bool compressed =
1637 inst->dst.component_size(inst->exec_size) > REG_SIZE;
1638 brw_set_default_compression(p, compressed);
1639 brw_set_default_group(p, inst->group);
1640
1641 for (unsigned int i = 0; i < inst->sources; i++) {
1642 src[i] = brw_reg_from_fs_reg(inst, &inst->src[i], devinfo->gen,
1643 compressed);
1644
1645 /* The accumulator result appears to get used for the
1646 * conditional modifier generation. When negating a UD
1647 * value, there is a 33rd bit generated for the sign in the
1648 * accumulator value, so now you can't check, for example,
1649 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1650 */
1651 assert(!inst->conditional_mod ||
1652 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1653 !inst->src[i].negate);
1654 }
1655 dst = brw_reg_from_fs_reg(inst, &inst->dst, devinfo->gen, compressed);
1656
1657 brw_set_default_access_mode(p, BRW_ALIGN_1);
1658 brw_set_default_predicate_control(p, inst->predicate);
1659 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1660 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1661 brw_set_default_saturate(p, inst->saturate);
1662 brw_set_default_mask_control(p, inst->force_writemask_all);
1663 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1664 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1665
1666 assert(inst->force_writemask_all || inst->exec_size >= 4);
1667 assert(inst->force_writemask_all || inst->group % inst->exec_size == 0);
1668 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1669 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1670
1671 switch (inst->opcode) {
1672 case BRW_OPCODE_MOV:
1673 brw_MOV(p, dst, src[0]);
1674 break;
1675 case BRW_OPCODE_ADD:
1676 brw_ADD(p, dst, src[0], src[1]);
1677 break;
1678 case BRW_OPCODE_MUL:
1679 brw_MUL(p, dst, src[0], src[1]);
1680 break;
1681 case BRW_OPCODE_AVG:
1682 brw_AVG(p, dst, src[0], src[1]);
1683 break;
1684 case BRW_OPCODE_MACH:
1685 brw_MACH(p, dst, src[0], src[1]);
1686 break;
1687
1688 case BRW_OPCODE_LINE:
1689 brw_LINE(p, dst, src[0], src[1]);
1690 break;
1691
1692 case BRW_OPCODE_MAD:
1693 assert(devinfo->gen >= 6);
1694 brw_set_default_access_mode(p, BRW_ALIGN_16);
1695 brw_MAD(p, dst, src[0], src[1], src[2]);
1696 break;
1697
1698 case BRW_OPCODE_LRP:
1699 assert(devinfo->gen >= 6);
1700 brw_set_default_access_mode(p, BRW_ALIGN_16);
1701 brw_LRP(p, dst, src[0], src[1], src[2]);
1702 break;
1703
1704 case BRW_OPCODE_FRC:
1705 brw_FRC(p, dst, src[0]);
1706 break;
1707 case BRW_OPCODE_RNDD:
1708 brw_RNDD(p, dst, src[0]);
1709 break;
1710 case BRW_OPCODE_RNDE:
1711 brw_RNDE(p, dst, src[0]);
1712 break;
1713 case BRW_OPCODE_RNDZ:
1714 brw_RNDZ(p, dst, src[0]);
1715 break;
1716
1717 case BRW_OPCODE_AND:
1718 brw_AND(p, dst, src[0], src[1]);
1719 break;
1720 case BRW_OPCODE_OR:
1721 brw_OR(p, dst, src[0], src[1]);
1722 break;
1723 case BRW_OPCODE_XOR:
1724 brw_XOR(p, dst, src[0], src[1]);
1725 break;
1726 case BRW_OPCODE_NOT:
1727 brw_NOT(p, dst, src[0]);
1728 break;
1729 case BRW_OPCODE_ASR:
1730 brw_ASR(p, dst, src[0], src[1]);
1731 break;
1732 case BRW_OPCODE_SHR:
1733 brw_SHR(p, dst, src[0], src[1]);
1734 break;
1735 case BRW_OPCODE_SHL:
1736 brw_SHL(p, dst, src[0], src[1]);
1737 break;
1738 case BRW_OPCODE_F32TO16:
1739 assert(devinfo->gen >= 7);
1740 brw_F32TO16(p, dst, src[0]);
1741 break;
1742 case BRW_OPCODE_F16TO32:
1743 assert(devinfo->gen >= 7);
1744 brw_F16TO32(p, dst, src[0]);
1745 break;
1746 case BRW_OPCODE_CMP:
1747 if (inst->exec_size >= 16 && devinfo->gen == 7 && !devinfo->is_haswell &&
1748 dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1749 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1750 * implemented in the compiler is not sufficient. Overriding the
1751 * type when the destination is the null register is necessary but
1752 * not sufficient by itself.
1753 */
1754 assert(dst.nr == BRW_ARF_NULL);
1755 dst.type = BRW_REGISTER_TYPE_D;
1756 }
1757 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1758 break;
1759 case BRW_OPCODE_SEL:
1760 brw_SEL(p, dst, src[0], src[1]);
1761 break;
1762 case BRW_OPCODE_BFREV:
1763 assert(devinfo->gen >= 7);
1764 /* BFREV only supports UD type for src and dst. */
1765 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1766 retype(src[0], BRW_REGISTER_TYPE_UD));
1767 break;
1768 case BRW_OPCODE_FBH:
1769 assert(devinfo->gen >= 7);
1770 /* FBH only supports UD type for dst. */
1771 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1772 break;
1773 case BRW_OPCODE_FBL:
1774 assert(devinfo->gen >= 7);
1775 /* FBL only supports UD type for dst. */
1776 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1777 break;
1778 case BRW_OPCODE_LZD:
1779 brw_LZD(p, dst, src[0]);
1780 break;
1781 case BRW_OPCODE_CBIT:
1782 assert(devinfo->gen >= 7);
1783 /* CBIT only supports UD type for dst. */
1784 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1785 break;
1786 case BRW_OPCODE_ADDC:
1787 assert(devinfo->gen >= 7);
1788 brw_ADDC(p, dst, src[0], src[1]);
1789 break;
1790 case BRW_OPCODE_SUBB:
1791 assert(devinfo->gen >= 7);
1792 brw_SUBB(p, dst, src[0], src[1]);
1793 break;
1794 case BRW_OPCODE_MAC:
1795 brw_MAC(p, dst, src[0], src[1]);
1796 break;
1797
1798 case BRW_OPCODE_BFE:
1799 assert(devinfo->gen >= 7);
1800 brw_set_default_access_mode(p, BRW_ALIGN_16);
1801 brw_BFE(p, dst, src[0], src[1], src[2]);
1802 break;
1803
1804 case BRW_OPCODE_BFI1:
1805 assert(devinfo->gen >= 7);
1806 brw_BFI1(p, dst, src[0], src[1]);
1807 break;
1808 case BRW_OPCODE_BFI2:
1809 assert(devinfo->gen >= 7);
1810 brw_set_default_access_mode(p, BRW_ALIGN_16);
1811 brw_BFI2(p, dst, src[0], src[1], src[2]);
1812 break;
1813
1814 case BRW_OPCODE_IF:
1815 if (inst->src[0].file != BAD_FILE) {
1816 /* The instruction has an embedded compare (only allowed on gen6) */
1817 assert(devinfo->gen == 6);
1818 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1819 } else {
1820 brw_IF(p, brw_inst_exec_size(devinfo, p->current));
1821 }
1822 break;
1823
1824 case BRW_OPCODE_ELSE:
1825 brw_ELSE(p);
1826 break;
1827 case BRW_OPCODE_ENDIF:
1828 brw_ENDIF(p);
1829 break;
1830
1831 case BRW_OPCODE_DO:
1832 brw_DO(p, brw_inst_exec_size(devinfo, p->current));
1833 break;
1834
1835 case BRW_OPCODE_BREAK:
1836 brw_BREAK(p);
1837 break;
1838 case BRW_OPCODE_CONTINUE:
1839 brw_CONT(p);
1840 break;
1841
1842 case BRW_OPCODE_WHILE:
1843 brw_WHILE(p);
1844 loop_count++;
1845 break;
1846
1847 case SHADER_OPCODE_RCP:
1848 case SHADER_OPCODE_RSQ:
1849 case SHADER_OPCODE_SQRT:
1850 case SHADER_OPCODE_EXP2:
1851 case SHADER_OPCODE_LOG2:
1852 case SHADER_OPCODE_SIN:
1853 case SHADER_OPCODE_COS:
1854 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1855 if (devinfo->gen >= 6) {
1856 assert(inst->mlen == 0);
1857 assert(devinfo->gen >= 7 || inst->exec_size == 8);
1858 gen6_math(p, dst, brw_math_function(inst->opcode),
1859 src[0], brw_null_reg());
1860 } else {
1861 assert(inst->mlen >= 1);
1862 assert(devinfo->gen == 5 || devinfo->is_g4x || inst->exec_size == 8);
1863 gen4_math(p, dst,
1864 brw_math_function(inst->opcode),
1865 inst->base_mrf, src[0],
1866 BRW_MATH_PRECISION_FULL);
1867 }
1868 break;
1869 case SHADER_OPCODE_INT_QUOTIENT:
1870 case SHADER_OPCODE_INT_REMAINDER:
1871 case SHADER_OPCODE_POW:
1872 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1873 if (devinfo->gen >= 6) {
1874 assert(inst->mlen == 0);
1875 assert((devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) ||
1876 inst->exec_size == 8);
1877 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1878 } else {
1879 assert(inst->mlen >= 1);
1880 assert(inst->exec_size == 8);
1881 gen4_math(p, dst, brw_math_function(inst->opcode),
1882 inst->base_mrf, src[0],
1883 BRW_MATH_PRECISION_FULL);
1884 }
1885 break;
1886 case FS_OPCODE_CINTERP:
1887 brw_MOV(p, dst, src[0]);
1888 break;
1889 case FS_OPCODE_LINTERP:
1890 generate_linterp(inst, dst, src);
1891 break;
1892 case FS_OPCODE_PIXEL_X:
1893 assert(src[0].type == BRW_REGISTER_TYPE_UW);
1894 src[0].subnr = 0 * type_sz(src[0].type);
1895 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
1896 break;
1897 case FS_OPCODE_PIXEL_Y:
1898 assert(src[0].type == BRW_REGISTER_TYPE_UW);
1899 src[0].subnr = 4 * type_sz(src[0].type);
1900 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
1901 break;
1902 case FS_OPCODE_GET_BUFFER_SIZE:
1903 generate_get_buffer_size(inst, dst, src[0], src[1]);
1904 break;
1905 case SHADER_OPCODE_TEX:
1906 case FS_OPCODE_TXB:
1907 case SHADER_OPCODE_TXD:
1908 case SHADER_OPCODE_TXF:
1909 case SHADER_OPCODE_TXF_LZ:
1910 case SHADER_OPCODE_TXF_CMS:
1911 case SHADER_OPCODE_TXF_CMS_W:
1912 case SHADER_OPCODE_TXF_UMS:
1913 case SHADER_OPCODE_TXF_MCS:
1914 case SHADER_OPCODE_TXL:
1915 case SHADER_OPCODE_TXL_LZ:
1916 case SHADER_OPCODE_TXS:
1917 case SHADER_OPCODE_LOD:
1918 case SHADER_OPCODE_TG4:
1919 case SHADER_OPCODE_TG4_OFFSET:
1920 case SHADER_OPCODE_SAMPLEINFO:
1921 generate_tex(inst, dst, src[0], src[1], src[2]);
1922 break;
1923 case FS_OPCODE_DDX_COARSE:
1924 case FS_OPCODE_DDX_FINE:
1925 generate_ddx(inst->opcode, dst, src[0]);
1926 break;
1927 case FS_OPCODE_DDY_COARSE:
1928 case FS_OPCODE_DDY_FINE:
1929 generate_ddy(inst->opcode, dst, src[0]);
1930 break;
1931
1932 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1933 generate_scratch_write(inst, src[0]);
1934 spill_count++;
1935 break;
1936
1937 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1938 generate_scratch_read(inst, dst);
1939 fill_count++;
1940 break;
1941
1942 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1943 generate_scratch_read_gen7(inst, dst);
1944 fill_count++;
1945 break;
1946
1947 case SHADER_OPCODE_MOV_INDIRECT:
1948 generate_mov_indirect(inst, dst, src[0], src[1]);
1949 break;
1950
1951 case SHADER_OPCODE_URB_READ_SIMD8:
1952 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1953 generate_urb_read(inst, dst, src[0]);
1954 break;
1955
1956 case SHADER_OPCODE_URB_WRITE_SIMD8:
1957 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1958 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1959 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1960 generate_urb_write(inst, src[0]);
1961 break;
1962
1963 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1964 assert(inst->force_writemask_all);
1965 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1966 break;
1967
1968 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1969 assert(inst->force_writemask_all);
1970 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1971 break;
1972
1973 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
1974 generate_varying_pull_constant_load_gen4(inst, dst, src[0]);
1975 break;
1976
1977 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1978 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1979 break;
1980
1981 case FS_OPCODE_REP_FB_WRITE:
1982 case FS_OPCODE_FB_WRITE:
1983 generate_fb_write(inst, src[0]);
1984 break;
1985
1986 case FS_OPCODE_FB_READ:
1987 generate_fb_read(inst, dst, src[0]);
1988 break;
1989
1990 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1991 generate_mov_dispatch_to_flags(inst);
1992 break;
1993
1994 case FS_OPCODE_DISCARD_JUMP:
1995 generate_discard_jump(inst);
1996 break;
1997
1998 case SHADER_OPCODE_SHADER_TIME_ADD:
1999 generate_shader_time_add(inst, src[0], src[1], src[2]);
2000 break;
2001
2002 case SHADER_OPCODE_UNTYPED_ATOMIC:
2003 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2004 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud,
2005 inst->mlen, !inst->dst.is_null());
2006 break;
2007
2008 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2009 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2010 brw_untyped_surface_read(p, dst, src[0], src[1],
2011 inst->mlen, src[2].ud);
2012 break;
2013
2014 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
2015 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2016 brw_untyped_surface_write(p, src[0], src[1],
2017 inst->mlen, src[2].ud);
2018 break;
2019
2020 case SHADER_OPCODE_TYPED_ATOMIC:
2021 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2022 brw_typed_atomic(p, dst, src[0], src[1],
2023 src[2].ud, inst->mlen, !inst->dst.is_null());
2024 break;
2025
2026 case SHADER_OPCODE_TYPED_SURFACE_READ:
2027 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2028 brw_typed_surface_read(p, dst, src[0], src[1],
2029 inst->mlen, src[2].ud);
2030 break;
2031
2032 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
2033 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2034 brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].ud);
2035 break;
2036
2037 case SHADER_OPCODE_MEMORY_FENCE:
2038 brw_memory_fence(p, dst);
2039 break;
2040
2041 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2042 generate_set_simd4x2_offset(inst, dst, src[0]);
2043 break;
2044
2045 case SHADER_OPCODE_FIND_LIVE_CHANNEL: {
2046 const struct brw_reg mask =
2047 brw_stage_has_packed_dispatch(devinfo, stage,
2048 prog_data) ? brw_imm_ud(~0u) :
2049 stage == MESA_SHADER_FRAGMENT ? brw_vmask_reg() :
2050 brw_dmask_reg();
2051 brw_find_live_channel(p, dst, mask);
2052 break;
2053 }
2054
2055 case SHADER_OPCODE_BROADCAST:
2056 assert(inst->force_writemask_all);
2057 brw_broadcast(p, dst, src[0], src[1]);
2058 break;
2059
2060 case FS_OPCODE_SET_SAMPLE_ID:
2061 generate_set_sample_id(inst, dst, src[0], src[1]);
2062 break;
2063
2064 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2065 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2066 break;
2067
2068 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2069 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2070 generate_unpack_half_2x16_split(inst, dst, src[0]);
2071 break;
2072
2073 case FS_OPCODE_PLACEHOLDER_HALT:
2074 /* This is the place where the final HALT needs to be inserted if
2075 * we've emitted any discards. If not, this will emit no code.
2076 */
2077 if (!patch_discard_jumps_to_fb_writes()) {
2078 if (unlikely(debug_flag)) {
2079 annotation.ann_count--;
2080 }
2081 }
2082 break;
2083
2084 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2085 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2086 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2087 break;
2088
2089 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2090 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2091 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2092 break;
2093
2094 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2095 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2096 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2097 break;
2098
2099 case CS_OPCODE_CS_TERMINATE:
2100 generate_cs_terminate(inst, src[0]);
2101 break;
2102
2103 case SHADER_OPCODE_BARRIER:
2104 generate_barrier(inst, src[0]);
2105 break;
2106
2107 case BRW_OPCODE_DIM:
2108 assert(devinfo->is_haswell);
2109 assert(src[0].type == BRW_REGISTER_TYPE_DF);
2110 assert(dst.type == BRW_REGISTER_TYPE_DF);
2111 brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
2112 break;
2113
2114 default:
2115 unreachable("Unsupported opcode");
2116
2117 case SHADER_OPCODE_LOAD_PAYLOAD:
2118 unreachable("Should be lowered by lower_load_payload()");
2119 }
2120
2121 if (multiple_instructions_emitted)
2122 continue;
2123
2124 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2125 assert(p->next_insn_offset == last_insn_offset + 16 ||
2126 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2127 "emitting more than 1 instruction");
2128
2129 brw_inst *last = &p->store[last_insn_offset / 16];
2130
2131 if (inst->conditional_mod)
2132 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2133 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2134 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2135 }
2136 }
2137
2138 brw_set_uip_jip(p, start_offset);
2139 annotation_finalize(&annotation, p->next_insn_offset);
2140
2141 #ifndef NDEBUG
2142 bool validated = brw_validate_instructions(p, start_offset, &annotation);
2143 #else
2144 if (unlikely(debug_flag))
2145 brw_validate_instructions(p, start_offset, &annotation);
2146 #endif
2147
2148 int before_size = p->next_insn_offset - start_offset;
2149 brw_compact_instructions(p, start_offset, annotation.ann_count,
2150 annotation.ann);
2151 int after_size = p->next_insn_offset - start_offset;
2152
2153 if (unlikely(debug_flag)) {
2154 fprintf(stderr, "Native code for %s\n"
2155 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2156 " bytes (%.0f%%)\n",
2157 shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
2158 spill_count, fill_count, promoted_constants, before_size, after_size,
2159 100.0f * (before_size - after_size) / before_size);
2160
2161 dump_assembly(p->store, annotation.ann_count, annotation.ann,
2162 p->devinfo);
2163 ralloc_free(annotation.mem_ctx);
2164 }
2165 assert(validated);
2166
2167 compiler->shader_debug_log(log_data,
2168 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2169 "%d:%d spills:fills, Promoted %u constants, "
2170 "compacted %d to %d bytes.",
2171 _mesa_shader_stage_to_abbrev(stage),
2172 dispatch_width, before_size / 16,
2173 loop_count, cfg->cycle_count, spill_count,
2174 fill_count, promoted_constants, before_size,
2175 after_size);
2176
2177 return start_offset;
2178 }
2179
2180 const unsigned *
2181 fs_generator::get_assembly(unsigned int *assembly_size)
2182 {
2183 return brw_get_program(p, assembly_size);
2184 }